Debug registers 0 to 3 (DR0, DR1, DR2, and DR3) are used to store virtual (linear) addresses of the so-called hardware breakpoints.
- Preface
- Intel Architecture
- Setting Up a Development Environment
- Intel Instruction Set Architecture (ISA)
- Memory Addressing Modes
- Parallel Data Processing
- Macro Instructions
- Data Structures
- Mixing Modules Written in Assembly and Those Written in High-Level Languages
- Operating System Interface
- Patching Legacy Code
- Oh, Almost Forgot
Debug address registers DR0 - DR3
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