Processors based on the Intel architecture have a set of control registers that are used for configuration of the processor at run time (such as switching between execution modes). These registers are 32-bit wide on x86 and 64-bit wide on AMD64 (long mode).

There are six control registers and one Extended Feature Enable Register (EFER):

• CR0: This register contains various control flags that modify the basic operation of the processor.
• CR1: This register is reserved for future use.
• CR2: This register contains the Page Fault Linear Address when a page fault occurs.
• CR3: This register is used when virtual addressing is enabled (paging) and contains the physical address of the page directory, page directory pointer table, or page map level 4 table, depending on the current mode of operation.
• CR4: This register is used in the protected mode for controlling different options of the processor.
• CR8: This register is new and is only available in long mode. It is used for prioritization of external interrupts.
• EFER: This register is one of the several model-specific registers. It is used for enabling/disabling SYSCALL/SYSRET instructions, entering/exiting long mode, and a few other features. Other model-specific registers are of no interest for us.

However, these registers are not accessible in ring3 (user land).