8

Multilevel DC/AC Inverters

Multilevel inverters use a different method to construct DC/AC inverters. This idea was published by Nabae in 1980 in an IEEE international conference, IEEE APEC’80 [1], and the same idea was published in 1981 in IEEE Transactions on Industry Application [2]. Actually, multilevel inverters employ a different technique from the PWM method, which vertically chops a reference waveform to achieve the similar output waveform (e.g., a sine wave). The multilevel inverting technique horizontally accumulates levels to achieve the waveform (e.g., a sine wave).

The soft-switching technique has been implemented in DC/DC conversion for more than 20 years. We introduce this technique in DC/AC inverters in this chapter.

8.1    Introduction

Although PWM inverters have been used in industrial applications, they have many drawbacks:

1.  The carrier frequency must be very high. Mohan suggested mf > 21[3], which means fΔ > 1 kHz if the output waveform has frequency 50 Hz. Usually, in order to keep the THD small, fΔ is selected as 2–20 kHz [3].

2.  The pulse height is very high. In a normal PWM waveform (not multistage PWM), all pulse height is the DC linkage voltage. The output voltage of this PWM inverter has a large jumping span. For example, if the DC linkage voltage is 400 V, all pulses have the peak value 400 V. Usually, this causes large dv/dt and strong electromagnetic interference (EMI).

3.  The pulse width would be very narrow when the output voltage has a low value. For example, if the DC linkage voltage is 400 V, the output is 10 V, and the corresponding pulse width should be 2.5% of the pulse period.

4.  Terms 2 and 3 cause plenty of harmonics to produce poor THD.

5.  Terms 2 and 3 result In a very rigorous switching condition. The switching devices experience large switching power losses.

6.  The inverter control circuitry is complex, and the devices are costly. Therefore, the whole inverter is costly.

Multilevel inverters accumulate the output voltage in horizontal levels (layers). Therefore, using this technique overcomes the above drawbacks of the PWM technique:

1.  The switching frequencies of most switching devices are low, which are equal to or only a small multiple of the output signal frequency.

2.  The pulse heights are quite low. For an m-level inverter with output amplitude V_m, the pulse heights are V_m/m or only a small multiple of it. Usually, it causes low dv/dt and ignorable electromagnetic interference (EMI).

3.  The pulse widths of all pulses have reasonable values that are comparable to the output signal.

4.  Terms 2 and 3 cannot cause plenty of harmonics producing lower THD.

5.  Terms 2 and 3 offer smooth switching condition. The switching devices have small switching power losses.

6.  Inverter control circuitry is relatively simple, and the devices are not costly. Therefore, the inverter is economical.

Multilevel inverters contain several power switches and capacitors [4]. Output voltages of multilevel inverters are the sum of the voltages due to the commutation of the switches. Figure 8.1 shows one phase leg of inverters with different level numbers. A two-level inverter, as shown in Figure 8.1a, generates an output voltage with two levels with respect to the negative terminal of the capacitor. The three-level inverter shown in Figure 8.1b generates a three-level voltage, and an m-level inverter shown in Figure 8.1c generates an m-level voltage. Thus, the output voltages of multilevel inverters have several levels. Moreover, they can reach high voltage levels, while power semiconductors can withstand only lower voltages.

FIGURE 8.1
One phase leg of an inverter: (a) two levels, (b) three levels, and (c) m levels.

Multilevel inverters have been receiving increasing attention in recent decades, because of their many attractive features. Various kinds of multilevel inverters have been proposed, tested, and installed:

•  Diode-clamped (neutral-clamped) multilevel inverters

•  Capacitor-clamped (flying capacitors) multilevel inverters

•  Cascaded multilevel inverters with separate DC sources

•  H-bridge multilevel inverters

•  Generalized multilevel inverters

•  Mixed-level multilevel inverters

•  Multilevel inverters by the connection of three-phase two-level inverters

•  Soft-switched multilevel inverters

•  Laddered inverters

The family tree of multilevel level inverters is shown in Figure 8.2.

The family of multilevel inverters has emerged the solution for high power applications [4]. It is hard to be implemented via a single power semiconductor switch directly in medium-voltage networks. Multilevel inverters have been applied to different high-power applications, such as large motor drives, railway traction applications, high-voltage DC transmissions (HVDC), unified power flow controllers (UPFC), static VAR compensators (SVCs), and static synchronous compensators (STATCOMs). The output voltage of the multilevel inverter has many levels synthesized from several DC voltage sources. The quality of the output voltage is improved as the number of voltage levels increases, so the effort of output filters can be decreased. The transformers can be eliminated due to reduced voltage that the life of the switch increases. Moreover, being cost-effective solutions, the applications of multilevel inverters are also extended to medium- and low-power applications such as electrical vehicle propulsion systems, active power filters (APFs), voltage sag compensations, photovoltaic systems, and distributed power systems.

FIGURE 8.2
Family tree of multilevel inverters.

Multilevel inverter circuits have been investigated for three decades. Separate DC-sourced full-bridge cells are connected in series to synthesize a staircase AC output voltage. The diode-clamped inverter, also called the neutral-point clamped (NPC) inverter, was presented in 1980 by Nabae. Because the NPC inverter effectively doubles the device voltage level without requiring precise voltage matching, this circuit topology prevailed in the 1980s. The capacitor-clamped (also called flying capacitor) multilevel inverter was introduced in the 1990s. Although the cascaded multilevel inverter was invented earlier, its application did not become widespread until the mid 1990s. The advantages of cascaded multilevel inverters have been indicated for motor drives and utility applications. The cascaded inverter has drawn great interest due to the great demand for medium-voltage high-power inverters.

The cascaded inverter is also used in regenerative-type motor drive applications. Recently, some new topologies of multilevel inverters have emerged, such as generalized multilevel inverters, mixed multilevel inverters, hybrid multilevel inverters, and soft-switched multilevel inverters. Today, multilevel inverters are extensively used in high-power applications with medium voltage levels, such as laminators, mills, conveyors, pumps, fans, blowers, compressors, and so on. Moreover, as a cost-effective solution, the applications of multilevel inverters are also extended to low-power applications such as photovoltaic systems, hybrid electrical vehicles, and voltage sag compensation, in which the effort of output filter components can be greatly decreased due to low harmonic distortions of output voltages of the multilevel inverters.

8.2    Diode-Clamped Multilevel Inverters

In this category, the switching devices are connected in series to make up the desired voltage rating and output levels. The inner voltage points are clamped by either two extra diodes or one high-frequency capacitor. The switching devices of an m-level inverter are required to block a voltage level of V_dc/(m-1). The clamping diode needs different voltage ratings for different inner voltage levels. In summary, an m-level diode clamped inverter has

•  Number of power electronic switches = 2(m - 1)

•  Number of DC-link capacitors = (m - 1)

•  Number of clamped diodes = 2(m - 2)

•  Voltage across each DC-link capacitor = $\frac{V_{dc}}{m-1}$

where Vd_c is the DC-link voltage. A three-level diode-clamped inverter is shown in Figure 8.3a with V_dc = 2E. In this circuit, the DC-bus voltage is split into three levels by two series-connected bulk capacitors, C₁ and C₂. The middle point of the two capacitors, n, can be defined as the neutral point. The output voltage v_an has three states: E, 0, and -E. For voltage level E, switches S₁ and S₂ need to be turned on; for -E, switches S_1’ and S_2’ need to be turned on; and for the 0 level, S₂ and S_2’ need to be turned on.

The key components that distinguish this circuit from a conventional two-level inverter are D₁ and D_1’. These two diodes clamp the switch voltage to half the level of the DC-bus voltage. When both S₁ and S₂ turn on, the voltage across a and 0 is 2E, that is, v_a0 = 2E. In this case, D_1’ balances out the voltage sharing between S_1’ and S_2’ with S_1’ blocking the voltage across C₁ and S_2’ blocking the voltage across C₂. Notice that output voltage v_an is AC, and v_a0 is DC. The difference between v_an and v_a0 is the voltage across C₂, which is E. If the output is removed between a and 0, then the circuit becomes a DC/DC converter that has three output voltage levels: E, 0, and -E. The simulation waveform is shown in Figure 8.4.

FIGURE 8.3
Diode-clamped multilevel inverter circuit topologies: (a) three-level, (b) five-level, and (c) seven-level.

FIGURE 8.4
Output waveform of a three-level inverter.

Usually, as the number of levels increases, the corresponding THD of the output voltage decreases. The switching angle decides the THD of the output voltage as well. The three-level diode clamped inverter has the THD is shown in Table 8.1.

Figure 8.3b) shows a five-level diode-clamped converter in which the DC bus consists of four capacitors: C₁, C₂, C₃, and C₄. For DC bus voltage 4E, the voltage across each capacitor is E, and each device voltage stress will be limited to one capacitor voltage level E through clamping diodes.

TABLE 8.1
THD Content for Different Switching Angles (m = 3)

Methods	Switching Angle (α1o)	THD
FFM	15°	31.76%
HHM	30°	30.9%

Note:  FFM is a feed-forward method and HHM is a half-height method, which will be discussed in Chapter 14.

To explain how the staircase voltage is synthesized, the neutral point n is considered as the output phase voltage reference point. There are five switch combinations to synthesize five level voltage across a and n:

•  For voltage level v_an = 2E, turn on all upper switches S₁–S₄.

•  For voltage level v_an = E, turn on three upper switches S₂–S₄ and one lower switch S_1’.

•  For voltage level v_an = 0, turn on two upper switches S₃ and S₄ and two lower switches S_1’ and S₂’.

•  For voltage level v_an = -E, turn on one upper switch S₄ and three lower switches S_1’ –S₃’.

•  For voltage level v_an = –2E, turn on all lower switches S_1’–S₄’.

For a diode-clamped inverter, each output level has only one combination to implement its output voltage. Four complementary switch pairs exist in each phase. The complementary switch pair is defined such that turning on one of the switches will exclude the other from being turned on. In this example, the four complementary pairs are (S₁, S_1’), (S₂, S₂), (S₃, S₃’), and (S₄, S₄’). Although each active switching device is only required to block a voltage level of E, the clamping diodes must have different voltage ratings for reverse voltage blocking. Using D_1’ of Figure 8.3b as an example, when lower devices S_2’–S₄’ are turned on, D_1’ needs to block three capacitor voltages, or 3E. Similarly, D₂ and D_2’ need to block 2E, and D₁ needs to block 3E.

The simulation waveform is shown in Figure 8.5 below.

FIGURE 8.5
Output waveform of a five-level inverter.

TABLE 8.2
THD Content for Different Switching Angles (m = 5)

Methods	Switching Angle α1(o)	Switching Angle α2 (o)	THD
FFM	7.24°	24.5°	24.86%
HHM	14.48°	49°	21.14%

The five-level diode-clamped inverter has the THD shown in Table 8.2.

A seven-level diode clamped inverter is shown in Figure 8.3c, and its output waveform is shown in Figure 8.6.

The seven-level diode-clamped inverter has the THD shown in Table 8.3.

From Figures 8.4 to 8.6, the THD is reduced when the number (m) of the level of the inverter is increased. Hence, a higher level inverter will produce output with less harmonic content. For each inverter, careful setting of the switching angles can obtain the best THD.

FIGURE 8.6
Output waveform of a seven-level inverter.

TABLE 8.3
THD Content for Different Switching Angles (m = 7)

Methods	α1	α2	α2	THD
FFM	4.8°	15°	28.22°	22.17%
HHM	9.6°	30°	56.44°	11.70%

8.3    Capacitor-Clamped Multilevel Inverters (Flying Capacitor Inverters)

Figure 8.7 illustrates the fundamental building block of a phase-leg capacitor-clamped inverter. The circuit has been called the flying capacitor inverter with dependent capacitors clamping the device voltage to one capacitor voltage level. The inverter in Figure 8.7a provides a three-level output across a and n, that is, v_an = E, 0, or -E. For the voltage level E, switches S₁ and S₂ need to be turned on; for -E, switches S_1’ and S₂’ need to be turned on; and for the 0 level, either pair (S₁, S_1’) or (S₂, S₂’) needs to be turned on. Clamping capacitor C₁ is charged when S₁ and S_1’ are turned on, and is discharged when S₂ and S_2’ are turned on. The charge of C₁ can be balanced by proper selection of the 0-level switch combination.

The voltage synthesis in a five-level capacitor-clamped inverter has more flexibility than a diode-clamped converter. Using Figure 8.7b as an example, the voltage of the five-level phase-leg a output with respect to the neutral point n, v_an, can be synthesized by the following switching combinations:

•  For voltage level v_an = 2E, turn on all upper switches S₁–S₄.

•  For voltage level v_an = E, there are three combinations:

•  S₁, S₂, S₃, S_1’: v_an = 2E (upper C₄) - E (C₁);

•  S₂, S₃, S₄, S_4’: v_an = 3E (C₃) - 2E (lower C₄); and

•  S₁, S₃, S₄, S₃’: v_an = 2E (upper C₄) - 3E (C₃) + 2E (C₂).

•  For voltage level v_an = 0, there are six combinations:

•  S₁, S₂, S_1’, S₄’: v_an = 2E (upper C₄) - 2E (C₂);

•  S₃, S₄, S_3’, S_4’: v_an = 2E (C₂) - 2E (lower C₄);

•  S₁, S₃, S_1’, S₃’: v_an = 2E (upper C₄) - 3E (C₃) + 2E (C₂) - E (C₁);

•  S₁, S₄, S_2’, S₃’: v_an = 2E (upper C₄) - 3E (C₃) + E (C₁);

•  S₂, S₄, S_2’, S₄’: v_an = 3E (C₃) - 2E (C₂) + E (C₁) - 2E (lower C₄); and

•  S₂, S₃, S_1’, S₄’: v_an = 3E (C₃) - E (C₁) - 2E (lower C₄).

•  For voltage level V_an = -E, there are three combinations:

•  S₁, S_1’, S_2’, S₃’: v_an = 2E (upper C₄) - 3E (C₃);

•  S₄, S_2’, S_3’, S₄’: v_an = E (C₁) - 2E (lower C₄); and

•  S₃, S_1’, S_3’, S_4’: v_an = 2E (C₂) - E (C₁) - 2E (lower C₄).

•  For voltage level v_an = -2E, turn on all lower switches, S_1’–S₄’.

FIGURE 8.7
Capacitor-clamped multilevel inverter circuit topologies: (a) three-level, (b) five-level, and (c) seven-level.

Usually, the positive top level and negative top level have only one combination to implement their output values. Other levels have various combinations to implement their output values. In the preceding description, the capacitors with positive signs are in discharging mode, while those with negative sign are in charging mode. By proper selection of capacitor combinations, it is possible to balance the capacitor charge.

Figure 8.7c shows the seven-level capacitor-clamped inverter. The readers can synthesize the switching combinations for each output voltage level.

8.4    Multilevel Inverters Using H-Bridges (HBs) Converters

The basic structure is based on the connection of H-bridges (HBs). Figure 8.8 shows the power circuit for one phase leg of a multilevel inverter with three HBs (HB₁, HB₂, and HB₃) in each phase. Each HB is supplied by a separate DC source. The resulting phase voltage is synthesized by the addition of the voltages generated by the different HBs. If the DC link voltages of HBs are identical, the multilevel inverter is called the cascaded multilevel inverter. Its output waveform is shown in Figure 8.9. However, it is possible to have different values among the DC link voltages of HBs, and the circuit can be called a hybrid multilevel inverter.

Example 9.3. A three-HB multilevel inverter is shown in Figure 8.8. The output voltage is v_an, which is shown in Figure 8.10. It is implemented as a binary hybrid multilevel inverter (BHMI). Explain the inverter’s working operation, and draw the corresponding waveforms, and indicate the source voltage’s arrangement and how many levels can be implemented.

FIGURE 8.8
Multilevel inverter based on the connection of HBs.

FIGURE 8.9
Waveforms of cascaded multilevel inverters.

Solution: The DC link voltages of HB_i (the ith HB),V_dci, is 2^i-1E. In a 3-HB one phase leg,

V_dc1 = E, V_dc2 = 2E, V_dc3, = 4E

FIGURE 8.10
Waveforms of binary hybrid multilevel inverter (BHMI).

The operation is listed as follows:

$\begin{array}{l}{\text{+0:\hspace{0.17em}v}}_{\text{H1}}{\text{=0,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}0,v}}_{\text{H3}}\text{=\hspace{0.17em}0,}\\ {\text{+1E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}E,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}0,v}}_{\text{H3}}\text{=\hspace{0.17em}0,}\\ {\text{+2E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}2E,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}0,}\\ {\text{+3E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}E,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}2E,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}0,}\\ {\text{+4E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}4E,}\\ {\text{+5E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}E,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}4E,}\\ {\text{+6E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}2E,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}4E,}\\ {\text{+7E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}E,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}2E,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}4E,}\\ -{\text{E:\hspace{0.17em}v}}_{\text{H1}}\text{=\hspace{0.17em}}-{\text{E,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}0,}\\ -{\text{2E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H2}}\text{=\hspace{0.17em}}-{\text{2E,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}0,}\\ -{\text{3E:\hspace{0.17em}v}}_{\text{H1}}\text{=\hspace{0.17em}}-{\text{E,\hspace{0.17em}v}}_{\text{H2}}\text{=\hspace{0.17em}}-{\text{2E,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}0,}\\ -{\text{4E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}-4E,}\\ -{\text{5E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}-E,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}-4E,}\\ -{\text{6E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}0,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}-2E,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}-4E,}\\ -{\text{7E:\hspace{0.17em}v}}_{\text{H1}}{\text{=\hspace{0.17em}-E,\hspace{0.17em}v}}_{\text{H2}}{\text{=\hspace{0.17em}-2E,\hspace{0.17em}v}}_{\text{H3}}\text{=\hspace{0.17em}-4E,}\end{array}$

As shown in Figure 8.10, the output waveform, v_an, has 15 levels. One of the advantages is that the HB with higher DC link voltage has a lower number of commutations and thereby reduces the associated switching losses. The higher switching frequency components, for example, IGBT, are used to construct the HB with lower DC link voltage.

8.4.1    Cascaded Equal Voltage Multilevel Inverters (CEMI)

In the cascaded equal voltage multilevel inverter, the DC link voltages of HBs are identical, as shown in Figure 8.8.

$V_{dc1}=V_{dc2}=V_{dc3}=E$

(8.1)

where E is the unit voltage. Each HB generates three voltages at the output: +E, 0, and -E. This is made possible by connecting the capacitors sequentially to the AC side via the three power switches. The resulting output AC voltage swings from -3E to 3E with seven levels as shown in Figure 8.9.

8.4.2    Binary Hybrid Multilevel Inverter (BHMI)

In the binary hybrid multilevel inverter (BHMI), the DC link voltages of HB_i (the ith HB), V_dci, is 2^i-1E. In a 3-HB one phase leg,

$V_{dc1}=E,V_{dc2}=2E,V_{dc3}=4E$

(8.2)

As shown in Figure 8.10, the output waveform, v_an,has 15 levels. One of the advantages is that the HB with higher DC link voltage has fewer commutations, thereby reducing the associated switching losses. The BHMI illustrates a seven-level (in half-cycle) inverter using this hybrid topology. The HB with higher DC link voltage consists of the lower switching frequency component. The higher switching frequency components, for example, the IGBT, are used to construct the HB with lower DC link voltage.

8.4.3    Quasi-Linear Multilevel Inverter (QLMI)

In the quasi-linear multilevel inverter, the DC link voltages of HB_i, be expressed as

$V_{dci}=\{\begin{array}{cc}E& i=1\\ 2\times 3^{i-2}E& i\ge 2\end{array}$

(8.3)

In a three-HB one-phase leg,

$V_{dc1}=E,V_{dc2}=2E,V_{dc3}=6E$

(8.4)

As shown in Figure 8.11, the output waveform, v_an, has 19 levels.

FIGURE 8.11
Waveforms of quasi-linear multilevel inverter.

FIGURE 8.12
Waveforms of a 27-level trinary hybrid multilevel inverter (THMI).

8.4.4    Trinary Hybrid Multilevel Inverter (THMI)

In a trinary hybrid multilevel inverter, the DC link voltages of HB_i, V_dci, are 3^i-1E. In a three-HB one phase leg,

$V_{dc1}=E{V}_{dc2}=3E{V}_{dc3}=9E$

(8.5)

As shown in Figure 8.12, the output waveform, v_an, has 27 levels. To the best of the authors’ knowledge, this circuit has the greatest level for a given number of HBs among existing multilevel inverters.

8.5    Other Kinds of Multilevel Inverters

Several other kinds of multilevel inverters are introduced in this subsection [5,6,7,8].

8.5.1    Generalized Multilevel Inverters (GMI)

A generalized multilevel inverter topology has previously been presented. The existing multilevel inverters, such as diode-clamped and capacitor-clamped multilevel inverters, can be derived from this generalized multilevel inverter topology. Moreover, the generalized multilevel inverter topology can balance each voltage level by itself regardless of load characteristics. Therefore, the generalized multilevel inverter topology provides a true multilevel structure that can balance each DC voltage level automatically at any number of levels, regardless of active or reactive power conversion, and without any assistance from other circuits. Thus, in principle, it provides a complete multilevel topology that embraces the existing multilevel inverters.

FIGURE 8.13
Generalized multilevel inverter structure.

Figure 8.13 shows the generalized multilevel inverter structure per phase leg. Each switching device, diode, or capacitor’s voltage is E, that is, 1/(m-1) of the DC link voltage. Any inverter with any number of levels, including the conventional two-level inverter, can be obtained using this generalized topology. As an application example, a four-level bidirectional DC/DC converter, shown in Figure 8.14, is suitable for the dual-voltage system to be adopted in future automobiles. The four-level DC/DC converter has a unique feature, which is that no magnetic components are needed. From this generalized multilevel inverter topology, several new multilevel inverter structures can be derived.

Figure 8.13 shows the generalized multilevel inverter structure per phase leg. Each switching device, diode, or capacitor’s voltage is E, that is, 1/(m-1) of the DC link voltage. Any inverter with any number of levels, including the conventional two-level inverter, can be obtained using this generalized topology. As an application example, a four-level bidirectional DC/DC converter, shown in Figure 8.14, is suitable for the dual-voltage system to be adopted in future automobiles. The four-level DC/DC converter has a unique feature, which is that no magnetic components are needed. From this generalized multilevel inverter topology, several new multilevel inverter structures can be derived.

8.5.2    Mixed-Level Multilevel Inverter Topologies

For high-voltage high-power applications, it is possible to adopt multilevel diode-clamped or capacitor-clamped inverters to replace the full-bridge cell in a cascaded multilevel inverter. The reason for doing so is to reduce the number of separate DC sources. The nine-level cascaded inverter requires 4 separate DC sources for one phase leg and 12 for a three-phase inverter. If a three-level inverter replaces the full-bridge cell, the voltage level is effectively doubled for each cell. Thus, to achieve the same nine voltage levels for each phase, only two separate DC sources are needed for one phase leg and six for a three-phase inverter. The configuration can be considered as having mixed-level multilevel cells because it embeds multilevel cells as the building block of the cascaded multilevel inverter.

FIGURE 8.14
Application example: a four-level inverter for the dual-voltage system in automobiles.

8.5.3    Multilevel Inverters by Connection of Three-Phase Two-Level Inverters

Standard three-phase two-level inverters are connected by transformers as shown in Figure 8.15. In order for the inverter output voltages to be added up, the inverter outputs of the three modules need to be synchronized with a separation of 120° between each phase. For example, obtaining a three-level voltage between outputs a and b, the voltage is synthesized by V_ab = V_a1-b1 + V_a1-b1 + V_a1-b1. The phase between b₁ and a₂ is provided by a₃ and b₃ through an isolated transformer. With three inverters synchronized, the voltages V_a1-b1, V_a1-b1, and V_a1-b1 are all in phase; thus, the output level is simply tripled.

FIGURE 8.15
Cascaded inverter with three-phase cells.

References

1.  Nabae, A., Takahashi, I., and Akagi, H. 1980. A neutral-point clamped PWM inverter. Proc. IEEE APEC’80 Conf., pp. 761–766.

2.  Nabae, A., Takahashi, I., and Akagi, H. 1981. A neutral-point clamped PWM inverter. IEEE Trans. Ind. Applicat., pp. 518–523.

3.  Mohan, N., Undeland, T. M., and Robbins, W. P. 2003. Power Electronics: Converters, Applications and Design. New York: John Wiley & Sons.

4.  Liu, Y. and Luo, F. L. 2008. Trinary hybrid 81-level multilevel inverter for motor drive with zero common-mode voltage. IEEE Trans. Ind. Electron., pp. 1014–1021.

5.  Manjrekar, M. D., Steimer, P. K., and Lipo, T. A. 2000. Hybrid multilevel power conversion system: a competitive solution for high-power applications. IEEE Trans. Ind. Applicat., pp. 834–841.

6.  Akagi, H. 2006. Medium-voltage power conversion systems in the next generation. Proc. IEEE-IPEMC’2006, pp. 23–30.

7.  Inoue, S. and Akagi, H. 2007. A bidirectional isolated DC–DC converter as a core circuit of the next-generation medium-voltage power conversion system. IEEE Trans. Power Electron., pp. 535–542.

8.  Liu, Y. and Luo, F. L. 2006. Multilevel inverter with the ability of self voltage balancing. IEE Proc. Electric Power Applicat., pp. 105–115.