7

Soft-Switching DC/AC Inverters

The soft-switching technique has been implemented in DC/DC conversion for more than 25 years. We also would like to introduce this technique in DC/AC inverters in this chapter.

There are numerous ways of implementing soft-switching methods, such as zero voltage switching (ZVS) and zero current switching (ZCS), to reduce the switching losses and to increase efficiency for different multilevel inverters. For the cascaded multilevel inverter, because each inverter cell is a two-level circuit, the implementation of soft switching is not at all different from that of conventional two-level inverters. For capacitor- or diode-clamped inverters, however, the choices of soft switching circuit involve different circuit combinations. Although zero current switching is possible, most approaches in the literature propose zero voltage switching types, including auxiliary resonant commutated pole (ARCP), coupled inductor with zero voltage transition (ZVT), and their combinations.

7.1    Notched DC Link Inverters for Brushless DC Motor Drive

The brushless DC motor (BDCM) has been widely used in industrial applications because of its low inertia, fast response, high power density, and high reliability, because of which it is maintenance-free. It exhibits the operating characteristics of a conventional commutated DC permanent magnet motor but eliminates the mechanical commutator and brushes. Hence, many problems associated with brushes are eliminated, such as radio-frequency interference and sparking, which is the potential source of ignition in an inflammable atmosphere. It is usually supplied by a hard-switching PWM inverter, which normally has low efficiency since the power losses across the switching devices are high. In order to reduce the losses, many soft-switching inverters have been designed [1].

The soft-switching operation of power inverters has attracted much attention in recent decades. In electric motor drive applications, soft-switching inverters are usually classified into three categories, namely, resonant pole inverters, resonant DC link inverters, and resonant AC link inverters [2]. The resonant pole inverter has the disadvantage of containing a large number of additional components, in comparison to other hard- and soft-switching inverter topologies. The resonant AC link inverter is not suitable for BDCM drivers.

In medium-power applications, the resonant DC link concept [3] offered a first practical and reliable way to reduce commutation losses and to eliminate individual snubbers. Thus, it allows high operating frequencies and improved efficiency. In this inverter, it is quite simple to get the zero voltage switching (ZVS) condition of the six main switches just by adding one auxiliary switch. However, the inverter has the drawbacks of high voltage stress of the switches and high voltage ripple of the DC link, the frequency of the inverter being related to the resonant frequency. Furthermore, the inductor power losses of the inverter are also considerable as current always flows in the inductor. In order to overcome the drawback of high voltage stress of the switches, the actively clamped resonant DC link inverter was introduced [4,5,6,7]. The control scheme of the inverter is exceedingly complex and the output contains subharmonics, which, in some cases, cannot be accepted. These inverters still do not overcome the drawback of high inductor power losses.

In order to generate voltage notches of the DC link at controllable instants and reduce the power losses of the inductor, several quasi-parallel resonant schemes were proposed [8,9,10]. As a dwell time is generally required after every notch, severe interference occurs, mainly in multiphase inverters, appreciably worsening the modulation quality. A novel DC-rail parallel resonant zero voltage transition (ZVT) voltage source inverter [11] was introduced that overcame many of the drawbacks mentioned earlier. However, it requires two ZVTs per PWM cycle, which lowers the output and limits the switch frequency of the inverter.

On the other hand, the majority of soft-switching inverters proposed in recent years have been aimed at induction motor drive applications. So it is necessary to research the novel topology of the soft-switching inverter and the special control circuit for BDCM drive systems. This chapter proposes a novel resonant DC link inverter for the BDCM drive system that can generate voltage notches of the DC link at controllable instants and widths. And the inverter possesses the advantages of low switching power loss, low inductor power loss, low voltage ripple of the DC link, low device voltage stress, and a simple control scheme.

The construction of the soft-switching inverter is shown in Figure 7.1. At the front is an uncontrolled rectifier for DC supply. The input AC supply can be single phase for low/medium power or three phases for medium/high power. It contains a resonant circuit, a conventional and control circuit. The resonant circuit contains three auxiliary switches (one IGBT and two fast switching thyristors), a resonant inductor, and a resonant capacitor. All auxiliary switches work under ZVS or zero current switching (ZCS) condition. It generates voltage notches of the DC link to guarantee that the main switches S₁–S₆ of the inverter will operate in ZVS condition. The fast-switching thyristor is the appropriate device as an auxiliary switch. We need not control the turn-off of a thyristor, because it has higher surge current capability than any other power semiconductor switch.

FIGURE 7.1
The construction of soft-switching for the BDCM drive system.

7.1.1    Resonant Circuit

The resonant circuit consists of three auxiliary switches, one resonant inductor, and one resonant capacitor. The auxiliary switches are controlled at a certain instant for resonance between inductor and capacitor. Thus, the voltage of the DC link reaches zero temporarily (voltage notch), and the main switches of the inverter reach assumed ZVS condition for commutation.

Since the resonant process is very short, the load current can be assumed constant. The equivalent resonant circuit is shown in Figure 7.2. The corresponding waveforms of the auxiliary switches gate signal, resonant capacitor voltage (u_Cr), inductor current (i_Lr), and current of switch S_L (i_SL) are shown in Figure 7.3. The operation of the ZVT process can be divided into six modes.

FIGURE 7.2
The equivalent resonant circuit.

FIGURE 7.3
Some waveforms of the equivalent circuit.

Mode 0 (as shown in Figure 7.4a) 0 < t < t₀. Its operation is the same as that of the conventional inverter. Current flows from the DC source through S_L to the load. The voltage across C_r (u_Cr) is equal to the supply voltage (V_s). The auxiliary switches S_a and S_b are in the off state.

Mode 1 (as shown in Figure 7.4b) t₀ < t < t₁. At the instant of phase current commutation or when the PWM signal is flipped from 1 to 0, thyristor S_a is fired (ZCS turns on due to L_r) and IGBT S_L is turned off (ZVS turns off due to C_r) at the same time. Capacitor C_r resonates with inductor L_r, and the voltage across capacitor C_r is decreased. Redefining the initial time, we have the equation

$\{{}_{I_0-i_{Lr}(t)+C_r\frac{d{u}_{cr}(t)}{dt}=0}^{u_{Cr}(t)+R_{Lr}{i}_{Lr}(t)+L_r\frac{d{i}_{Lr}(t)}{dt}=\frac{V_S}{2}}$

(7.1)

FIGURE 7.4
Operation mode of the zero voltage switching process.

R_Lr is the resistance of inductor L_r, I₀ is the load current, V_S is the DC power supply voltage, with initial condition u_cr (0) = V_S, i_Lr (0) = 0. Solving Equation (7.1), we get

$\{\begin{array}{c}\begin{array}{l}{u}_{Cr}(t)=\left(\frac{V_S}{2}-R_{Lr}{I}_0\right)+\left(\frac{V_s}{2}-R_{Lr}{I}_0\right)e^{-\frac{t}{\tau }}\cos (\omega t)\\ +\frac{1}{L_r{C}_r\omega }{e}^{-\frac{t}{\tau }}\left(\frac{1}{4}{R}_{Lr}{C}_r{V}_S-L_r{L}_0+\frac{1}{2}{R}_{Lr}^2{C}_{r}I\right)\sin (\omega t)\end{array}\\ i_{Lr}(t)=I_0-I_0{e}^{-\frac{t}{\tau }}\cos (\omega t)-\frac{V_S+R_{Lr}{I}_0}{2_{Lr}\omega }{e}^{-\frac{t}{\tau }}\sin (\omega t)\end{array}$

(7.2)

where

$\tau =\frac{2L_r}{R_{Lr}},\text{ω=}\sqrt{\frac{1}{L_r{C}_r}-\frac{1}{{\tau }^2}.}$

As the resonant frequency is very high (several hundred kHz), ωL_r >> R_Lr, and the resonant inductor resistance R_Lr can be neglected. Then Equation (7.2) can be simplified as

$\{\begin{array}{c}{u}_{Cr}(t)=\frac{V_S}{2}-I_0\sqrt{\frac{L_r}{C_r}}\sin \left(\frac{1}{\sqrt{L_r{C}_r}}t\right)+\frac{V_S}{2}\cos \left(\frac{1}{\sqrt{L_r{C}_r}}\right)\\ i_{Lr}(t)=I_0-I_0\cos \left(\frac{1}{\sqrt{L_r{C}_r}}t\right)-\frac{V_S}{2}\sqrt{\frac{C_r}{L_r}}\sin \left(\frac{1}{\sqrt{L_r{C}_r}}t\right)\end{array}$

(7.3)

That is,

$\{\begin{array}{c}{u}_{Cr}(t)=\frac{V_S}{2}+K\cos (\omega ,t+\alpha )\\ i_{Lr}(t)=I_0-K\sqrt{\frac{C_r}{L_r}}\sin (\omega ,t+\alpha )\end{array}$

(7.4)

where

$K=\sqrt{\frac{V_S^2}{4}+\frac{I_0^2{L}_r}{C_r},}{\text{ω}}_r=\sqrt{\frac{1}{L_r{C}_r}},\text{α}=t{g}^{-1}\left(\frac{2I_0}{V_S}\sqrt{\frac{L_r}{C_r}}\right)$

Letting u_Cr(t) = 0, we get

$\text{Δ}{T}_1=t_1-t_0=\frac{\text{π}-2\text{α}}{{\text{ω}}_r}$

(7.5)

i_Lr(t₁) is zero at the same time. Then thyristor S_a turns itself off.

Mode 2 (as shown in Figure 7.4c) t₁ < t < t₂. None of the auxiliary switches is fired, and the voltage of the DC link (u_Cr) is zero. The main switches of the inverter can now be either turned on or turned off under ZVS condition during the interval. Load current flows through the freewheeling diode D.

Mode 3 (as shown in Figure 7.4d) t₂ < t < t₃. As the main switches have turned on or off, thyristor S_b is fired (ZCS turns on due to L_r), and i_Lr starts to build up linearly in the auxiliary branch. The current in the freewheeling diode D begins to fall linearly. The load current is slowly diverted from the freewheeling diodes to the resonant branch. But u_Cr is still equal to zero. We have

$\text{Δ}{T}_2=t_3-t_2=\frac{2I_0{L}_r}{V_S}$

(7.6)

At t₃, i_Lr equals the load current I₀, and the current through the diode becomes zero. Thus, the freewheeling diode turns off under zero-current condition.

Mode 4 (as shown in Figure 7.4e) t₃ < t < t₄. i_Lr is increased continuously from I₀ and u_Cr is increased from zero when the freewheeling diode D is turned off. Redefining the initial time, we can get the same equation as Equation (7.1). But the initial condition is u_Cr (0) = 0, i_Lr (0) = I₀. Neglecting the inductor resistance and solving the equation, we get

$\{\begin{array}{c}{u}_{Cr}(t)=\frac{V_S}{2}-\frac{V_S}{2}\cos \left(\frac{1}{\sqrt{L_r{C}_r}}t\right)\\ i_{Lr}(t)=I_0+\frac{V_S}{2}\sqrt{\frac{C_r}{L_r}}\sin \left(\frac{1}{\sqrt{L_r{C}_r}}t\right)\end{array}$

(7.7)

That is,

$\{\begin{array}{c}{u}_{Cr}(t)=\frac{V_S}{2}[1-\cos ({\text{ω}}_{r}t)]\\ i_{Lr}(t)=I_0+\frac{V_S}{2}\sqrt{\frac{C_r}{L_r}}\sin (\text{ω}rt)\end{array}$

(7.8)

When

$\text{Δ}T=t_4-t_3=\frac{\text{π}}{{\text{ω}}_r}$

(7.9)

u_Cr = E, IGBT S_L is fired (ZVS turn on), and i_Lr = I₀ again. The peak inductor current can be derived from Equation (7.8) as

$i_{Lr-m}=I_0+\frac{V_S}{2}\sqrt{\frac{C_r}{L_r}}$

(7.10)

Mode 5 (as shown in Figure 7.4f) t₄ < t < t₅. When the DC link voltage is equal to the supply voltage, auxiliary switch S_L is turned on (ZVS turns on due to C_r). i_lr decreases linear from I₀ to zero at t₅, and the thyristor S_b turns itself off.

Then the device returns to mode 0 again. The operation principle of the other procedure is the same as for a conventional inverter.

7.1.2    Design Considerations

The design of the resonant circuit is to determine the resonant capacitor C_r, resonant inductor L_r, and the switching instants of auxiliary switches S_a, S_b, and S_L. It is assumed that the inductance of BDCM is much higher than the resonant inductance L_r From the analysis presented previously, the design considerations can be summarized as follows:

The auxiliary switch S_L works under ZVS condition, and the voltage stress is the DC power supply voltage V_S. The current flow through it is load current. The auxiliary switches S_a and S_b work under ZCS condition, the voltage stress is V_S/2, and the peak current flow through them is i_Lr-m. As the resonant auxiliary switches S_a and S_b carry peak current only during switch transitions, they can be rated for a lower continuous current rating.

The resonant period is expressed as $T_r=1/f_r=2\text{π}\sqrt{L_r{C}_r}$; for a high-switching frequency inverter, T_r should be as short as possible. For getting the expected T_r, the resonant inductor and capacitor values have to be selected. The first component to be designed is the resonant inductor. A small inductance value can ensure small T_r, but the rising slope of the inductor current di_Lr/dt = V_S/2L_r should be small enough to guarantee freewheeling diode turn-off. For a 600V to 1200V power diode, the reverse recovery time is about 50 to 200 ns, the rule to select an inductor is given by

$\frac{d{i}_{Lr}}{dt}=\frac{V_S}{2L_r}=75~150A/\text{μs}$

(7.11)

Certainly, inductance is as high as possible. This implies that a high inductance value is necessary. Thus, an optimum value of the inductance has to be chosen that would reduce the inductor current rise slope, while keeping T_r small enough.

The capacitance value is inversely proportional to the ascending or descending slope of the DC link voltage. This means the capacitance is as high as possible for switch S_L to get ZVS condition, but as the capacitance increases, more and more energy is stored in it. This energy should be charged or discharged via a resonant inductor; with high capacitance, the peak value of inductor current will be high. The peak value of i_Lr should be limited to twice the peak load current. From Equations (7.3),(7.4),(7.5),(7.6),(7.7),(7.8),(7.9),(7.10), we obtain

$\sqrt{\frac{C_r}{L_r}}\le \frac{2I_{0\max }}{V_S}$

(7.12)

Thus, an optimum value of the capacitance has to be chosen that would limit the peak inductor current, while the ascending or descending slope of the DC link voltage is low enough.

7.1.3    Control Scheme

When the duty of PWM is 100%, that is, there is no PWM, the main switches of the inverter work under the commutation frequency. When it is time to commutate the phase current of the BDCM, we control the auxiliary switches S_a, S_b, and S_L, and resonance occurs between L_r and C_r. The voltage of the DC link reaches zero temporarily; thus, ZVS condition of the main switches is obtained. When the duty of the PWM is less than 100%, the auxiliary switch S_L works as a chopper. The main switches of the inverter do not switch on within a PWM cycle when the phase current need not commutate. It has the benefit of reducing the phase current drop when the PWM is off. The phase current is commutated when the DC link voltage becomes zero. So there is only one DC link voltage notch per PWM cycle. It is very important, especially for very low or very high duty of PWM, where the interval between two voltage notches is very short or even overlapped which will limit the tuning range.

The commutation logical circuit of the system is shown in Figure 7.5. It is similar to the conventional BDCM commutation logical circuit except that six D flip-flops are added to the output. Thus, the gate signal of the main switches is controlled by the synchronous pulse CK, which will be mentioned later, and the commutation can be synchronized with the auxiliary switches’ control circuit. The operation of the inverter can be divided into PWM operation and non-PWM operation.

FIGURE 7.5
Commutation logical circuit for main switches.

7.1.3.1    Non-PWM Operation

When the duty of PWM is 100%, that is, there is no PWM, the whole ZVT process (mode 1–mode 5) occurs when the phase current commutation is under way. The control scheme for the auxiliary switches in this operation is illustrated in Figure 7.6a. When mode 1 begins, the pulse signal for thyristor S_a is generated by a monostable flip-flop, and the gate signal for IGBT S_L drops to a low level (i.e., turns off the S_L) at the same time. Then the pulse signal for thyristor S_b and the synchronous pulse CK can be obtained after two short delays (delay 1 and delay 2, respectively). Obviously, delay 1 is longer than delay 2. Pulse CK is generated during mode 2 when the voltage of DC link is zero and the main switches of the inverter get ZVS condition. Then modes 3, 4, and 5 occur and the voltage of DC link is increased to that of the supply again.

FIGURE 7.6
Control scheme for the auxiliary switches in (a) non-PWM operation and (b) PWM operation.

7.1.3.2    PWM Operation

In this operation, the auxiliary switch S_L works as a chopper, but the main switches of the inverter do not turn on or off within a single PWM cycle when the phase current need not commutate. The load current is commutated when the DC link voltage becomes zero, that is, when the PWM signal is 0 (as the PWM cycle is very short, it does not affect the operation of the motor). The control scheme for the auxiliary switches in PWM operation is illustrated in Figure 7.6b.

•  When the PWM signal is flipped from 1 to 0, mode 1 begins, the pulse signal for thyristor S_a is generated, and the gate signal for IGBT S_L drops to a low level. But the voltage of the DC link does not increase until the PWM signal is flipped from 0 to 1. Pulse CK is generated during mode 2.

•  When the PWM signal is flipped from 0 to 1, mode 3 begins, and the pulse signal for thyristor S_b is generated (mode 3). Then when the voltage of the DC link is increased to E (voltage of supply), the gate signal for IGBT S_L is flipped to a high level (modes 4 and 5).

Thus, only one ZVT occurs per PWM cycle: modes 1 and 2 for PWM turned off, modes 3, 4, and 5 for PWM turned on. And the switching frequency would not be greater than the PWM frequency.

Normally, a drive system requires a speed or position feedback signal to get high speed or position precision and be less susceptible to disturbance of load and power supply. A speed feedback signal can be derived from a tachometer-generator, optical encoder, or resolver, or it can be derived from the rotor position sensor. The quadrature encoder pulse (QEP) is a standard digital speed or position signal and can be input to many devices (e.g., special DSP for drive system TMS320C24x has a QEP receive circuit). The QEP can be derived from the rotor position sensor of a BDCM easily. The converter digital circuit and interesting waveforms are shown in Figure 7.7. Some single-chip computers have a digital counter and may require only direction and pulse signals; thus, the converter circuit can be simplified. The circuit can be implemented with a complex programmer logical device and only occupies part of one chip. The circuit can also be implemented by a gate array logic IC (e.g., 16V8) and a D flip-flop IC (e.g., 74LS74). With the circuit, a high-precision speed or position signal can be obtained when the motor speed is high or the drive system has a high ratio speed reduction mechanism. In high-performance systems, the rotor position sensor may be a resolver or optical encoder, with special-purpose decoding circuitry. At this level of control sophistication, it is possible to fine-tune the firing angles and the PWM control as a function of speed and load, to improve various aspects of performance such as efficiency, dynamic performance, or speed range.

FIGURE 7.7
Circuit of derived QEP from Hall signal and waveforms.

7.1.4    Simulation and Experimental Results

The proposed topology is verified by Psim simulation software. The schematic circuit of the soft-switching inverter is shown in Figure 7.8. The left bottom of the figure is the auxiliary switches’ gate signal generator circuit (see Figure 7.6), which is made up of a monostable flip-flop, delay, and logical gate. The gate signals of auxiliary switches S_a and S_b in PWM and no-PWM operation modes are combined by an OR gate. The gate signal of S_L in the two operation modes is combined by an AND gate, and the synchronous signal (CK) is combined by a date selector. The middle bottom of the diagram shows the commutation logical circuit of the BDCM (see Figure 7.5); it is synchronized (by CK) with the auxiliary switches’ control circuit.

Waveforms of DC link voltage u_Cr, resonant inductor current i_Lr, BDCM phase current, inverter output line-line voltage, and gate signal of the auxiliary switches are shown in Figure 7.9. The resonant inductor L_r has an inductance of 10 μH, and the resonant capacitor C_r has a capacitance of 0.047 μF, so the period of the resonant circuit is about 4 μs. The frequency of the PWM is 20 kHz. From the figure, we can see that the output of the simulation matches the theoretical analysis. The waveforms in Figure 7.9b, d, e, f, g, and h are the same as in Figure 7.10.

In order to verify the theoretical analysis and simulation results, the proposed soft-switching inverter was tested on an experimental prototype rated as follows:

DC link voltage	240 V
Power of BDCM	3.3 Hp
Switching frequency	10 kHz

A polyester capacitor of 47 nF, 1500 V, was adopted as the DC link resonant capacitor C_r. The resonant inductor had an inductance of 6 μH/20 A, with a ferrite core. The design of the auxiliary switches’ control circuit was referenced from Figure 7.8. The monostable flip-flop can be implemented with IC 74LS123, the delay can be implemented by a Schmitt trigger and an RC circuit, and the logical gate can be replaced by a programmable logical device to reduce the number of ICs.

FIGURE 7.8
Schematic circuit of the drive system for Psim simulation.

FIGURE 7.9
Simulation results.

FIGURE 7.10
Voltage and current waveforms of switch S_L in hard-switching and soft-switching inverters.

The waveforms of voltage across the switch and current under hard switching and soft switching are shown in Figures 7.10a and 7.10b, respectively. All the voltage signals come from differential probes, and there is a gain of 20. For voltage waveforms, 5.00 V/div = 100 V/div, which is the same for Figure 7.11. It can also be seen that there is a considerable overlap between the voltage and current waveforms under hard switching. The overlap is much less with soft switching.

The key waveforms with soft switching inverter are shown in Figure 7.11. The default scale is as follows: DC link voltage: 100 V/div, current: 20 A/div. The default switching frequency is 10 kHz. The DC link voltage is fixed at 240 V. These experimental waveforms are similar to the simulation waveforms in Figure 7.9.

FIGURE 7.11
Experiment waveforms.

7.2    Resonant Pole Inverter

The resonant pole inverter is a soft-switching DC/AC inverter circuit and is shown in Figure 7.12. Each resonant pole comprises a resonant inductor and a pair of resonant capacitors at each phase leg. These capacitors are directly connected in parallel to the main inverter switches in order to achieve zero voltage switching (ZVS) condition. In contrast to the resonant DC link inverter, the DC link voltage remains unaffected during the resonant transitions. These transitions occur separately at each resonant pole when the corresponding main inverter switch needs switching. Therefore, the main switches in the inverter phase legs can switch independently of each other and choose the commutation instant freely. Moreover, there is no additional main conduction path switch. Thus, the normal operation of the resonant pole inverter is precisely the same as that of the conventional hard-switching inverter [12].

The auxiliary resonant commutated pole (ARCP) inverter [13] and the ordinary resonant snubber inverter [14] provide a ZVS condition without increasing the device voltage and current stress. These inverters are able to achieve real PWM control. However, they require a stiff DC link capacitor bank that is center-taped to accomplish commutation. The center voltage of the DC link is susceptible to drift, which may affect the operation of the resonant circuit. The resonant transition inverter [15,16] uses only one auxiliary switch, whose switching frequency is much higher than that applied to the main switches. Thus, it will limit the switching frequency of the inverter. Furthermore, the three resonant branches of the inverter work together and will be affected by each other. A Y-configured resonant snubber inverter [17] has a floating neutral voltage that may cause overvoltage failure of the auxiliary switches. A delta (Δ)-configured resonant snubber inverter [18] avoids the floating neutral voltage and is suitable for multiphase operation without circulating currents between the off-state branch and its corresponding output load. However, the inverter requires three inductors and six auxiliary switches.

FIGURE 7.12
Resonant pole inverter.

Moreover, resonant pole inverters have been applied in induction motor drive applications. They are usually required to change two phase switch states at the same time to obtain a resonant path. It is not suitable for a BDCM drive system as only one switch is needed to change the switching state in a PWM cycle. The switching frequency of three upper switches (S₁, S₃, S₅) is different from that of the three lower switches (S₂, S₄, S₆) in an inverter for a BDCM drive system. All the switches have the same switching frequency in a conventional inverter for induction motor applications. Therefore, it is necessary to develop a novel topology for the soft-switching inverter and a special control circuit for BDCM drive systems. This chapter presents a specially designed resonant pole inverter that is suitable for BDCM drive systems and is easy to apply in industry. In addition, this inverter possesses the following advantages: low switching power losses, low inductor power losses, low switching noise, and simple control scheme.

7.2.1    Topology of Resonant Pole Inverter

A typical controller for a BDCM drive system [19] is shown in Figure 7.13.

FIGURE 7.13
Typical controller for the BDCM drive system.

FIGURE 7.14
Structure of the resonant pole inverter for the BDCM drive system.

The rotor position can be sensed by a Hall effect sensor or a slotted optical disk, providing three square-waves with phase shift in 120°. These signals are decoded by a combinatorial logic to provide the firing signals for 120° conduction on each of the three phases. The basic forward control loop is voltage control implemented by PWM (voltage reference signal compared with triangular wave or generated by microprocessor). The PWM is applied only to the lower switches. This not only reduces the current ripple but also avoids the need for wide bandwidth in the level-shifting circuit that feeds the upper switches. The three upper switches work under commutation frequency (typically, several hundred Hz) and the three lower switches work under PWM frequency (typically tens of kHz). So it is not important that the three upper switches work under soft-switching condition. The switching power losses can be reduced significantly and the auxiliary circuit would be simpler if only the three lower switches work under soft-switching condition. Thus, a specially designed resonant pole inverter for the BDCM drive system was introduced for this purpose. The structure of the proposed inverter is shown in Figure 7.14.

The system contains a diode bridge rectifier, a resonant circuit, a conventional three-phase inverter, and control circuitry. The resonant circuit consists of three auxiliary switches (S_a, S_b, S_c), one transformer with turn ratio 1: n, and two diodes D_fp and D_r. Diode D_fp is connected in parallel to the primary winding of the transformer, and diode D_r is connected in series with the secondary winding across the DC link. There is one snubber capacitor connected in parallel to each lower switch of the phase leg. The snubber capacitor resonates with the primary winding of the transformer. The emitters of the three auxiliary switches are connected together. Thus, the gate drive of these auxiliary switches can use one common output DC power supply.

In a whole PWM cycle, the three lower switches (S₂, S₄, S₆) can be turned off in the ZVS condition as the snubber capacitors (C_ra, C_rb, C_rc) can slow down the voltage rise rate. The turn-off power losses can be reduced, and the turn-off voltage spike is eliminated. Before turning on the lower switch, the corresponding auxiliary switch (S_a, S_b, S_c) must be turned on. The snubber capacitor is then discharged, and the lower switches reach the ZVS condition. During phase current commutation, the switching state is changed from one lower switch to another. For example, turn off S₆ and turn on S₂, S₆ can be turned off directly in the ZVS condition, turning on auxiliary switch S_c to discharge the snubber capacitor C_r then switch S₂ can achieve the ZVS condition. During phase current commutation, if the switching state is changed from one upper switch to another upper switch, the operation is the same as that of the hard-switching inverter, as the switching power losses of the upper switches are much smaller than those of the lower switches.

7.2.2    Operation Principle

For the sake of convenience, to describe the operation principle, we investigate the period of time when switch S₁ is always turned on, when switch S₆ works under PWM frequency, and when other main inverter switches are tuned off. Since the resonant transition is very short, it can be assumed that the load current is constant. The equivalent circuit is shown in Figure 7.15. V_S is the DC link voltage, i_Lr is the transformer primary winding current, u_S6 is the voltage drop across the switch S₆ (i.e., snubber capacitor C_rb voltage), and I_O is the load current. The waveforms of the switches’ (S₆, S_b) gate signal, PWM signal, main switch S₆ voltage drop (u_S6), and the transformer primary winding current (i_Lr) are shown in Figure 7.16, and the details will now be explained. Accordingly, at the instant t₀ – t₆, the operation of one switching cycle can be divided into seven modes.

FIGURE 7.15
Equivalent resonant circuit.

FIGURE 7.16
Key waveforms of the equivalent circuit.

Mode 0 [shown in Figure 7.17a] 0 < t < t₀: After the lower switch S₆ is turned off, load current flows through the upper freewheeling diode D₃, the voltage drop u_S6 (i.e., snubber capacitor C_rb voltage) across the switch S₆ is the same as that of the DC link voltage. The auxiliary resonant circuit does not operate.

Mode 1 [shown in Figure 7.17b] t₀ < t < t₁: If the switch S₆ is turned on directly, the capacitor discharge surge current will also flow through switch S₆; thus, switch S₆ may face the risk of a second breakdown. The energy stored in the snubber capacitor must be discharged ahead of time. Thus, auxiliary switch S_b is turned on (ZCS turns on as the current i_Lr cannot change suddenly due to the transformer inductance). As the transformer primary winding current i_Lr begins to increase, the current flowing through the freewheeling diode decays. The secondary winding current i_Lrs also begins to conduct through diode D_r to the DC link. Both terminal voltages of the primary and secondary windings are equal to the DC link voltage V_S. By neglecting the resistances of the windings and using the transformer equivalent circuit (referred to the primary side) [20], we get

$V_S=L{}_{l1}\frac{d{i}_{Lr}(t)}{dt}+a^2{L}_{l2}\frac{d[i_{Lrs}(t)/a]}{dt}+a{V}_S$

(7.13)

where L_l1 and L_l2 are the primary and secondary winding leakage inductance, respectively, and is the transformer turn ratio 1:n. The transformer has a high magnetizing inductance. We can assume that i_Lrs = i_Lr/n, and rewrite Equation (7.13) as

FIGURE 7.17
Operation modes of the resonant pole inverter: (a) Mode 0, (b) Mode 1, (c) Mode 2, (d) Mode 3, (e) Mode 4, and (f) Mode 6.

$\frac{d{i}_{Lr}}{dt}=\frac{(n-1)V_S}{n(L_{l1}+\frac{1}{n^2}{L}_{l2})}=\frac{(n-1)V_S}{n{L}_r}$

(7.14)

where L_r is the equivalent inductance of the transformer L_l1 + L_l2/n². The transformer primary winding current i_Lr increases linearly, and the mode terminates when i_Lr = I_O. The interval of this mode can be determined by

$\text{Δ}{t}_1=t_1-t_0=\frac{n{L}_r{I}_O}{(n-1)V_S}$

(7.15)

Mode 2 [shown in Figure 7.17c] t₁ < t < t₂: At t = t₁, all load current flows through the transformer primary winding, and the freewheeling diode D₃ is turned off in the ZCS condition. The freewheeling diode reverse recovery problems are greatly reduced. The snubber capacitor C_rb resonates with the transformer, and the voltage drop u_S6 across switch S₆ decays. By redefining the initial time, the transformer currents i_Lr, i_Lrs and capacitor voltage u_S6 obey the equation

$\{\begin{array}{c}{u}_{S6}(t)=L_{l1}\frac{d{i}_{Lr}(t)}{dt}+a^2{L}_{l2}\frac{d[i_{Lrs}(t)/a]}{dt}+a{V}_S\\ -C_r\frac{d{u}_{S6}(t)}{dt}=i_{Lr}(t)-I_O\end{array}$

(7.16)

where C_r is the capacitance of snubber capacitor C_rb. The transformer current i_Lrs = i_Lr/n, as in mode 1, with initial conditions u_S6(0) = V_S, i_Lr(0) = I_O; then the solution of (7.16) is

$\{\begin{array}{c}{u}_{S6}(t)=\frac{(n-1)V_S}{n}\cos ({\text{ω}}_{r}t)+\frac{V_S}{n}\\ i_{Lrs}(t)=I_O+\frac{(n-1)V_S}{n}\sqrt{\frac{C_r}{L_r}}\sin ({\text{ω}}_r,t)\end{array}$

(7.17)

where ${\omega }_r=\sqrt{1/L_r{C}_r}$.

Let u_Cr(t) = 0, which shows the duration of the resonance

$\text{Δ}{t}_2=t_2-t_1=\frac{1}{{\text{ω}}_r}\arccos \left(-\frac{1}{n-1}\right)$

(7.18)

The interval is independent of the load current. At t = t₂, the corresponding transformer primary current is

$i_{Lr}(t_2)=I_O+V_S\sqrt{\frac{(n-2)C_r}{n{L}_r}}$

(7.19)

The peak value of the transformer primary current can also be determined:

$i_{Lr-m}=I_O+\frac{n-1}{n}{V}_S\sqrt{\frac{C_r}{L_r}}$

(7.20)

Mode 3 [shown in Figure 7.17d] t₂ < t < t₃: When the capacitor voltage u_S6 reaches zero at t = t₂, the freewheeling diode D_pf begins to conduct. The current flowing through auxiliary switch S_b is the load current I_O. The sum of the currents flowing through switch S_b and diode D_pf is the transformer primary winding current i_Lr The transformer primary voltage is zero, and the secondary voltage is V_S. By redefining the initial time, we obtain

$0=L_{l1}\frac{d{i}_{Lr}(t)}{dt}+a^2{L}_{l2}\frac{d[i_{Lrs}(t)/a]}{dt}+a{V}_S$

(7.21)

Since the transformer current i_Lrs = i_Lr/n as in Mode 1, we deduce Equation

$\frac{d{i}_{Lr}}{dt}=-\frac{V_S}{n{L}_r}$

(7.22)

The transformer primary current decays linearly, and the mode terminates while i_Lr = I₀.With the initial condition given by (7.19), the interval of this mode can be determined by

$\text{Δ}{t}_3=t_3-t_2=\sqrt{n(n-2)L_r{C}_r}$

(7.23)

The interval is also independent of the load current. During this mode, switch is turned on in ZVS condition.

Mode 4 [shown in Figure 7.17e] t₃ < t < t₄: The transformer primary winding current i_Lr decays linearly from load current I_O to zero. Partial load current flows through the main switch S₆. The sum of the currents flowing through switches S₆ and S_b is equal to the load current I_O. The sum of the currents flowing through switch S_b and diode Df_p is the transformer primary winding current i_Lr. By redefining the initial time, the transformer winding current obeys Equation (7.22) with the initial condition i_Lr(0) = I_O. The interval of this mode is

$\text{Δ}{t}_4=t_4-t_3=\frac{n{L}_r{L}_O}{V_S}$

(7.24)

The auxiliary switch S_b can be turned off in ZVS condition. In this case, after switch S_b is turned off, the transformer primary winding current flows through the freewheeling diode Df_p. The auxiliary switch S_b can be also be turned off in ZVS and zero current switching (ZCS) condition after i_Lr decays to zero.

Mode 5 [t₄ < t < t₅]: The transformer primary winding current decays to zero and the resonant circuit idles. This is likely the same operational state as the conventional hard-switching inverter. The load current flows from the DC link through the two switches S₁ and S₆, and the motor.

Mode 6 [shown in Figure 7.17f] t₅ < t < t₆: The main inverter switch S₆ is turned directly off, and the resonant circuit does not work. The snubber capacitor C_rb can slow down the rise rate of u_S6, while the main switch S₆ operates in ZVS condition. The duration of the mode is

$\text{Δ}{t}_7=t_7-t_6=\frac{C_r{V}_S}{I_O}$

(7.25)

The next period starts from Mode 0 again, but the load current flows through freewheeling diode D₃. During phase current commutation, the switching state is changed from one lower switch to another (e.g., turn off S₆ and turn on S₂). S₆ can be turned off directly in ZVS condition (similar to Mode 6). Turning on auxiliary switch S_c to discharge the snubber capacitor C_rc, switch S₂ can then get ZVS condition (similar to Modes 1–4).

7.2.3    Design Considerations

It is assumed that the inductance of BDCM is much higher than the transformer leakage inductance. From the previous analysis, the design considerations can be summarized as follows:

1.  Determine the value of snubber capacitor C_r, and the parameter of transformer.

2.  Select the main and auxiliary switches.

3.  Design the control circuitry for the main and auxiliary switches.

The turn ratio (1:n) of the transformer can be determined ahead. Equation (7.18) must satisfy

$n>2$

(7.26)

On the other hand, from Equation (7.24) the transformer primary winding current i_Lr will take a long time to decay to zero if n is too large. So n must be a relatively small number. The equivalent inductance of the transformer L_r = L_{l 1} + L_l2/n² is inversely proportional to the rise rate of the switch current when the auxiliary switches are turned on. This means that the equivalent inductance L_r should be sufficient to limit the rising rate of the switch current to work in ZCS condition. The selection of L_r can be referred to the rule depicted in Reference [21]:

$L_r\approx 4t_{on}{V}_S/I_{O\max }$

(7.27)

where t_on is the turn-on time of an IGBT and I_Omax is the maximum load current. The snubber capacitance C_r is inversely proportional to the rise rate of the switch voltage drop when turning off the lower main inverter switches. It means that the capacitance should be as high as possible to limit the rising rate of the voltage to work in ZVS condition. The selection of the snubber capacitor can be determined as follows:

$C_r\approx 4t_{on}{I}_{O\max }/V_S$

(7.28)

where t_off is the turn-off time of an IGBT. However, as the capacitance increases, more energy is stored on it. This energy should be discharged when the lower main inverter switches are turned on. With high capacitance, the peak value of the transformer current will also be high. The peak value of i_Lr should be restricted to twice that of the maximum load current. From Equation (7.20), we obtain

$\sqrt{\frac{C_r}{L_r}}\le \frac{n{I}_{O\max }}{(n-1)V_S}$

(7.29)

Three lower switches of the inverter (i.e., S₄, S₆, S₂) are turned on during Mode 3 (i.e., lag rising edge of PWM at the time range Δt₁ + Δ t₂ ~ Δt₁ + Δ t₂ + Δ t₃). In order to turn on these switches at a fixed time (say ΔT1), lagging rising edge of PWM under various load current can be used for convenient control. The following condition should be satisfied:

$\text{Δ}{t}_1+\text{Δ}{t}_2+\text{Δ}{t}_3\left|I_0=0>(\text{Δ}{t}_1+\text{Δ}{t}_2)\right|I_0=I_{0\max }+t_{off}$

(7.30)

Substitute Equations (7.15), (7.18), and (7.23) into Equation (7.30):

$\sqrt{n(n-2)L_r{C}_r}>\frac{n{L}_r{I}_{O\max }}{(n-1)V_S}$

(7.31)

The whole switching transition time is expressed as

$T_w=\text{Δ}{t}_1+\text{Δ}{t}_2+\text{Δ}{t}_3+\text{Δ}{t}_4=\frac{n{L}_r{I}_0}{(n-1)V_S}+\sqrt{L_r{C}_r}\times [\arccos \left(-\frac{1}{n-1}\right)+\sqrt{n(n-2)}$

(7.32)

For high switching frequencies, T_w should be as short as possible. Select the equivalent inductance L_r and snubber capacitance C_r to satisfy Equations (7.26),(7.27),(7.28),(7.29),(7.30),(7.31), and L_r and C_r should be as small as possible.

As the transformer operates at high frequency (20 kHz), the magnetic core material can be ferrite. The design of the transformer needs the parameters of form factor, frequency, the input/output voltage, input/output maximum current, and ambient temperature. From Figure 7.16, the transformer current can be simplified as triangle waveforms, and the form factor can be then determined as 2/√3. The ambient temperature is dependent on the application field. Other parameters can be obtained from the previous section. The transformer only carries current during the transition of turning on a switch in one cycle, so the winding can be a smaller diameter one.

The main switches S_1–6 work under ZVS condition; therefore, the voltage stress is equal to the DC link voltage V_S. The device current rate can be load current. Auxiliary switches S_a–c work under the ZCS or ZVS condition, while the voltage stress is also equal to the DC link voltage V_S. The peak current flowing through them is limited to double the maximum load current. As the auxiliary switches S_a-c carry the peak current only during switch transitions, they can be rated with a lower continuous current rating. The additional cost will not be too much.

The gate signal generator circuit is shown in Figure 7.18. The rotor position signal decode module produces the typical gate signal of the main switches. The inputs of the module are rotor position signals, rotating the direction of the motor, which “enables” the signal and PWM pulse train. The rotor position signals are three square waves with a phase shift in 120°. The “enable” signal is used to disable all outputs in case of emergency (e.g., overcurrent, overvoltage, and overheat). The PWM signal is the output of comparator, comparing the reference voltage signal with the triangular wave. The reference voltage signal is the output of the speed controller. The speed controller is a processor (single-chip computer or digital signal processor), and the PWM signal can be produced by software. The outputs (G₁–G₆) of the module are the gate signals applying to the main inverter switches. The outputs G_1,3,5 are the required gate signals for the three upper main inverter switches.

FIGURE 7.18
Gate signal generator circuit.

FIGURE 7.19
Gate signals G_S4,6,2 and G_Sa,b,c from G_4,6,2.

The gate signals of the three lower main inverter switches and auxiliary switches can be deduced from the outputs G_4,6,2 as shown in Figure 7.19. The trailing edge of the gate signals for three lower main inverter switches G_S4,6,2 is the same as that of G_4,6,2, and the leading edge of G_S4,6,2 lags G_4,6,2 for a short time ΔT₁. The gate signals for auxiliary switches G_S4,6,2 have a fixed pulse width (ΔT₂), the leading edge being the same as that of G_4,6,2. The gate signals G_Sa,b,c are the outputs of monostable flip-flops M_4,6,2 with the inputs G_4,6,2. The three monostable flip-flops M_4,6,2 have the same pulse width ΔT₂. The gate signals G_S4,6,2 are combined by the negative outputs of monostable flip-flops M_1,3,5 and G_4,6,2. The combining logical controller can be implemented by a D flip-flop with “preset” and “clear” terminals. The three monostable flip-flops M_4,6,2 have the same pulse width ΔT₁. Determination of the pulse widths of ΔT₁ and ΔT₂ is from theoretical analysis in the preceding subsection. In order to get the ZVS condition of the main inverter switches under various load currents, the lag time should satisfy

$(\text{Δ}{t}_1+\text{Δ}{t}_2)\left|I_O=I_{O\max }<\text{Δ}{T}_1<(\text{Δ}{t}_1+\text{Δ}{t}_2+\text{Δ}{t}_3)\right|I_O=0-t_{off}$

(7.33)

In order to get a soft-switching condition of the auxiliary switches, pulse width need only satisfy

$\text{Δ}{T}_2>(\text{Δ}{t}_1+\text{Δ}{t}_2+\text{Δ}{t}_3)|I_O=I_{O\max }$

(7.34)

7.2.4    Simulation and Experimental Results

The proposed topology is verified by the simulation software PSim. The DC link voltage is 300 V, and the maximum load current is 25 A. The parameters of the resonant circuit were determined from Equations (7.26),(7.27),(7.28),(7.29),(7.30),(7.31),(7.32). The transformer turns ratio is 1:4, and the leakage inductances of the primary secondary windings are 6 and 24 μH, respectively. Therefore, the equivalent transformer inductance L_r is 7.5 μH. The resonant capacitance C_r is 0.047 μF. Then, Δt₁ + Δt₂ and Δt₁ + ΔT₂ + ΔT₃ can be determined under various load currents I_O as shown in Figure 7.20, considering that the turn-off times of a switch with lagging time ΔT₁ and pulse width ΔT₂ are set to 2.1 μs and 5 μs, respectively. The frequency of the PWM is 20 kHz. Waveforms of transformer primary winding current i_Lr, switch S₆ voltage drop u_S6, PWM, main switch S₆, and auxiliary switch S_b, and the gate signal under low and high load currents are shown in Figure 7.21. The figure shows that the inverter worked well under various load currents. In order to verify the theoretical analysis and simulation results, the inverter was tested by experiment. The test conditions are

FIGURE 7.20
Boundary of ΔT₁ and ΔT₂ under various load currents I_O.

FIGURE 7.21
Simulation waveforms of i_Lr, u_S6, PWM, S₆, and S_b gate signal under various load currents: (a) under low load current (I_O = 5 A) and (b) under high load current (I_O = 25 A).

1.  DC link voltage: 300 V

2.  Power of BDCM: 3.3 Hp

3.  Rated phase current: 7.8 A

4.  Switching frequency: 20 kHz

Select a 50 A, 1200 V BSM 35 GB 120 DN2 dual IGBT module as main inverter switches, and a 30 A 600 V IMBH30D-060 IGBT as auxiliary switches. With datasheets of these switches and Equations (7.26),(7.27),(7.28),(7.29),(7.30),(7.31),(7.32), the value of inductance and capacitance can be determined. Three polyester capacitors of 47 nF/630 V were adopted as snubber capacitors for the three lower switches of the inverter. A highly magnetizing inductance transformer with turn ratio 1:4 was employed in the experiment. Fifty-two turn wires of size AWG 15 are selected as the primary winding, and 208 turn wires with size AWG 20 are selected as the secondary winding. The equivalent inductance is about 7 μH. The switching frequency is 20 kHz. The rotor position signal decode module is implemented by a 20 lead gate array logic (GAL) IC GAL16V8. The monostable flip-flop is set up by IC 74LS123, variable resistor, and capacitor. With Equations (7.33) and (7.34), lag time and pulse width are determined to be 2.5 and 5 μs, respectively.

The system is tested in light load and full load currents. The voltage waveforms across the main inverter switch u_S6 and its gate signal with low and high load currents are shown in Figures 7.22a and 7.22b, respectively. All the voltage signals are measured by a differential probe with a gain of 20, for voltage waveform, 5.00 V/div 100 V/div. The waveforms of u_S6 and the current i_S6 are shown in Figure 7.22c. We can see that both dv/dt and di/dt are reduced significantly. The waveforms of u_S6 and transformer primary winding current i_Lr are shown in Figure 7.22d. The phase current is shown in Figure 7.22e. It can be seen that the resonant pole inverter works well under various load currents, and there is little overlap between the voltage and current waveforms during soft-switching condition; therefore, the switching. The efficiency of hard switching and soft switching under rated speeds and various load torques (p.u.) are shown in Figure 7.23. Efficiency improves with the softswitching inverter. Therefore, the design of the system is successful.

FIGURE 7.22
Experiment waveforms: (a) Switch S₆ voltage u_S6 (top) and its gate signal (bottom) under low load current (100 V/div), (b) Switch S₆ voltage u_S6 (top) and its gate signal (bottom) under high load current (100 V/div), (c) Switch S₆ voltage u_S6 (top) and its current i_S6 (bottom) (100 V/div, 5 A/div), (d) Switch S₆ voltage u_S6 (top) and transformer current i_S6 (bottom) (100 V/div, 25 A/div), (e) waveforms of phase current (10 A/div).

FIGURE 7.23
Efficiency of hard switching and soft switching under various load torques (p.u.).

7.3    Transformer-Based Resonant DC Link Inverter

In order to generate voltage notches of the DC link at controllable instants and reduce the power losses of the inductor, several quasi-parallel resonant schemes were proposed [5,6,22]. As a dwell time is generally required after every notch, severe interference occurs, mainly in multiphase inverters, appreciably worsening the modulation quality. A novel DC rail parallel resonant zero voltage transition (ZVT) voltage source inverter [23] was introduced that overcomes many drawbacks mentioned earlier. However, it requires a stiff DC link capacitor bank that is center-taped to accomplish commutation. The center voltage of the DC link is susceptible to drift, which may affect the operation of the resonant circuit. In addition, it requires two ZVT per PWM cycle, which would lower the output voltage and limit the switch frequency of the inverter.

FIGURE 7.24
Structure of the resonant DC link inverter for the BDCM drive system.

On the other hand, the majority of soft-switching inverters proposed in recent years have been aimed at induction motor drive applications. So it was necessary to research the novel topology of soft-switching inverter and the special control circuit for BDCM drive systems. This chapter proposes a resonant DC link inverter based on a transformer for the BDCM drive system to solve the aforementioned problems. The inverter possesses the advantages of low switching power loss, low inductor power loss, low DC link voltage ripple, small device voltage stress, and a simple control scheme. The structure of the soft-switching inverter is shown in Figure 7.24 [24]. The system contains a diode bridge rectifier, a resonant circuit, a conventional three-phase inverter, and a control circuit. The resonant circuit consists of three auxiliary switches (S_L, S_a, S_b) and corresponding built-in freewheeling diode (D_L, D_a, D_b), one transformer with turn ratio 1:n, and one resonant capacitor. All auxiliary switches work under ZVS or zero current switching (ZCS) condition. The system generates voltage notches of the DC link to guarantee that the main switches (S₁–S₆) of the inverter operate in ZVS condition.

7.3.1    Resonant Circuit

The resonant circuit consists of three auxiliary switches, one transformer, and one resonant capacitor. The auxiliary switches are controlled at a certain instant to obtain resonance between transformer and capacitor. Thus, the DC link voltage reaches zero temporarily (voltage notch), and the main switches of the inverter reach ZVS condition for commutation. Since the resonant process is very short, the load current can be assumed constant. The equivalent circuit of the inverter is shown in Figure 7.25. When V_S is the DC power supply voltage, I_O is the load current. The corresponding waveforms of the auxiliary switches gate signal, PWM signal, resonant capacitor voltage u_Cr (i.e., DC link voltage), the transformer primary winding current i_Lr, and current i_SL of switch (S_L) are illustrated in Figure 7.26. The DC link voltage is reduced to zero and then rises to the supply voltage again; this is called one zero voltage transition (ZVT) process or one DC link voltage notch. The operation of the ZVT process in one PWM cycle can be divided into eight modes.

FIGURE 7.25
Equivalent circuit of the inverter.

Mode 0 [shown in Figure 7.27a] 0 < t < t₀: Its operation is the same as the conventional inverter. Current flows from DC power supply through S_L to the load. The voltage u_Cr across resonant capacitor C_r is equal to the supply voltage V_S. The auxiliary switches S_a and S_b are turned off.

Mode 1 [shown in Figure 7.27b] t₀ < t < t₁: When it is the instant for phase current commutation or the PWM signal is flipped from high to low, the auxiliary switch S_a is turned on with ZCS (as the i_Lr cannot suddenly change due to the transformer inductance) and switch S_L is turned off with ZVS (as the voltage cannot be suddenly changed due to resonant capacitor C_r) at the same time. The transformer primary winding current i_Lr begins to increase, and the secondary winding current i_Lrs also begins to build up through diode D_b to the DC link. The terminal voltages of primary and secondary windings of the transformer are the DC link voltage u_Cr and supply voltage V_S, respectively. Capacitor C_r resonates with the transformer, and the DC link voltage u_Cr is decreased. Neglecting the resistances of windings and using the transformer equivalent circuit (referred to the primary side) [25], the transformer current i_Lr, i_Lrs, and DC link voltage u_Cr obey the equation

FIGURE 7.26
Key waveforms of the equivalent circuit.

$\{\begin{array}{c}{u}_{Cr}(t)=L_{l1}\frac{d{i}_{Lr}(t)}{dt}+a^2{L}_{l2}\frac{d[i_{Lrs}(t)/a]}{dt}+a{V}_S\\ i_{Lr}(t)+I_O+C_r\frac{d{u}_{Cr}(t)}{dt}=0\end{array}$

(7.35)

where L_l1 and L_l2 are the primary and secondary winding leakage inductance, respectively. The transformer turn ratio is 1:n. The transformer has a high magnetizing inductance. We can assume that i_Lrs = i_Lr/n, with initial condition u_Cr(0) = V_S, i_Lr(0) = 0; solving Equation (7.35), we get

FIGURE 7.27
Operation mode of the resonant DC link inverter: (a) Mode 0, (b) Mode 1, (c) Mode 2, (d) Mode 3, (e) Mode 4, (f) Mode 5, (g) Mode 6, and (h) Mode 7.

$\{\begin{array}{c}{u}_{Cr}(t)=\frac{(n-1)V_S}{n}\cos ({\text{ω}}_{r}t)-I_O\sqrt{\frac{L_r}{C_r}}\sin ({\text{ω}}_{r}t)+\frac{V_S}{n}\\ i_{Lr}(t)=I_O\cos ({\text{ω}}_{r}t)-I_O+\frac{(n-1)V_S}{n}\sqrt{\frac{L_r}{C_r}}\sin ({\text{ω}}_{r}t)\end{array}$

(7.36)

where L_r = L_l1 + L_l2/n² is the equivalent inductance of the transformer, and ω_r = √(1/L_rC_r) is the natural angular resonance frequency. Rewriting Equation (7.36), we get

$\{\begin{array}{c}{u}_{Cr}(t)=K\cos ({\text{ω}}_{r}t+\text{α})+\frac{V_S}{n}\\ i_{Lr}(t)=K\sqrt{\frac{C_r}{L_r}}\sin ({\text{ω}}_{r}t+\text{α})-I_O\end{array}$

(7.37)

where $K=\sqrt{({(n-1)}^2{V}_S^2/n^2+(I_0^2{L}_r/C_r)}$, $\text{α}=\arctan [n{I}_0\sqrt{L_r/C_r}/(n-1)V_S]$. n is slightly less than 2 (the selection of the number will be explained later), and i_Lr will decay to zero faster than u_Cr Letting i_Lr(t) = 0, the duration of the resonance can be determined:

$\text{Δ}{t}_1=t_1-t_0=\frac{\text{π}-\text{α}}{{\text{ω}}_r}$

(7.38)

When i_Lr is reduced to zero, the auxiliary switch S_a can be turned off with ZCS condition. At t = t₁, the corresponding dc link voltage u_Cr is

$u_{Cr}(t_1)=\frac{2-n}{n}{V}_{\text{S}}$

(7.39)

Mode 2 [shown in Figure 7.27c] t₁ < t < t₂: When the transformer current is reduced to zero, the resonant capacitor is discharged through load from initial condition as in Equation (7.39). The interval of this mode can be determined by

$\text{Δ}{t}_2=t_2-t_1=\frac{C_r{V}_S(2-n)}{n{I}_0}$

(7.40)

As has been mentioned, n is slightly less than 2, and the interval is normally very short.

Mode 3 [shown in Figure 7.27d] t₂ < t < t₃: The DC link voltage u_Cr is zero. The main switches of the inverter can now be either turned on or turned off under ZVS condition during this mode. Load current flows through the freewheeling diode D.

Mode 4 [shown in Figure 7.27e] t₃ < t < t₄: As the main switches have turned on or turned off, the auxiliary switch S_b is turned on with ZCS (as i_Lrs cannot suddenly change due to the transformer inductance) and the transformer secondary current i_Lrs starts to build up linearly. The transformer primary current i_Lr also begins to conduct through diode D_a to the load. The current in the freewheeling diode D begins to fall linearly. The load current is slowly diverted from the freewheeling diodes to the resonant circuit. The DC link voltage u_Cr is still zero before the transformer primary current is greater than load current. The terminal voltages of transformer primary and secondary windings are zero and DC power supply voltage V_S, respectively. Redefining the initial time, we obtain

$0=L_{l1}\frac{d{i}_{Lr}(t)}{dt}+a^2{L}_{l2}\frac{d[i_{Lrs}(t)/a]}{dt}+a{V}_{\text{S}}$

(7.41)

Since the transformer current i_Lrs = i_Lr/n as in mode 1, we rewrite Equation (7.41) as

$\frac{d{i}_{Lr}}{dt}=-\frac{V_S}{n{L}_r}$

(7.42)

The transformer primary current is increased reverse-linearly from zero, and the mode terminates when i_Lr = -I_O; the interval of this mode can be determined as

$\text{Δ}{t}_4=t_4-t_3=\frac{n{L}_r{I}_O}{V_S}$

(7.43)

At t₄, i_Lr equals the negative load current -I_O, and the current through the diode D becomes zero. Thus, the freewheeling diode turns off under ZCS condition, and the diode reverse recovery problems are reduced.

Mode 5 [shown in Figure 7.27f] t₄ < t < t₅: The absolute value of i_Lr is continuously increased from I_O, and u_Cr is increased from zero when the freewheeling diode D is turned off. Redefining the initial time, we can get the same equation as Equation (7.35). The initial condition is u_Cr(0) = 0, i_Lr(0) = -I_O neglecting the inductor resistance and solving the equation, we get

$\{\begin{array}{c}{u}_{Cr}(t)=\frac{V_S}{n}\cos ({\text{ω}}_{r}t)+\frac{V_S}{n}\\ i_{Lr}(t)=-I_O-\frac{V_S}{n}\sqrt{\frac{C_r}{L_r}}\sin ({\text{ω}}_{r}t)\end{array}$

(7.44)

when

$\text{Δ}{t}_5=t_5-t_4=\frac{1}{{\text{ω}}_r}\arccos (1-n)$

(7.45)

u_Cr = V_S, and the auxiliary switch S_L is turned on with ZVS (due to C_r). The interval is independent of load current. At t = t₅, the corresponding transformer primary current i_Lr is

$i_{Lr}(t_5)=-I_O-V_S\sqrt{\frac{(2-n)C_r}{n{L}_r}}$

(7.46)

The peak value of the transformer primary current can also be determined:

$i_{Lr-m}=\left|-I_O-\frac{V_S}{n}\sqrt{\frac{C_r}{L_r}}\right|=I_O+\frac{V_S}{n}\sqrt{\frac{C_r}{L_r}}$

(7.47)

Mode 6 [shown in Figure 7.27g] t₅ < t < t₆: Both the terminal voltages of primary and secondary windings are equal to the supply voltage V_S after the auxiliary switch S_L is turned on. Redefining the initial time, we obtain

$V_S=L_{l1}\frac{d{i}_{Lr}(t)}{dt}+a^2{L}_{l2}\frac{d[i_{Lrs}(t)/a]}{dt}+a{V}_S$

(7.48)

Since the transformer current i_Lrs = i_Lr/n as in mode 1, we rewrite Equation (7.48) as

$\frac{d{i}_{Lr}}{dt}=\frac{(n-1)V_S}{n{L}_r}$

(7.49)

The transformer primary current i_Lr decays linearly, and the mode terminates when i_Lr = -I_O again. With the initial condition (Equation 7.46), the interval of this mode can be determined as

$\text{Δ}{t}_6=t_6-t_5=\frac{\sqrt{n(2-n)L_r{C}_r}}{n-1}$

(7.50)

The interval is also independent of load current. As mentioned earlier, n is slightly less than 2, and the interval is also very short.

Mode 7 [shown in Figure 7.27h] t₆ < t < t₇: The transformer primary winding current i_Lr decays linearly from negative load current -I_O to zero. Partial load current flows through the switch S_L. The sum of the currents flowing through switch S_L and transformer is equal to the load current I_O. Redefining the initial time, the transformer winding current obeys Equation (7.49) with the initial condition i_Lr(0) = -I_O. The interval of this mode is

$\text{Δ}{t}_7=t_7-t_6=\frac{n{L}_r{I}_0}{(n-1)V_S}$

(7.51)

Then auxiliary switch S_b can be also turned off with ZCS condition after i_Lr decays to zero (at any time after t₇).

7.3.2    Design Considerations

It is assumed that the inductance of BDCM is much higher than the transformer leakage inductance. From the analysis presented previously, the design considerations can be summarized as follows:

1.  Determine the value of resonant capacitor C_r and the parameters of the transformer.

2.  Select the main switches and auxiliary switches.

3.  Design the gate signal for the auxiliary switches.

The turn ratio 1:n of the transformer can be determined ahead. From Equation (7.45), n must satisfy

$n<2$

(7.52)

On the other hand, from Equations (7.39) and (7.40), n should be as close to 2 as possible so that the duration of mode 2 would be not very long and would be small enough at the end of mode 1.

Normally, n can be selected in the range 1.7–1.9. The equivalent inductance of the transformer L_r = L_l1 + L_l2/n² is inversely proportional to the rising rate of switch current when auxiliary switches are turned on. It means that the equivalent inductance L_r should be large enough to limit the rising rate of the switch current to work in ZCS condition. The selection of L_r can be referred to the rule depicted in Reference [26].

$L_r\ge \frac{4t_{on}{V}_S}{I_{O\max }}$

(7.53)

where t_on is the turn-on time of switch S_a, and I_Omax is the maximum load current. The resonant capacitance C_r is inversely proportional to the rising rate of switch voltage drop when switch S_L is turned off. This means that the capacitance is as high as possible to limit the rising rate of the voltage to work in ZVS condition. The selection of the resonant capacitor can be determined as

$C_r\ge \frac{4t_{off}{I}_{O\max }}{V_S}$

(7.54)

where t_off is the turn-off time of switch S_L. However, as the capacitance increases, more energy is stored in it, and the peak value of transformer current will also be high. The peak value of i_Lr should be limited to twice the peak load current. From Equation (7.47), we obtain

$\sqrt{\frac{C_r}{L_r}}\le \frac{n{I}_{O\max }}{V_S}$

(7.55)

The DC link voltage rising transition time is expressed as

$T_w=\text{Δ}{t}_4+\text{Δ}{t}_5=\frac{n{L}_r{I}_{0\max }}{V_S}+\sqrt{L_r{C}_r}\arccos (1-n)$

(7.56)

For high switching frequency, T_w should be as short as possible. Select the equivalent inductance L_r and resonant capacitance C_r to satisfy the inequalities (7.52),(7.53),(7.54),(7.55); L_r and C_r should be as small as possible. L_r and C_r selection area is illustrated in Figure 7.28 to determine their values, and the valid area is shadowed, where B₁–B₃ is the boundary, which is defined according to inequalities (7.52),(7.54),(7.55):

FIGURE 7.28
L and C selection area: (a) Case 1: B intersects B first and (b) Case 2: B intersects A first.

$B_1:L_r=\frac{4t_{on}{V}_S}{I_{0\max }}$

(7.57)

$B_2:C_r=\frac{4t_{off}{I}_{0\max }}{V_S}$

(7.58)

$B_3:\sqrt{\frac{C_r}{L_r}}=\frac{n{I}_{0\max }}{V_S}$

(7.59)

If boundary B₃ intersects B₁ first as shown in Figure 7.28a, the value of L_r and C_r in the intersection (i.e., A₁) can be selected. Otherwise, the value of L_r and C_r in the intersection A₂ is selected as shown in Figure 7.28b.

Main switches S₁–S₆ work under ZVS condition, and the voltage stress is equal to the DC power supply voltage V_S. The device current rate can be the load current. The auxiliary switch S_L works under ZVS condition, and its voltage and current stresses are the same as for the main switches. Auxiliary switches S_a and S_b work under ZCS or ZVS condition, and the voltage stress is equal to the DC power supply voltage V_S. The peak current flowing through them is limited to double the maximum load current. As the auxiliary switches S_a and S_b carry the peak current only during switch transitions, they can be the devices with lower continuous current ratings.

The design of the gate signal for auxiliary switches can be referenced from Figure 7.26. The trailing edge of the gate signal for auxiliary switch S_L is the same as that of PWM, and the leading edge is determined by the output of the DC link voltage sensor. The gate signal for auxiliary switch S_a is a positive pulse with leading edge the same as the PWM trailing edge, and its width ΔT_a should be greater than Δt₁. From Equation (7.38), Δt₁ is maximum when the load current is zero. So Δt_a can be a fixed value determined by

$\text{Δ}{T}_a>\text{Δ}{t}_1|{}_{\max }=\frac{\text{π}}{{\text{ω}}_r}=\text{π}\sqrt{L_r{C}_r}$

(7.60)

The gate signal for auxiliary switch S_b is also a pulse with leading edge the same as that of PWM, and its width ΔT_b should be longer than t₇ – t₃ (i.e., Δt₄ + Δt₅ + Δt₆ + Δt₇). ΔT_b can be determined from Equations (7.43), (7.45), (7.50), and (7.51):

$\text{Δ}{T}_b>{\displaystyle \sum _{i=4}^7\text{Δ}{t}_i|{}_{\max }=}\frac{n^2{L}_r{I}_{O\max }}{(n-1)V_S}+\sqrt{L_r{C}_r}\times \left[\arccos (1-n)+\frac{\sqrt{n(2-n)}}{n-1}\right]$

(7.61)

7.3.3    Control Scheme

When the duty of PWM is 100%, that is, full duty cycle, the main switches of the inverter work under the commutation frequency. When it is the instant to commutate the phase current of the BDCM, we control the auxiliary switches S_a, S_b, and S_L, and resonance occurs between transformer inductor L_r and capacitor C_r. The DC link voltage reaches zero temporarily; thus, ZVS condition of the main switches is obtained. When the duty of PWM is less than 100%, the auxiliary switch S_L works as a chopper. The main switches of the inverter do not switch within a PWM cycle when the phase current need not commutate. It has the benefit of reducing phase current drop when the PWM is off. The phase current is commutated when the DC link voltage becomes zero. There is only one DC link voltage notch per PWM cycle. It is very important especially for very low or very high duty of PWM. Otherwise the interval between two voltage notches will be very short even when overlapped, which will limit the tuning range.

The commutation logical circuit of the system is shown in Figure 7.29. It is similar to the conventional BDCM commutation logical circuit except that six D flip-flops are added to the output. Thus, the gate signal of the main switches is controlled by the synchronous pulse CK, which will be mentioned later, and the commutation can be synchronized with the auxiliary switches’ control circuit (shown in Figure 7.30). The operation of the inverter can be divided into PWM operation and full duty cycle operation.

FIGURE 7.29
Commutation logical circuit for the main switches.

FIGURE 7.30
Control circuit for the auxiliary switches.

7.3.3.1    Full Duty Cycle Operation

When the duty of PWM is 100%, that is, full duty cycle, the whole ZVT process (mode 1–mode 7) occurs when the phase current commutation is under way. The monostable flip-flop M₃ will generate one narrow negative pulse. The width of the pulse ΔT₃ is determined by (Δt₁ + Δt₂ + T’_c), where T’_c is a constant, considering the turn-on/turn-off time of the main switches. If n is close to 2, Δt₂ would be very short or u_Cr would be small enough at the end of the mode1, and ΔT₃ can be determined by

$\text{Δ}{T}_3=\text{Δ}{t}_1|{}_{\max }+T_C=\text{π}\sqrt{L_r{C}_r}+T_C$

(7.62)

where T_c is a constant that is greater than T’_c. The data selector makes the output of monostable flip-flop M₃ active. The monostable flip-flop M₁ generates a positive pulse when the trailing edge of M₃ negative pulse arrives. The pulse is the gate signal for auxiliary switch S_a, and its width is AT_a, which is determined by inequality (7.60). The gate signal for switch S_L is flipped to low at the same time. Then mode 1 begins, and the DC link voltage is reduced to zero. Synchronous pulse CK is also generated by a monostable flip-flop M₄, and the pulse width Δt_d should be greater than maximum Δt₁ (i.e., π√L_rC_r). If the D flip-flops are rising edge active, then CK is connected to the negative output of M₄, otherwise it is connected to the positive output. Thus, the active edge of pulse CK is within mode 3 when the voltage of the DC link is zero, and the main switches of the inverter are in ZVS condition. The monostable flip-flop M₂ generates a positive pulse when the leading edge of negative pulse arrives. The pulse width of M₂ is ΔT_d,which is determined by inequality (7.61). Then modes 4–7 occur, and the DC link voltage is increased to that of the supply voltage again. The leading edge of the gate signal for switch S_L is determined by the DC link voltage sensor signal. In other words, in full-cycle operation, when the phase current commutation is under way, the resonant circuit generates a DC link voltage notch to let main switches of the inverter switch under ZVS condition.

7.3.3.2    PWM Operation

In this operation, the data selector makes the PWM signal active. The auxiliary switch S_L works as a chopper, but the main switches of the inverter do not turn on or turn off within a single PWM cycle when the phase current need not commutate. The load current is commutated when the DC link voltage becomes zero. (As the PWM cycle is very short, it does not affect the operation of the motor).

1.  When PWM signal is flipped down, mode 1 begins, the pulse signal for switch S_a is generated by M₁, and the gate signal for switch S_L drops to low. However, the voltage of the DC link does not increase until the PWM signal is flipped up. Pulse CK is also generated by M₄ to locate the active edge of CK in mode 3.

2.  When the PWM signal is flipped up, mode 4 begins, and the pulse signal for switch S_b is generated at that moment. Then, when the voltage of the DC link is increased to the supply voltage V_S, the gate signal for switch S_L is flipped to a high level.

Thus, only one ZVT occurs per PWM cycle: modes 1 and 2 for PWM turning off, and modes 4, 5, 6, and 7 for PWM turning on. And the switching frequency would not be greater than the PWM frequency.

7.3.4    Simulation and Experimental Results

The proposed system is verified by simulation software PSim. The DC power supply voltage V_S is 240 V, and the maximum load current is 12 A. The transformer turn ratio n is 1: 1.8, and the leakage inductances of the primary secondary windings are selected as 4 and 12.96 μH, respectively. So the equivalent transformer inductance L_r is about 8 μH. The resonant capacitance C_r is 0.1 μF. Switch S_a,b gate signal widths ΔT_a and ΔT_b are set to be 3 and 6 μs, respectively. The narrow negative pulse width ΔT₃ in a full-duty cycle is set to 4.5 μs, and the delay time for synchronous pulse CK is set to 3.5 μs. The frequency of the PWM is 20 kHz. Waveforms of dc link voltage u_Cr, transformer primary winding current i_Lr, switch S_L and diode D_L current i_SL/i_DL, PWM, auxiliary switch gate signal under low and high load current are shown in Figure 7.31. The figure shows that the inverter worked well under various load currents.

FIGURE 7.31
Waveforms of u_Cr, i_Lr, i_SL/i_DL, PWM, auxiliary switches’ gate signal under various load currents: (a) under low load current (I_O = 2 A) and (b) under high load current (I_O = 8 A).

In order to verify the theoretical analysis and simulation results, the proposed soft switching inverter was tested on an experimental prototype. The DC link voltage is 240 V, the rated phase current is 7.8 A, and the switching frequency is 20 kHz. Select a 50 A/1200 V BSM 35 GB 120 DN2 dual IGBT module as the main inverter switches S₁–S₆ and auxiliary switch S_L, another switch in the same module of S_L can be adopted as auxiliary switch S_a, and 30 A/600 V IMBH30D-060 IGBT as auxiliary switch S_b. With datasheets of these switches and Equations (7.52),(7.54),(7.55), the value of capacitance and the parameter of the transformer can be determined. A polyester capacitor of 0.1 μF, 1000 V was adopted as the DC link resonant capacitor C_r. A high magnetizing inductance transformer with turn ratio 1:1.8 was employed in the experiment. The equivalent inductance is about 8 μH under short-circuit test [25]. The switching frequency is 20 kHz. The monostable flip-flop is set up by IC 74LS123, variable resistor, and capacitor. The logical gate can be replaced by a programmable logical device to reduce the number of ICs. ΔT_a, ΔT_b, ΔT₃, and ΔT_d are set to 3, 6, 4.5, and 3.5 μs, respectively.

The system is tested under light and heavy loads. The waveform’s DC link voltage u_Cr and transformer primary winding current i_Lr under low and high load currents are shown in Figures 7.32a and 7.32b, respectively. The transformer-based resonant DC link inverter works well under various load currents. The waveforms of auxiliary switch S_L voltage u_SL and its current i_SL are shown in Figure 7.32c. There is little overlap between the switch S_L voltage and its current during the switching under soft-switching condition, so the switching power losses are low. The waveforms of the resonant DC link voltage u_Cr and synchronous signal CK are shown in Figure 7.32d, which the main switches can switch under ZVS condition during commutation. The phase current of BDCM is shown in Figure 7.32e. The design of the system is successful.

FIGURE 7.32
Experiment waveforms: (a) the DC link voltage u_Cr (top) and transformer current i_Lr (bottom) under low load current (100 V/div, 10 A/div), (b) the DC link voltage u_Cr (top) and transformer current i_Lr (bottom) under high load current (100 V/div, 10 A/div), (c) switch S_L voltage (top) and current (bottom) (100 V/div, 10 A/div), (d) the DC link voltage u_Cr (top) and synchronous signal CK (bottom) (100 V/div), and (e) phase current of BDCM (5 A/div).

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