3

Voltage Source Inverters

Voltage source inverters (VSIs) are widely used in industrial applications and renewable energy systems [1,2,3]. Their structure and control circuitry are simple. Therefore, most engineers like to use them. Many semiconductor companies produce VSI control chips to simplify control circuitry design. We introduce some typical VSI circuits in this chapter.

3.1    Single-Phase Voltage Source Inverter

Single-phase voltage source inverters can be implemented in half-bridge and full bridge circuits.

3.1.1    Single-Phase Half-Bridge VSI

A single-phase half-bridge voltage source inverter (VSI) is shown in Figure 3.1. The carrier-based pulse width modulation (PWM) technique is applied in this inverter. Two large capacitors are required to provide a neutral point N; therefore, each capacitor keeps half of the input DC voltage. Since the output voltage is referring to the neutral point N, the maximum output voltage is smaller than half of the DC-link voltage if it is operating in linear modulation. The modulation operations are shown in Figure 2.5. Two switches S+ and S– in one chopping leg are switched by the PWM signal. Two switches S+ and S– operate in an exclusive state with small deadtime to avoid a short-circuit.

In general, linear modulation operation is considered, so that m_a is usually smaller than unity, for example, m_a = 0.8. Generally, in order to obtain low THD, the m_f is usually a large number. For description convenience we choose m_f = 9. In order to understand each inverter well, we show some typical waveforms in Figure 3.2.

How to determine the pulse width is the key of the PWM. If the control signal v_C is a sine wave function as shown in Figure 3.2a, we call the modulation sinusoidal pulse width modulation (SPWM). Figure 3.2b offers the switching signal. When it is “ON” switch on the upper switch S+, and switch off the lower switch S–, vice versa, it is “OFF” switch off the upper switch S+, and switch on the lower switch S–. Assume that the amplitude of the triangle wave is unity and the amplitude of the sine-wave is 0.8. Referring to Figure 3.2a, the sine wave function is

FIGURE 3.1
Single-phase half-bridge VSI. (a) Carrier and modulating signals. (b) Switch S+ state. (c) Switch S- state. (d) AC output voltage. (e) AC output current.

FIGURE 3.2
Single-phase half-bridge VSI (m_a = 0.8, m_f = 9).

$f(t)=m_a\sin \text{ω}t=0.8\sin 100\text{π}t$

(3.1)

where ω = 2πf, f = 50 Hz. The triangle functions are lines:

$\begin{array}{cccccccc}{f}_{\text{Δ}1}(t)& =& -4f{m}_{f}t=-1800t& & & f_{\text{Δ}2}(t)& =& 4f{m}_{f}t-2=1800t-2\\ f_{\text{Δ}3}(t)& =& 4-4f{m}_{f}t=4-1800t& & & f_{\text{Δ}4}(t)& =& 4f{m}_{f}t-6=1800t-6\end{array}$

$\begin{array}{l}\cdot \cdot \cdot \cdot \cdot \cdot \\ f_{\text{Δ}(2n-1)}(t)=4(n-1)-4f{m}_{f}t{f}_{\text{Δ}2n}(t)=4f{m}_{f}t-(4n-2)\\ \cdot \cdot \cdot \cdot \cdot \cdot \end{array}$

(3.2)

$\begin{array}{l}{f}_{\text{Δ}17}(t)=32-1800t{f}_{\text{Δ}18}(t)=1800t-34\\ f_{\text{Δ}19}(t)=36-1800t\end{array}$

Example 3.1

A single-phase half-bridge DC/AC inverter is shown in Figure 3.1 to implement SPWM with m_a = 0.8 and m_f = 9. Determine the first width of the pulse shown in Figure 3.2a.

Solution:

The leading age of the first pulse is at t = 0. Referring to the trigonometric formulae, the first pulse width (time or degree) is determined by the equation

$0.8\sin 100\text{π}t=1800t-2$

(3.3)

FIGURE 3.3
Sinusoidal PWM.

fideal waveforms associated with theThis is a transcendental equation with the unknown parameter t. Using iterative method to solve the equation, let x = 0.8sin100πt and y = 1800t − 2. We can choose the initial t₀ = 1.38889 ms = 25°.

The first pulse width to switch on and off the switch S+ is 1.2861 ms (or 23.15°).

Other pulse widths can be determined from other equations using the iterative method. For a PWM operation with large m_f, readers can refer to Figure 3.3.

Figure 3.2 shows the ideal waveforms associated with the half-bridge VSI. We can find out the phase delay between the output current and voltage. For a large m_f we can see the cross points demonstrated in Figure 3.3 with smaller phase delay between the output current and voltage.

3.1.2    Single-Phase Full-Bridge VSI

A single-phase full-bridge voltage source inverter (VSI) is shown in Figure 3.4. The carrier-based pulse-width modulation (PWM) technique is applied in this inverter. Two large capacitors may be used to provide a neutral point N, but are not necessary. Since the output voltage is not referring to the neutral point N, the maximum output voltage is possibly greater than the half of the DC-link voltage. If it is operating in linear modulation the output voltage is smaller than the DC-link voltage. The modulation operation of multi-leg VSI is different from that of single-leg (single-phase half-bridge); VSI is shown in the previous subsection. It will be shown in Figure 3.8. Four switches, S₁+/S₁– and S₂+/S₂–, in two legs are applied and switched by the PWM signal.

FIGURE 3.4
Single-phase full-bridge VSI. (a) Carrier and modulating signals. (b) Switch S₁+ and S₁- state. (c) Switch S₂+ and S₂- state. (d) AC output voltage. (e) AC output current.

Figure 3.5 shows the ideal waveforms associated with the full-bridge VSI. There are two sine waves used in Figure 3.5a corresponding to the two legs operation. We can find out the phase delay between the output current and voltage.

The method to determine the pulse widths is the same as that introduced in the previous section. Referring to Figure 3.5a, we can find that there are two sine wave functions:

$f_{+}(t)=m_a\sin \text{ω}t=0.8\sin 100\text{π}t$

(3.4)

and

$f_{-}(t)=m_a\sin \text{ω}t=-0.8\sin 100\text{π}t$

(3.5)

The triangle functions are:

$\begin{array}{cccccccc}{f}_{\text{Δ}1}(t)& =& -4f{m}_{f}t=-1600t& & & f_{\text{Δ}2}(t)& =& 4f{m}_{f}t-2=1600t-2\\ f_{\text{Δ}3}(t)& =& 4-4f{m}_{f}t=4-1600t& & & f_{\text{Δ}4}(t)& =& 4f{m}_{f}t-6=1600t-6\end{array}$

$\begin{array}{l}\cdot \cdot \cdot \cdot \cdot \cdot \\ f_{\text{Δ}(2n-1)}(t)=4(n-1)-4f{m}_{f}t{f}_{\text{Δ}2n}(t)=4f{m}_{f}t-(4n-2)\\ \cdot \cdot \cdot \cdot \cdot \cdot \end{array}$

(3.6)

$\begin{array}{l}{f}_{\text{Δ}15}(t)=28-1600t{f}_{\text{Δ}16}(t)=1600t-30\\ f_{\text{Δ}17}(t)=32-1600t\end{array}$

FIGURE 3.5
The full-bridge VSI (m_a = 0.8, m_f = 8).

The first pulse width to switch on and switch off S₁+ and S₁– is determined by the equation below:

$0.8sin100\text{π}t=1600t-2$

(3.7)

The first pulse width to switch on and switch off the switches S₂₊ and S₂- is determined by the equation below:

-0.8sin100πt = 1600t-2

or

$0.8sin100\text{π}t=2-1600t$

(3.8)

Since the output voltage varies between legs, the rms voltages of the output voltage harmonics are calculated by the following formula

$(V_{\text{O}})h=\frac{2V_d}{\sqrt{2}}\frac{({\widehat{V}}_{AO})h}{V_d/2}$

(3.9)

where (V_O)_h is the hth harmonic rms voltage of the output voltage, V_d is the DC link voltage and ${({\widehat{V}}_{AO})}_h/(V_d/2)$ is tabulated as a function of m_a, which can be found in Table 2.1.

Example 3.2

A single-phase full-bridge DC/AC inverter is shown in Figure 3.4 to implement SPWM with V_d = 300 V, m_a = 1.0 and m_f = 31. The fundamental frequency is 50 Hz. Determine the rms value of the fundamental frequency and some of the harmonics in output voltage using Table 3.1.

Solution:

From Equation 2.3 we have the general rms values

${(V_O)}_h=\frac{2V_d}{\sqrt{2}}\frac{{({\widehat{V}}_{AO})}_h}{V_d/2}=\frac{600}{\sqrt{2}}\frac{{({\widehat{V}}_{AO})}_h}{V_d/2}=424.26\frac{{({\widehat{V}}_{AO})}_h}{V_d/2}V$

Checking the data from Table 2.1, we can get the rms values as follows:

TABLE 3.1
Iterative Method

t (ms/degree)	x	y	x|:y	Remarks
1.38889/25°	0.338	0.5	<	Decrease t
1.27778/23°	0.3126	0.3	>	Increase t
1.2889/23.2°	0.3152	0.32	<	Decrease t
1.2861/23.15°	0.3145	0.315	≈

(V_O)₁ = 424.26×1.0 = 424.26 V at 50 Hz

(V_O)₂₇ = 424.26 × 0.018 = 7.64 V at 1350 Hz

(V_O)₂₉ = 424.26 × 0.318 = 134.92 V at 1450 Hz

(V_O)₃₁ = 424.26× 0.601= 254.98 V at 1550 Hz

(V_O)₃₃ = 424.26 × 0.318 = 134.92 V at 1650 Hz

(V_O)₃₅ = 424.26 × 0.018 = 7.64 V at 1750 Hz

(V_O)₅₇ = 424.26× 0.033 = 14 V at 2850 Hz

(V_O)₅₉ = 424.26× 0.212 = 89.94 V at 2950 Hz

(V_O)₆₁ = 424.26× 0.181= 76.79 V at 3050 Hz

(V_O)₆₃ = 424.26× 0.181= 76.79 V at 3150 Hz

(V_O)₆₅ = 424.26× 0.212 = 89.94 V at 3250 Hz

(V_O)₆₇ = 424.26× 0.033 = 14 V at 3350 Hz, etc.

3.2    Three-Phase Full-Bridge VSI

A three-phase full-bridge VSI is shown in Figure 3.6. The carrier-based pulse width modulation (PWM) technique is applied in this single-phase full-bridge VSI. Two large capacitors may be used to provide a neutral point N, but are not necessary. Six switches S₁ – S₆ in three legs are applied and switched by the PWM signal.

FIGURE 3.6
Three-phase full-bridge VSI. (a) Carrier and modulating signals. (b) Switch S₁/S₄ state. (c) Switch S₃/S₄ state. (d) AC output voltage. (e) AC output current.

Figure 3.7 shows the ideal waveforms associated with the full-bridge VSI. We can find out the phase delay between the output current and voltage.

Since the three-phase waveform in Figure 3.7a is not referring to the neutral point N, the operation conditions are different from single-phase half-bridge VSI. The maximum output line-to-line voltage is possibly greater than the half of the DC-link voltage. If it is operating in linear modulation, the output voltage is smaller than the DC-link voltage. The modulation indication of a three-phase VSI is different from that of single-phase half-bridge VSI as noted in Section 3.1.1. It is shown in Figure 3.8.

FIGURE 3.7
Three-phase full-bridge VSI (m_a = 0.8, m_f = 9).

FIGURE 3.8
The function of modulation for a three-phase inverter.

3.3    Vector Analysis and Determination of m_a

Vector analysis and determination of m_a are important topics for a three-phase PWM VSI. We discuss this topic in this section and would like to draw more attention to DC/AC inverter designs.

3.3.1    Vector Analysis

A three-phase PWM VSI vector is shown in Figure 3.9. Referring to Figure 3.6, we have

${\upsilon }_{control}={\widehat{V}}_{control}\sin ({\text{ω}}_{\text{1}}t)$

(3.10)

FIGURE 3.9
Three-phase inverter vector analysis: (a) circuit diagram; (b) phasor diagram (fundamental frequency).

Since

$V_{AO}=\frac{{\upsilon }_{control}}{{\widehat{V}}_{tri}}\frac{V_d}{2}=\frac{{\widehat{V}}_{control}}{{\widehat{V}}_{tri}}\sin ({\text{ω}}_{\text{1}}t)\frac{V_d}{2}=m_a\frac{V_d}{2}\sin ({\text{ω}}_{\text{1}}t)$

(3.11)

3.3.2    m_a Calculation

If the load is resistive, the phasor diagram is shown in Figure 3.10.

$V_{An1}=m_a\frac{V_d}{2}\sin ({\text{ω}}_{\text{1}}t)$

(3.12)

$V_{An1-rms}=m_a\frac{V_d}{2\sqrt{2}}$

(3.13)

$V_{R-rms}=m_a\frac{V_d}{2\sqrt{2}}\cos \Phi$

(3.14)

FIGURE 3.10
Three-phase inverter vector analysis for resistive load R.

$\Phi V_{R-rms}={\tan }^{-1}\left(\frac{{\text{ω}}_{\text{1}}L}{R}\right)={\tan }^{-1}\left(\frac{100\text{π*20}m}{80}\right)\approx 4.49°$

(3.15)

$V_{AB-rms}=\sqrt{3}{V}_{R-rms}=m_a\frac{\sqrt{3}{V}_d}{2\sqrt{2}}\cos \Phi$

(3.16)

Hence,

$m_a=\sqrt{3}{V}_{R-rms}=\frac{V_{AB-rms}}{V_d}\frac{2\sqrt{2}}{\sqrt{3}\cos \Phi }\approx 0.936$

(3.17)

We can choose m_a = 0.939.

FIGURE 3.11
Three-phase inverter simulation circuit with a resistive load R = 80 Ω.

3.3.3    m_a Calculation with l-C Filter

If we set a L-C output filter (star connection) before the load, we have

$R//C=\frac{R\frac{1}{j\text{ω}C}}{R+\frac{1}{j\text{ω}C}}=\frac{R}{1+j\text{ω}CR}$

(3.18)

$V_R=\frac{R//C}{j\text{ω}L+R//C}{V}_{An}=\frac{\frac{R}{1+j\text{ω}CR}}{j\text{ω}L+\frac{R}{1+j\text{ω}CR}}{V}_{An}=\frac{R}{R(1-{\text{ω}}^{\text{2}}CL)+j\text{ω}L}{V}_{An}$

(3.19)

The variation is ωCωL = 100π × 3u × 100π × 20m ≈ 0.0056.

Therefore, we can choose m_a = 0.9304.

3.3.4    Some Waveforms

We chose the DC input voltage V_d = 700 V, the load R = 80 Ω, and an L filter L = 20 mH. The simulation circuit is shown in Figure 3.11, and the output voltage is a three-phase 50 Hz/400 V (rms liner-to-liner) as shown in Figure 3.12.

In order to obtain better output voltage, we can set an L-C filter before the load. The capacitance is 3 μF in a star connection. The simulation circuit is shown in Figure 3.13, and the output voltage is a three-phase 50 Hz/400 V (liner-to-liner rms) as shown in Figure 3.14.

FIGURE 3.12
The corresponding input and output waveforms of VSI in Figure 3.11.

FIGURE 3.13
Three-phase inverter simulation circuit with a resistive load R = 80 Ω.

We can also set an L-C filter before the load. The capacitance is 1 μF in delta connection. The simulation circuit is shown in Figure 3.15, and the output voltage is a three-phase 50 Hz/400 V (liner-to-liner rms) as shown in Figure 3.16.

3.4    Multistage PWM Inverter

Multistage PWM inverters can be constructed by two methods: multicell and multilevel. Unipolar modulation PWM inverters can be considered multistage inverters.

FIGURE 3.14
The corresponding input and output waveforms of VSI in Figure 3.13.

3.4.1    Unipolar PWM VSI

In Section 3.1 we introduced the single-phase source inverter operating in the bipolar modulation. Refer to the circuit in Figure 3.1; both upper switch S+ and lower switch S– work together. The carrier and modulating signals are shown in Figure 3.2a, and the switching signals for upper switch S+ and lower switch S– are shown in Figures 3.2b and c. The output voltage of the inverter is the pulse train with both polarities shown in Figure 3.2d.

There are some drawbacks using bipolar modulation: (1) if the inverter is VSI, a dead time has to be set to avoid a short circuit; (2) the zero output voltage corresponds to the equal-pulse width of positive and negative pulses; (3) power losses are high since two devices work, and hence the efficiency is lower; and (4) two devices should be controlled simultaneously.

The modulation method of the unipolar VSI is shown in Figure 3.17. There are two triangle signals in positive and negative levels. When the control signal is positive, only the top switch works and when the control signal is negative, only the lower switch works.

In most industrial applications, unipolar modulation is widely applied. The regulation and corresponding waveforms are shown in Figure 3.17 with m_a = 0.8 and m_f = 9. For unipolar regulation the m_a is measured by

$m_a=\frac{V_{in-m}}{2V_{tri-m}}$

(3.20)

FIGURE 3.15
Three-phase inverter simulation circuit with a resistive load R = 80 Ω.

This regulation method is likely a two-stage PWM inverter. If the output voltage is positive, only the upper device works and the lower device idles. Therefore, the output voltage only remains the positive polarity pulse train. Conversely, if the output voltage is negative, only the lower device works and the upper device idles. Therefore, the output voltage only remains the negative polarity pulse train. The advantages to implement unipolar regulation are

•  No need to set dead time.

•  The pulses are narrow, for example, zero output voltage requires zero pulse width.

•  Power losses are low and hence the efficiency is high.

•  Only one device should be controlled in half-cycle operation.

FIGURE 3.16
The corresponding input and output waveforms of VSI in Figure 3.15.

3.4.2    Multicell PWM VSI

Multistage PWM inverters can consist of many cells. Each cell can be a single-phase or three-phase input plus single-phase output VSI, which is shown in Figure 3.18. If the three-phase AC supply is a secondary winding of a main transformer, it is floating and isolated from other cells and a common ground point. Therefore, all cells can be linked in a series or parallel manner.

A three-stage PWM inverter is shown in Figure 3.19. Each phase consists of three cells with difference phase-angle shift by 20° of each other.

The carrier-based pulse width modulation (PWM) technique is applied in this three-phase multistage PWM inverter. Figure 3.20 shows the ideal waveforms associated with the full-bridge VSI. We can find out the output of the phase delayed between the output current and voltage.

3.4.3    Multilevel PWM Inverter

A three-level PWM inverter is shown in Figure 3.21. The carrier-based pulse width modulation (PWM) technique is applied in this multilevel PWM inverter. Figure 3.22 shows the ideal waveforms associated with the multilevel PWM inverter. We can determine the output of the phase delayed between the output current and voltage.

FIGURE 3.17
Three-phase unipolar regulation inverter (m_a = 0.8, m_f = 9).

FIGURE 3.18
Three-phase input single-phase output cell.

FIGURE 3.19
Multistage converter based on a multicell arrangement.

FIGURE 3.20
Multicell PWM inverter (3 stages, m_a = 0.8, m_f = 6).

FIGURE 3.21
Three-phase, three-level VSI. (a) Carrier and modulating signals. (b) Switch S_1a status. (c) Switch S_4b status. (d) Inverter phase a-N voltage. (e) AC output line voltage. (f) AC output phase voltage.

FIGURE 3.22
Three-level VSI (3 levels, m_a = 0.8, m_f = 15).

References

1.  Mohan, N., Undeland, T. M., and Robbins, W. P. 2003. Power Electronics: Converters, Applications and Design (3rd edition). New York: John Wiley & Sons.

2.  Holtz, J. 1992. Pulsewidth modulation—a survey. IEEE Trans. Ind. Electron., pp. 410–420.

3.  Luo, F. L. and Ye, H. 2010. Power Electronics: Advanced Conversion Technologies. Boca Raton, FL: Taylor & Francis.