16.2.1 Requirements on 5G Radio Frontends

The requirement of significantly increased radio bandwidth for mobile communication asks for exploiting additional spectral resources to the already used frequency bands, as covered in Section 3.4, and, consequently, impacts the components utilized for the air interface.

The operation in several radio bands defined in the 3^rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) standard [1] for carrier aggregation between 700 MHz and 3.6 GHz has been extended to the frequency range of 450 MHz to 6 GHz to include new available radio bands allowing for increased capacity in mobile systems. The concurrent operation in different radio bands increases the HW complexity when duplicating the individual transceiver chains to support each of the bands. Thus, solutions for multiple band transceivers help to decrease the HW complexity by reducing the number of components and have motivated the research on such topics.

An additional increase of operating bandwidth is achieved by exploiting higher frequency bands of centimetre and millimetre wavelength. There, several GHz of spectrum will become available for mobile communications. System architectures and air interfaces are currently being defined, and solutions for radio frontends are necessary.

Multi‐antenna systems will be used in all frequency ranges to enhance the radio performance, as addressed in detail in Section 11.5. At lower frequencies, an increased number of multiple‐input multiple‐output (MIMO) streams is targeted to increase spectral efficiency by exploiting spatial multiplexing. Similar approaches are also considered for mmWave, where multiple antennas are required to enable mobile radio links at these frequencies by overcoming the particular radio propagation conditions through beamforming and the related antenna gain. These approaches, however, lead to HW complexity that scales (linearly or even non‐linearly) with the number of antennas and MIMO streams. Solutions to decrease complexity are hence required to enable their implementation.

An efficient utilization of spectrum is mandatory due to its limited availability. Solutions for more efficient spectrum usage are necessary to increase the mobile data volume for a defined bandwidth. One considered option is to use a certain frequency band simultaneously for transmission and reception, referred to as full‐duplex.

A further requirement on implemented HW components is to improve their energy efficiency with the goal of simplifying their integration, due to lower cooling requirements, and decreasing the carbon footprint of wireless communication systems, as detailed in Section 15.3. This requirement implies the utilization of semiconductor technologies with lower power consumption and techniques for energy efficient component operation. It is worth highlighting here again that if the 1000‐fold increase in data rate foreseen in 5G is expected to dissipate the same energy as in 4G systems, this would require improving the energy efficiency per bit by the same factor of 1000, as also discussed in Section 2.3.

Concepts and solutions to meet the requirements for 5G radio frontends are presented in the following sections, which give insights on recent research, while more details are available in [2] and [3].

16.2.2 Multi‐Band Transceivers

The focus of this section is on bands below 6 GHz. Some aspects related to mmWave bands can be found in Section 16.2.3.2, especially related to multi‐antenna operation, which is key at these higher bands.

To decrease the HW complexity, the signals of multiple radio bands are ideally fed through a single transceiver chain. The multiplication of transceiver chains by the number of supported bands and the increase of the number of included components are avoided, reducing size, weight and cost. The approach is based on broadband or multi‐band capability of components used for data and frequency conversion, amplification and filtering.

Newly developed radio frequency (RF) data converters facilitate the generation of signals directly at radio frequencies. This includes the digital‐to‐analog and frequency conversion. Operating at sampling rates between 9 and 15 Gsamples/s, they show a broadband performance of up to 2 GHz signal bandwidth positioned arbitrarily at up to 6 GHz carrier frequency. The high‐speed serial data interface allows the separated transmission of signals for different radio bands enabling an efficient utilization of the interface. This advantage is supported by numerically controlled oscillators (NCO) together with up or down conversion functionalities included in broadband digital‐to‐analog converters (DAC) or analog‐to‐digital converters (ADC). In this way, data and frequency conversion are provided by a single component for multiple radio bands.

The implementation of the RF signal generation with newest samples of DACs operating at 12 Gsamples/s, (e.g., those available at [4],[5]), targets three‐band operation at carrier frequencies around 2.6, 2.8, and 3.5 GHz, as shown in Figure 16‐1. Six times 20 MHz signal carriers provide 120 MHz of aggregated operating bandwidth positioned as two adjacent carriers in the three different radio bands. The pre‐distorted signals generated in the digital signal processor (DSP) to compensate nonlinear distortions in the power amplifier (PA) show five times larger bandwidth than the wanted signal, and are adapted to the bandwidth of the third and fifth order intermodulation distortions caused by amplifiers. Thus, signals of 600 MHz aggregated bandwidth will pass through the component, utilizing mostly the capacity of the high‐speed serial data link, which connects the DSP with the RF‐DAC. It supports aggregated multiple complex input data streams up to a maximum complex data rate of 1.5 Gsamples/s. The three individual baseband signals accepted at the digital interface of the RF‐DAC are individually configured in gain, converted to RF signals and positioned in the targeted radio bands. These signals feed the amplification stages of the transmitter as shown in Figure 16‐1.

Broadband amplification is state‐of‐the‐art at low power levels. For higher power, an increase in power efficiency of amplifiers is required to reduce the effort for component cooling and the power consumption of the system. The required energy efficiency stays in contradiction with the wide bandwidth, and a trade‐off between output power, bandwidth and efficiency has to be considered. Accordingly, it is more appropriate to realize multi‐band PAs for radio bands positioned in a restricted frequency range to limit the overall amplifier bandwidth, and implement separate transceiver chains for widely spaced bands.

To cover the three envisaged radio bands, a dual‐band high‐power amplifier is designed with a relative bandwidth of 10.9% (2.6 GHz – 2.9 GHz) and 5.7% (3.4 – 3.6 GHz) in a Doherty topology [6] with a peak output power of more than 53 dBm. It allows the operation in all three envisaged bands simultaneously. Considering the concurrent operation of six modulated carriers, an average transmission power of up to 38 dBm per carrier is achieved, corresponding to the power level of medium range base stations (BSs). This combination of bandwidth, power level and carrier frequencies is achieved in a Gallium Nitride (GaN) technology by realizing two transistor power elements, which are mounted and matched in ceramic packages. These are integrated with circuitries on printed circuit boards, resulting in a Doherty amplifier module.

In multi‐band transceiver chains, signal filtering is required for each supported radio band. This demands solutions which allow for a closer integration of filters for different bands by enabling volume and weight reduction. Two concepts of resonators with multiple resonant frequencies are key building blocks for multi‐band filters. One considers a coaxial resonator with two conductive posts of different size inside, which determine the two resonance frequencies of a dual‐frequency resonator. This concept requires a minimum distance between the resonant frequencies as an inherent limitation, which prevents frequency ratios close to 1. The second approach provides full flexibility on the positioning of the resonant frequencies and allows optimizing the volume and resonator quality. The two cavities are intertwined while the top surface of the lower one determines the lower surface, as an enlarged post of the upper one. The theoretical and experimental evaluation of these dual‐band filter solutions, carried out for frequency bands of 2.6 and 3.5 GHz, prove their feasibility and demonstrate a volume reduction of up to 40% compared to the volume of two single‐band filters taken individually and separated.

These two concepts of dual‐band frequency resonators allow to be combined, resulting in a three‐band resonator solution, anticipating significant benefit on volume and weight reduction. The presented concepts for multi‐band filters show a variety of possibilities on the port implementations. Coaxial connectors at the input and output can be assigned to one, two or even three bands allowing a flexible adaptation to the transceiver architecture, especially to the number of amplifiers or antennas used to cover the envisaged radio bands.

The list of key building blocks for multi‐band transceivers has to be completed by the antennas. Many activities are focusing on broadband solutions, but significant research includes also multi‐band approaches at frequencies up to 6 GHz and covering radio bands which are further apart. Antenna topologies based on substrate integrated waveguide (SIW) technology [7][8], which allows for more than 1 GHz bandwidth, were proved for the range of 3.5 to 4.5 GHz and provide advantages on the integration environment. The shielded feeding line prevents coupling with adjacent components, and parasitic surface waves are minimized on the radiating element, which is realized as a slot in a conductor sheet. This eases a compact integration of the antenna in the system. Multi‐band solutions also ask for different resonant structures or mechanisms realized as a radiating patch on a printed circuit board for the lower frequencies, and a radiating slot within the patch serving the upper frequencies. This allows a free positioning of the two radiation frequencies, but shows a restricted relative bandwidth around 1.5% to 3%, as evaluated for radio bands at 2.6 and 3.5 GHz.

The building blocks for multi‐band transceivers promote carrier aggregation in radio frontends for increased capacity of mobile systems, as for instance addressed in Section 6.5. This is supported by the expected technology evolution on RF data converters with high sampling rates and decreased power consumption and by decreased fabrication costs of GaN based amplifiers, when moving from silicon carbide (SiC) to silicon (Si) as substrate material, which allows the fabrication on larger wafers.

16.2.3 Multi‐Antenna Transceivers

In this section, concepts and solutions for multi‐antenna transceivers are presented, which take into account in which frequency range they are going to operate. Section 16.2.3.1 considers the sub‐6 GHz region, whereas Section 16.2.3.2 deals with the mmWave domain.

16.2.3.1 Solutions for Base Stations at Lower Frequencies

Approaches for compact multi‐antenna system implementation address multiple signal generation and the chains to connect the antenna elements, including amplification and filtering, and resulting in a complete transmitter setup.

A compact solution for RF signal generation is achieved by integrating several transmit chains in a single field programmable gate array (FPGA) or application‐specific integrated circuit (ASIC) as digital transmitters. Each chain comprises the generation of a binary pulse train, which includes the modulated RF waveform positioned at the targeted carrier frequency. The signal encoding is based on pulse‐width modulation combined with delta‐sigma modulation at sampling rates around 24.5 Gsamples/s, enabling high coding efficiency and a large spurious‐free bandwidth [9]. The concept is proved with 8 chains integrated in an FPGA, whereby the number of chains is limited by the high‐speed interfaces realized by the board implementation. It allows to position carriers of 5 or 10 MHz bandwidth between 0.9 and 4 GHz, meets the required signal performance, and provides a coding efficiency of 50% and 100 MHz of spurious‐free bandwidth. Within this bandwidth, the mandatory requirements on spectral emission are met. If a spurious‐free bandwidth of two times the radio band is provided, no additional filtering is required for spurious emissions and noise suppression beside the radio band (RB) filtering. These results show significant performance improvements compared to prior research results [9]. Further progression is expected when utilizing new FPGA families with a higher sampling rate and an increased number of high speed interfaces used as RF signal ports.

The RF digital signal provided by the FPGA has to be amplified to achieve the signal level targeted at the antenna input. Switched mode amplifiers allow to maximize efficiency as well as to utilize the digital modulation scheme available at the differential interface. Realized as an integrated circuit, it allows to design amplifiers with a form factor suited for mounting behind the antennas, adapted to the grid of the antenna array and enabling a compact system integration. Prototypes realized in GaN technology provide 38 dBm output power in the frequency band between 3.4 and 4.2 GHz [10]. The amplifier is followed by a filter to suppress the unwanted spurious emissions and noise signals. Figure 16‐2 shows a schematic architecture of the discussed multi‐antenna transmitter with digital transmitter, PA, filter and antenna as the mandatory parts.

Fibre‐to‐the‐antenna (FTTA) links are a promising solution to connect large amounts of distributed antennas to a central BS. In the transmitter architecture, these links are placed at the RF interface between the central multi‐chain component (digital transmitter at RF frequency) and the individual RF chains (amplifier, filter) close to the antennas, as depicted in Figure 16‐2. Investigations with vertical‐cavity surface‐emitting lasers and electro‐absorption modulators (EAMs) working as electrical‐optical converters (E/O), and with photo‐diodes and EAMs working as optical‐electrical converters (O/E) show the potential of these low‐cost components to be used in high data rate transmission systems [3].

16.2.4 Full‐Duplex Transceivers

The challenge of in‐band full‐duplex (IBFD) transceivers is to simultaneously transmit and receive at the same frequency band. To be able to listen and decode a low‐power received signal while transmitting a high‐power signal, it is necessary to mitigate the self‐interference (SI) signal caused by leakages between the transmitter (Tx) and the receiver (Rx). To avoid placing the computational load of SI cancelation (SIC) on the user equipment (UE), IBFD is considered here only at the BS. The scenario considered is a frequency division duplex (FDD) or time division duplex (TDD) system, where a UE1 transmits to the BS on a certain frequency, while the BS simultaneously transmits to a UE2 on the same frequency. UE1 and UE2 are chosen to be spatially separated to avoid UE1 to interfere towards UE2. Moreover, a small cell scenario is considered, where there is a smaller difference between transmit and receive power than in large cell scenarios, thus requiring less isolation between transmitter and receiver, and therefore less SIC capability. Such transmission schemes can bring an important capacity gain compared to standard TDD [11] or FDD.

The SIC is done in several steps, as shown in Figure 16‐3. First, a circulator with only one antenna can provide around 20 dB isolation between Tx and Rx ports. Alternatively, two antennas can also be used to further increase the isolation. As a second step, analog cancelers (RFSIC) must be used in order to avoid the saturation of the low noise amplifier (LNA), and to allow the ADC to convert the useful signal within the adapted power range. Finally, a digital SIC (DSIC) after the ADC can be applied to remove the remaining part of the SI. The receiver gain must be set in order not to saturate the ADC. An additional hybrid SIC (HSIC) may also be used between the RFSIC and the DSIC. It combines a duplication of the main Tx chain (the so‐called auxiliary chain), with a digital linear filter whose role is to take into account the effect of the RFSIC, circulator, coupler, etc.

Figure 16‐3 presents the architecture. It is based on a classical 2x2 MIMO transceiver. Only a few functions have been added to manage the swap between TDD MIMO and IBFD SISO.

RFSIC mitigates the strong part of the SI and has low tracking capability. It is based on a digitally controlled vector modulator component. The HSIC mitigates the remaining linear component of the SI. The HSIC can easily manage long delays and provide medium tracking capability. The DSIC cancels the nonlinear contribution of the SI. It is a fully adaptive filter working after the ADC.

Each canceller has been evaluated in a standalone way on real signals thanks to a test bench based on a SDR transceiver board. Globally, with less than 20 dB antenna subsystem isolation, both analog and digital cancelers together are able to reduce the SI signal by 85 dB over a 40 MHz bandwidth while receiving a useful signal. The main limitation of the current solution is the noise generated by the analog cancelers. Extra nonlinear distortions of the analog cancelers are also a limiting constraint. Nevertheless, the depicted solution can lead to 69% capacity gain on the downlink (DL) on a system level [11].

16.2.5 Techniques for the Enhancement of Power Amplifier Efficiency

As it has been pointed out above, low overall power consumption is a highly desirable feature, in particular because it can increase the battery life of user devices. In this context, poor power added efficiency (PAE, i.e. the ratio between the difference of the RF output power and the RF input power to the DC input power) of the RF PA is one of the primary factors that decrease the battery life. Accordingly, the following two techniques target to enhance the PAE in 5G systems.

16.3.1 Requirements on 5G Digital HW

Device chipset and platform suppliers will face the need to support an increasing number of RATs together with the trend toward a highly diverse set of device form factors, with cars, wearable and machine‐type devices joining tablets and smartphones. This progressive increase in form factor diversity is driving multiple levels of platform support and capability, making transceiver complexity a key challenge for 5G devices. In addition, 5G devices are expected to integrate and interact with a multiplicity of sensors (e.g., those related to location and positioning, environmental conditions, image processing, etc.) that will provide context awareness to the communication and the deployed RAT, which will allow improvements in the efficiency of existing services, and help to provide new and more user‐centric and personalized services.

A heterogeneous situation similar to that of 5G devices is also valid for 5G network elements. Since cost and flexibility of deployment will also be important factors, a shift towards SW‐based implementations and virtualization technologies will be required, as detailed in Section 5.2.3. Ideally, these SW‐based implementations should be as HW‐agnostic as possible and, at the same time, supported by versatile, reconfigurable and flexible HW platforms that are able to cope with all the functionalities needed and invoked from the SW domain.

16.3.2 Complexity Analysis of the Individual Implementation of New Waveforms

An indicative way to indirectly quantify the implementation cost of digital HW is the analysis of the computation complexity of digital baseband processing blocks. The waveform generation and recovery are two of the basic digital signal processing blocks that need to be flexible and scalable in 5G system architectures due to the various possible use cases, scenarios and their requirements. In MIMO systems, for example, one waveform generation and recovery block is necessary for each antenna, and for carrier aggregation the same is true for each component carrier. In addition to that, if multiple subcarrier spacings are employed for different time‐frequency resource blocks, separate waveform generation and recovery may need to be implemented for each of them.

In this subsection, the computational complexity of the waveforms proposed for 5G and beyond are analyzed by considering individual implementations, and in the next subsection, by a harmonized implementation of multiple waveforms as proposed in Section 11.4.4.

Multi‐carrier (MC) and OFDM‐based single carrier (SC) modulations considered for 5G and beyond include:

• Conventional cylic prefix OFDM (CP‐OFDM) with windowing [13];
• Discrete Fourier transform (DFT)‐spread‐OFDM, also referred to as DFT‐s‐OFDM;
• Single carrier frequency division multiple access (SC‐FDMA);
• Zero tail DFT‐s‐OFDM (ZT‐DFT‐s‐OFDM) [14];
• FBMC with offset quadrature amplitude modulation (FBMC‐OQAM) [15] and with quadrature amplitude modulation (FBMC‐QAM) [16];
• Filtered multitone (FMT), a.k.a. pulse‐shaped OFDM (P‐OFDM) [17];
• Universal filtered multicarrier (UFMC or UF‐OFDM);
• Cyclic convolution based FBMC, a.k.a. generalized frequency division multiplexing (GFDM).

In this section, the complexity is quantified and compared in terms of the total number of real multiplications and additions.

We consider the signal processing operations involved in the generation of the MC and SC signals, as well as the recovery of the subcarrier/subchannel/subband signals and equalization in the presence of multipath propagation. Here, we do not consider the operations involved in channel estimation or calculation of the equalizer coefficients. The first reason is because those signal processing tasks are not in the user data chain, which is the one that concentrates the processing burden, and the second is because of the many existing algorithms for those tasks, making the choice of one not trivial. Moreover, we assume that all systems are perfectly synchronized.

Because all waveforms are based on MC modulation, we assume that a total of N subcarriers are available out of which N_f are occupied with symbols. We will consider first the number of real‐valued multiplications and additions to transmit one block of N_f symbols.

The transmitter (Tx) and receiver (Rx) of a CP‐OFDM system are basically built with one single inverse fast Fourier transform (IFFT) and fast Fourier transform (FFT) and, possibly, a windowing operation. The SC waveforms cyclic‐prefix‐based DFT‐s‐OFDM and ZT‐DFT‐s‐OFDM have the same complexity of CP‐OFDM plus the DFT spreading part, which slightly increases the complexity. In the case of ZT‐DFT‐s‐OFDM, the complexity is similar to cyclic‐prefix‐based DFT‐s‐OFDM, but the two main differences are that no cyclic prefix is attached and zero‐valued headers and tails on a subchannel level are added.

One of the basic and common building blocks for all waveforms is the FFT/IFFT. The number of real multiplications and additions of an N‐point FFT/IFFT using a split‐radix algorithm are given by [18]:

(16‐1)

Assuming an FBMC‐OQAM system where the prototype filter has length KM, two approaches can be adopted for the generation and recovery of the MC signal: the polyphase‐based and the frequency‐spread‐based structure.

We consider first the complexity of FBMC‐OQAM implemented with a structure based on the polyphase decomposition of the prototype filter and using a direct form realization of the polyphase components (PPC) [18]. The Tx is composed of 3 steps after the OQAM modulation:

• Phase rotations to get linear phase filters in each subcarrier, i.e., 4N_f real multiplications;
• IFFT;
• Polyphase filtering followed by block overlapping of 50%, i.e. 4KN real multiplications.

At the receiver (Rx) side, similar operations in the inverted order are implemented, including one more step: polyphase filtering, FFT, multi‐tap channel equalization per subcarrier with an equalizer of length L_eq, resulting in a complexity of 4N_fL_eq, and the OQAM demodulation. The phase rotations at the Rx side can be embedded in the equalizer coefficients.

The second approach is a frequency domain filtering, also known as frequency spread based (FS)‐FBMC‐OQAM [19], featuring also a prototype of length KN and designed using the frequency sampling approach [20] with only 2(K − 1) non‐zero coefficients in the frequency domain. In this case, the structure changes drastically. The subcarrier signals have to be spread over frequency domain samples, and each of them multiplied by one of the prototype frequency domain coefficients. The complexity of the frequency domain filtering encompasses 8N_f(K − 1) multiplications. The overlapping parts in frequency domain are all added and then transformed with an IFFT of size KN. Finally, the first M/2 samples of a given block of KN IFFT outputs are added to the last M/2 samples of the previous block to generate the serialized time domain signal. At the Rx side, the inverse operations are done. In addition to the FFT at the Rx, a frequency domain filtering with 16N_f(K − 1) multiplications is also performed.

The FMT/P‐OFDM waveforms are similar to the FBMC/OQAM case, but there is neither OQAM nor a 2‐stage up‐sampling. Nevertheless, for the calculation of the number of operations per sample, we need to consider the lower sampling rate.

The UFMC system can be parametrized between two extremes: on one end, the whole CP‐OFDM signal is filtered by one filter to reduce the out‐of‐band radiation. At the other end, each or a minimum number of resource blocks is transformed with the IFFT and filtered with its own filter. In a UFMC system with maximum granularity, N_B resource blocks each with M subcarriers require N_B FFTs of size N, where each of them has only NN_B non‐zero inputs.

The modulation is performed in the following steps: First, the signal of each subband is spread over the whole symbol length and transformed into frequency domain. Then, the filtering is performed in frequency domain, and the sum of all subbands is converted into time domain [21].

Instead of filtering and then transforming, a non‐matched filtering is applied in frequency domain [22]. The Rx then has 3 steps:

• Windowing in the time domain;
• FFT transformation of size N_uM with zero padding and half of the outputs thrown away;
• Frequency domain filtering and equalization.

The GFDM modulation scheme is based on circularly convolving each subcarrier in a block of data with a filter kernel. In contrast to OFDM, a cyclic prefix is added per block and not per symbol [23][24]. Since a circular convolution can be calculated as a multiplication of two vectors in frequency domain, then both transmitter and receiver can be efficiently implemented using the FFT.

Out of a total number of subcarriers N only N_f are used. M_B symbols per subcarrier are combined to form one transmission block. In total, N_fM_B data symbols can be transmitted per block. The prototype filter is designed to overlap with N_a adjacent subcarriers, and it is typically chosen to be an RRC filter with .

As described in [23], excluding the trivial operations like reordering, the following signal processing tasks need to be performed at the transceiver:

• Transformation of the data signal of each subcarrier into frequency domain;
• Filtering in frequency domain;
• Transformation of the signal into time domain.

The details of the corresponding receiver are described in [24]. It is important to mention that since the subcarriers are overlapping, it is necessary to cancel this interference to achieve a sufficient performance. In [24], the authors use the detected symbols to subtract the interference to adjacent subcarriers in an iterative fashion. For a constellation as large as 64QAM it was shown that iterations are sufficient. The receiver can be divided into the following signal processing tasks:

• Transformation of the signal into the frequency domain;
• Channel equalization;
• Filtering in the frequency domain;
• Iterative interference cancelation.

Let us now consider a numerical evaluation of the individual waveform implementations. For that, we calculate here only the complexity at the base station. We utilize the complexity formulas presented in detail in [25]. The metric utilized is the number of multiplications and additions normalized by the number of QAM symbols transmitted across the used subcarriers. We assume a similar overhead in terms of training or reference signals for all waveforms.

Moreover, we consider here four 3GPP New Radio (NR) wideband parameters [26]:

1. NR downlink with BS wideband and UE narrowband allocation (UE: 1 MHz, BS: 100 MHz)
2. NR downlink with wideband allocation (100 MHz)
3. NR uplink with BS wideband and UE narrowband allocation (UE: 1 MHz BS: 100 MHz)
4. NR uplink with wideband allocation (100 MHz)

In scenarios 1 and 3, six resource blocks are allocated for each UE, and 85 mobiles are served simultaneously. In scenarios 2 and 4, only one UE is served, and all 6600 available subcarriers are allocated to it.

The parameters have been chosen as given in Table 16‐1.

In Figure 16‐4, the BS complexity results related to the different waveforms for the different scenarios are shown.

16.3.3 Complexity Analysis of a Multi‐Waveform Harmonized Implementation

A flexible implementation integrating multiple waveforms in a single harmonized solution can be very useful to select the waveform that better matches a particular communication scenario and to reduce implementation costs. For this particular purpose, a generic MC waveform implementation was presented in Section 11.4.4. In such a tuneable waveform implementation, by selectively enabling or disabling particular blocks, one out of six different MC waveforms could be generated. The waveforms of interest include classical CP‐OFDM, windowed OFDM (W‐OFDM), P‐OFDM and SC‐FDMA or ZT‐DFTs‐OFDM. Furthermore, the framework is also valid to represent waveforms of the FBMC family such as FBMC‐QAM and FBMC‐OQAM.

Firstly, focusing on the transmitters for the independent waveforms, it can be noted that they all include the following blocks: one for serial‐to‐parallel data conversion, one for QAM constellation mapping, a subcarrier mapping and pilot insertion block, a block for MC modulation through FFT and, before sending the data to the channel, one parallel‐to‐serial data conversion block. However, recall that there are some extra modules needed for specific waveforms, which should be considered within the harmonized implementation:

• DFT spreading/de‐spreading: This block is intended to perform the spreading/de‐spreading operations necessary for the ZT‐DFT‐s‐OFDM waveform transmission/reception. It has the same cost as an FFT of size M;
• OQAM pre‐processing/post‐processing: The FBMC‐OQAM waveform needs a specific module for complex to real conversion of QAM symbols, up‐sampling, and time staggering. At the receiver, these operations obviously need to be reverted;
• Reconstructing IFFT block: Because of its importance for reducing the complexity of FBMC‐OQAM, we propose the simultaneous calculation of the FFTs of size N for the two real‐valued inputs involved, via a single FFT of size N with complex‐valued inputs, as shown in [27]. After performing the IFFT, the additional total cost of reconstructing each individual FFT for both two real‐valued inputs is 8N multiplications and 4N additions;
• Polyphase network (PPN): The implementations of all the waveforms that include filtering or windowing in time domain (W‐OFDM, P‐OFDM, FBMC‐QAM and FBMC‐OQAM) include a PPN, where the input data is convolved with a filter. For the complexity evaluation in the next section, it will be assumed that the prototype filter used in the PPN has real coefficients, i.e., it is symmetric in frequency domain, the most common assumption in waveform implementations.

16.3.3.1 Complexity Evaluation

The harmonized implementation at the minimum complexity requires: one FFT block of size N (common to all waveforms); one block to rebuild the FFT of two real‐valued inputs (required for FBMC‐OQAM); two blocks of real‐valued PPN filtering; and one block for DFT spreading of size M, necessary for ZT‐DFT‐s‐OFDM. Considering the complexity analysis carried out in the previous section for new waveforms, the aggregated complexity cost in terms of multiplications, additions, and floating point operations per second (flops) is [28]

(16‐2)

The complexity cost of a solution where all the waveforms are drawn together as standalone implementations is found by adding the number of multiplications, additions, or flops of all of them. The total result is

(16‐3)

Assuming the typical values and and a number of subcarriers ranging from 16 to 4096, Figure 16‐5 and Figure 16‐6 show the complexity in terms of multiplications, additions and flops of the harmonized and non‐harmonized implementations for different values of N. From basic calculations based on the values in the figures, it can be observed that the typical savings due to harmonized implementation range between 60–75%.

16.3.3.2 Multi‐Processor Baseband Architectures for 5G Network Elements

Current baseband processing architectures, such as the ones required to implement the waveforms whose complexity has been analyzed in the previous sections, typically rely on a combination of general purpose processor, DSP processors and dedicated HW due to stringent performance and power‐efficiency requirements. The flexibility and programmability of these solutions featuring fixed partitioning is typically limited since the DSPs are not efficient in general purpose processing. Further, general purpose processors are not efficient in dedicated tasks, and it is impossible to use HW accelerators for anything other than their dedicated tasks. While it is not possible to entirely remove these limitations, with a smart enough architecture it is possible to have a fully programmable and flexible computing solution for 5G baseband computation, which can be suitable for implementation in network elements, for example.

REPLICA is an architectural framework (or family of chip multi‐processors) aimed to solve the performance and programmability bottlenecks of current multi‐core processors [29]. The performance comes from a scalable latency hiding (a technique to eliminate delays caused by the shared memory system) combined with a low‐cost inter‐thread synchronization mechanism and efficient exploitation of low‐level parallelism. Programmability is achieved via support for architecture‐independent abstraction, strict memory consistency and synchronous, more deterministic execution than in current alternatives. A REPLICA chip multi‐processor (CMP) consists of P processors, M_S shared memory modules, M_l local memory modules, P instruction memory modules and a high‐bandwidth network for connecting the elements, as shown in Figure 16‐7. REPLICA processors are T_p ‐way multi‐threaded to support latency hiding of the shared memory system, where T_p is a design‐time parameter chosen so that the latency of typical memory accesses gets hidden. They feature a chained very long instruction word organization of functional units to support execution of dependent sub‐instructions within an instruction and have a stage pipeline to avoid pipeline delays that affect current processors [30].

Applying the REPLICA architecture framework for 5G baseband processing requires architectural improvements to fulfil performance requirements with affordable energy efficiency. Modifications to the threading system have been introduced, and an architectural unit to speed up the FFT computation has been added. In terms of the silicon area and power consumption, this solution looks affordable with respect to commercial general purpose processor alternatives [25].

16.3.4 Channel Decoder Implementations for 5G

5G systems should also consider advanced forward error correction (FEC) technologies such as advanced Turbo‐codes, low‐density parity check (LDPC) codes and Polar codes. From the decoder standpoint, such FEC codes are often decoded using iterative decoding strategies, relying on maximum a posteriori (MAP) or similar algorithms. 3GPP has moved forward on the selection of the coding scheme for eMBB, and LDPC and Polar codes are most likely to be considered for the data and control signals, respectively. As the data rates in 5G will be very high also on the terminal side, there is a need to develop high‐speed channel decoders that are also energy and area efficient. However, for backward compatibility with LTE, it is also of high interest to investigate flexible decoder architectures able to address Polar, LDPC or Turbo codes.

16.4.1 Architecture for Supporting MAC/PHY Cross‐Layer Reconfiguration

In this section, we describe an architecture for wireless terminals able to support advanced Medium Access Control (MAC) and physical layer (PHY) reconfigurations. The design has been motivated by the need to improve the terminal capabilities for exploiting context information and adapting the PHY to the application requirements and network operating conditions. Following this need, PHY‐layer improvements can be divided into two main groups: i) those aiming at supporting new PHY primitives, devised to configure the central frequency and the bandwidth of the transceiver, in order to optimize the spectrum utilization and minimize the interference generated to other coexisting links; ii) those aiming at supporting new PHY measurements, in order to characterize the network environment.

The terminal is based on an extension of the so‐called wireless MAC processor architecture [25], according to which the terminal transceiver is driven by a programmable state machine which specifies the MAC protocol logic and the configuration of the transceiver and receiver processing chain. The prototype has been implemented on the WARP v3 research platform, by exploiting the implementation of a complete Institute of Electrical and Electronics Engineers (IEEE) 802.11 MAC/PHY legacy stack, already available for this platform. For this reason, the design has been organized in terms of incremental extensions of the IEEE 802.11 implementation. While the generic executor of MAC/PHY state machines was implemented at the firmware level with minimal modifications of the original firmware (devised to take into account the possibility to specify chains of multiple actions), the implementation of advanced PHY layer primitives required to work on the IP cores and HW blocks of the platform [38].

The developed architecture has been applied to evaluate the benefits of dynamic bandwidth adaptation and innovative signaling mechanisms based on tones. Bandwidth adaptation is more powerful than simple adaptive modulation schemes, because it can increase robustness by identifying the most suitable spectrum portion to be utilized for transmissions. Adaptive modulation can still be utilized on top of bandwidth adaptation. Although the idea of bandwidth‐dynamic adaptation for wireless links is not new and especially relevant in the cognitive network scenario, the proposed solution is promising, since it does not require an out‐of‐band or in‐band signaling channel to be used for negotiating the bandwidth to be utilized.

16.4.2 Cognitive Dynamic HW/SW Partitioning Algorithm

The static HW/SW partitioning methods may generally lead to reduced energy consumption, but they are not reusable and not reconfigurable and thus limiting network upgrades and resource allocation. Also, the processing power cannot be shared among nodes, which can lead to load unbalancing and, thus, a decrease in efficiency. Full virtualization is not always available as the devices of the underlying network might not be able of performing such a task, or virtualization might be limited according to available physical and computational resources. Within this context, the cognitive and dynamic HW/SW partitioning algorithm’s task is to provide the best HW/SW partitioning of the 5G network functions for both device and network elements. The algorithm takes the required KPIs for a given scenario and the available HW/SW resources and optimizes for high flexibility, configurability, performance and/or energy efficiency [38].

In [38], the cognitive and dynamic HW/SW partitioning algorithm has been tested considering a dynamic hotspot use case, resulting in the LTE enhanced Node‐B (eNB) PHY layer reconfiguration according to pre‐specified measured KPIs and optimization goals that lead to higher flexibility, lower execution time and energy consumption reduction. The cognitive and dynamic HW/SW partitioning offers extended flexibility and re‐configurability inside a network node, while also ensuring the KPI requirements and further applying an optimized functional partitioning towards user‐defined KPIs. In terms of reconfiguration, the proposed solution performs its optimization operation in less than 17 ms for common scenarios.

16.5.1 Functional Modules

Versatile wireless interfaces are a key requirement for future 5G systems, as these enable to adapt to the estimated context conditions. However, to take advantage of this versatility, the interfaces have to be provided with the adequate functionality to properly estimate network conditions, and to react accordingly in the most appropriate manner, which may involve altering the operation of other wireless interfaces. To satisfy the requirements discussed above in 5G systems, the architecture of future wireless interfaces have to be designed building on three key concepts, namely, flexibility, reconfigurability and monitoring. This required functionality can be divided into three different areas: the operation of a single device, i.e. intra‐node enhancements, the coordination of multiple devices, i.e. inter‐node functionality, and the control and optimization of the network, i.e. intelligent programs to optimize performance.

For the single node operation, the most relevant concept is flexibility: to cope with the high variability of 5G application requirements and network topologies, 5G technologies will support advanced reconfiguration capabilities at both PHY and MAC levels. Architectures are needed which move from the traditional approach of a “one‐size‐fits‐all” MAC/PHY protocol stack to an innovative paradigm of on‐the‐fly configuration of context‐specific stacks, see also Section 6.4, implementing abstracted versions of wireless primitives that sit between the current ossified stacks and the fully‐programmable SDR solutions.

The control and optimization of the network deals with the optimization of network performance, and should be based on an information‐centric operation and exploit the re‐configurability and monitoring features. This requires functionality such as a monitoring library that provides access to the data collected by sensors and monitoring agents throughout the network, which should feed two modules that extract network‐wide performance and context estimations to trigger different types of optimizations. For instance, performance degradations or context variations may trigger the activation of additional network elements or switching to a radio access technology that is more robust. Moreover, we also envision the need of a global scheduler, coordinating the operation of the BSs, enabling the C‐RAN and vRAN vision as described next, and a service scheduler that coordinates the optimization of all these elements, to enable a smooth operation that precludes conflicts.

Finally, to connect these two areas, a third one is needed: multi‐node coordination. Here, we envision functionalities such as: a monitoring service which gathers data from the local monitoring agents of the multiple devices (including sensors), processes their information, and forwards it to the optimization modules; and modules for functional re‐composition, which stitch together SW and HW functions and abstract the changing of the operation of multiple devices to the performance optimizers, hence providing a technology‐agnostic re‐configurability service to the intelligent programs.

As an example of field‐use of the proposed architecture, context‐based system requirements could trigger a network‐wide partitioning and reconfiguration of HW‐accelerated and SW baseband functions tailored for different traffic service delivery and QoE needs. Out of the different available options, the flexible partitioning could result in placing i) the gNB layer‐2 and above together with the EPC functions in the cloud, ii) the gNB layer‐2 and above functions at a local MEC server or distributed unit (DU) or iii) move most of the gNB stack to the cloud and transform the remainder of the gNB into a remote radio head (RRH). This dynamic split and reconfiguration of baseband functions is complementary to the partitioning of the gNB protocol stack, either at stack or algorithm level, e.g., MAC‐PHY, Radio Link Control (RLC), Packet Data Convergence Protocol (PDCP), etc., that was promoted recently by key industry actors in [50]. See also details on related RAN split options as considered by 3GPP in Section 6.6, and related deployment options in Section 6.7.

16.5.2 SW Platform Solutions for Prototyping 5G Systems

We will now review some of the most relevant existing SW platforms that can support a vision such as the one described before. Several efforts have been done recently related to prototyping mobile networks in SW, with most of the platforms exploiting and supporting the GNU Radio development suite [51] and the Ettus Research USRP SDR platforms [52][53]. One prominent product is Amari LTE 100, a fully SW‐based LTE base station commercialized by Amarisoft [54] that offers a complete out‐of‐the‐box solution for students and researchers. While being a relevant and promising product with an outstanding computational efficiency, its closed license makes it unsuitable for MAC scheduling algorithms optimization and other advanced research fields.

The most popular open‐source LTE SDR SW available for testbeds today are Eurecom’s OpenAirInterface (OAI) [35] and openLTE [55]. OAI provides a standard‐compliant implementation of a subset of Release 10 LTE, including key elements of the network such as UE, eNB, Mobility Management Entity (MME), Home Subscriber Server (HSS), serving gateway (S‐GW) and packet gateway (P‐GW) on standard Linux‐based computing equipment (Intel x86 PC architectures). The SW can be used in conjunction with standard RF laboratory equipment available in many labs (i.e., National Instruments/Ettus USRP and PXIe platforms). Although OAI’s implementation is very complete and provides relatively good performance, the code structure is complex and difficult to customize, plus the implementation of the CN functionality does not provide a very stable performance (although the pace of updates has increased recently).

openLTE is an open‐source implementation of LTE specifications. The project includes a C library, Octave code for testing DL and UL Physical Random Access CHannel (PRACH) functionalities, GNU Radio applications for DL functionalities, both simulated and using HW platforms, and a simple implementation of an eNB using Universal Software Radio Peripheral (USRP). It runs with the Ettus Research B2x0 USRP and provides eNB, MME and HSS functionalities. openLTE code is well organized, documented and easy to customize or modify. However, it is incomplete and many features are still unstable or under development. Furthermore, it does not provide a UE, limiting the testbed capabilities in terms of instrumentation and measurement.

A relatively recent library is srsLTE [37], an open‐source platform for LTE experimentation designed for maximum modularity and code reuse and fully compliant with LTE Release 8, which can be considered as the evolution of the libLTE [56], an initial attempt that suffered from lack of functionality and poorly documented code. Although the platform provides a complete UE, this is not the case for the implementation of the eNB and core network, which are available for purchase, while the open version of the eNB lacks functionality such as Hybrid Automatic Repeat reQuest (HARQ).

Following the above overview, the OAI project by Eurecom [35] appears to be the most complete and flexible LTE SDR platform to date [57][58], and an implementation example will be described in the following sections targeting a vRAN/CRAN architecture.

16.6.1 Overall Architecture

To support the envisioned three‐tier architecture, OAI is evolving from an isolated monolithic BS concept (i.e., LTE eNB) to a more flexible and disaggregated BS spanning multiple modules. The overall architecture supports multi‐RAT, namely (e)LTE, NR and NB‐IoT as shown in Figure 16‐8. The envisioned RRU supports low‐level L1 functionalities, while more signal processing is concentrated at the DU, when using low‐latency FH links. Otherwise, more functions have to be distributed to RRUs, for example the whole PHY layer may be placed at the RRU if 3GPP split option 6 is applied. Further, the CU covers a larger area than the DU and possesses a centralized PDCP functionality to allocate the user plane among different RATs within its coverage area. The same CU also hosts the control functions of the core network. All these three‐tier components can be further managed by the global orchestrator under different deployment topologies. Please also refer to Section 6.7 for further details.

16.6.2 Deployment Topology

Since the C‐RAN concept first appeared, a single FH link per RRU that connects all the way directly to the BBU has normally been assumed. However, it is expected that the FH network will evolve to a more complex multi‐hop mesh network topology that requires switching and aggregation [63], see also Chapter 7. Hence, we focus on a multi‐segment FH network topology in Figure 16‐9. The considered topology can support a generic mesh deployment of the FH network that can be shared with other RRU traffic flows. The RRU gateways are the multiplex/de‐multiplex point in the network and can be utilized to transport not only the C‐RAN traffic, but also other traffic flows. Further, the BBU can be pooled and distributed centrally in the cloud, or at the network edge in some aggregated points. Figure 16‐9 also shows how the considered C‐RAN network can be mapped to the three‐tier architecture stated before (i.e., RRU, DU, CU) and the ones provided by Next Generation Fronthaul Interface (NGFI), such as the RRU, the radio aggregation unit (RAU) and radio cloud center (RCC) in [64], or the telecom industry, which considered a RRU, new generation central office (NGCO), and a next generation point of presence (NGPoP). Another key characteristic is how the information between the RRU and BBU is transported over the FH link. A number of FH transmission protocols are already used in the field, such as CPRI [65], OBSAI [66] and ORI [67]. However, as stressed before, these techniques consider carrying raw I/Q samples that can be utilized in the FH segment between the first and second tier of the architecture in Figure 16‐9. In light of the flexible centralization concept, different types of information are transported over the FH link based on the functional split between RRU and BBU, such as the 3GPP split options 7‐x that are described in detail in Section 6.6.2. Given the extensive adoption of Ethernet in remote clouds, data centers and the core network, the Radio over Ethernet (RoE) [68] approach is a generic, cost‐effective and off‐the‐shelf alternative for FH link traffic transport.

16.6.3 Performance Results

We evaluate the C‐RAN implementation using OAI [35], a SW‐based LTE/LTE‐A system implementation spanning the full 3GPP protocol stack with a third‐party EPC, and commercial off‐the‐shelf (COTS) UE and USRP B210 SDR. In the following, we consider two C‐RAN network deployments: (a) no RRU gateway (i.e., 1 hop between RRU/DU) and (b) a single RRU gateway (i.e., 2 hops between RRU/DU) with each FH link being made up of a 3‐meter cable. In simple, there is only 1 RRU and 1 DU in the considered C‐RAN network using split A or split B defined in [69] with 5 MHz/10 MHz radio bandwidth. In the following, some important KPIs related to C‐RAN are presented.

16.6.3.1 FH‐related KPIs: FH Link Throughput

The FH link throughput together with the theoretical rate of both 5 MHz and 10 MHz cases is shown in Figure 16‐10. First, the RAW transmission throughput only has little overhead (between 3 to 4 Mbps) compared with the theoretical rates. The UDP transportation shows little further overhead (up to 3 Mbps) compared with RAW transmission. Moreover, the applied a‐law compression scheme reaches almost 50% reduction in the FH link throughput. Further, using split B shows a gain of 43.8% in terms of FH link throughput reduction compared with split A via moving the FFT/IFFT operation to RRU, as considered in 3GPP split option 7‐1. This reduction ratio is similar to that presented in Section 6.2.2, and also close to the analysis in [60] that shows 45.3% of throughput reduction. We can also observe that the throughput is scaling with the channel bandwidth and hence the predicted FH capacity when using 20 MHz channel bandwidth without any compression scheme will be around 1 Gbps.

16.6.3.2 FH‐related KPIs: Round‐trip Time of the FH and RF Front‐end

These KPIs measure the round‐trip latency between the FH link and RF devices. Such metrics are crucial to evaluate the possible RRU‐DU functional split, and for instance NGMN adopts 250 µs as the maximum one‐way FH latency [70], and SCF categorizes the one‐way FH latency from 250 µs to the millisecond level to evaluate the applicable RRU‐DU split [71]. Here, we use the difference of timestamps at RRU side to measure both round‐trip times (RTTs). The RTT of the FH is measured as the time elapsed at the RRU between the start of sending the receiver data samples and the end of reading the corresponding transmitter data samples from the DU on the FH link. In detail, this RTT of the FH is made up of 5 components: (a) compress time, (b) FH write time, (c) FH link RTT, (d) FH read time, and (e) decompress time. Moreover, the RTT of the RF front‐end is defined as the time elapsed from the reading of data samples of RF devices until the writing of samples to RF devices, which includes the RTT of the FH.

Based on aforementioned definitions, the results are shown in Figure 16‐11. The reduction of the RTT in the FH is proportional to the reduction of throughput (by a factor of 2) when applying the a‐law compression which comes at the cost of the extra processing time for compression and decompression (see Table 16‐2) but with much fewer FH link read/write time (see Table 16‐2), which confirms the benefit of the compression in the FH network. In addition, it can be seen from Figure 16‐11(b) that the average RTT of the RF front‐end remains comparable for the 5 MHz case even without the compression since the RTT of the FH is less than the duration of one transmission time interval (TTI, 1 ms in this case) in Figure 16‐11(a). However, in case of 10 MHz, the RTT of the FH in Figure 16‐11(a) without compression is significantly larger than 1 ms, corresponding to the duration of one TTI, which in turn greatly increases the RTT of RF front‐end in Figure 16‐11(b).

Bandwidth	Compression	Compress time [µs]	FH write time [µs]	FH read time [µs]	Decompress time [µs]
5 MHz	No	‐	69.19	224.37	‐
	Yes	16.53	68.80	53.13	23.43
10 MHz	No	‐	72.35	469.53	‐
	Yes	31.70	71.95	170.13	35.93

16.6.3.4 User Plane related KPIs

We first clarify the relations between user plane (UP) and FH‐related KPIs. Taking the FH delay as an example, it can be absorbed and compensated by scheduling the transmission ahead of time, which in turn reduces the total transmitter and receiver processing time to provide extra FH transportation time. However, such shortened processing time might not be enough for some processing (e.g., Turbo decoder) in some cases [72], and it can cause an extra UP delay due to retransmission. To evaluate the UP KPIs, we use 15 Mbps/30 Mbps user traffic for 5 MHz/10 MHz in downlink direction separately.

To characterize the UP QoS from the user perspective, we measure the delay jitter and good‐put. First, the delay jitter is shown in Figure 16‐12. Due to the extra route from the user to the gateway that leads to less available transmitter/receiver processing time, the jitter of the C‐RAN deployment is larger than the one in a legacy D‐RAN, and the jitter of the case with two hops is larger than the one in a one‐hop case. Further, the measured good‐put at application level is shown in Figure 16‐13, and seven different C‐RAN deployments (A1 to A5, B1 and B2 in Table 16‐4) are considered to be compared to a legacy eNB/D‐RAN deployment. Note that the good‐put is the application‐level successful throughput that is significant from the user perspective. We observe that these deployment scenarios show almost the same good‐put variation as the D‐RAN one; that is to say, the experienced good‐put will be maintained among different RAN deployments.

Mode	Split	Protocol	Compression	Hop count
A1	A	RAW	No	1
A2	A	RAW	No	2
A3	A	UDP	No	2
A4	A	RAW	Yes	2
A5	A	UDP	Yes	2
B1	B	RAW	Yes	2
B2	B	UDP	Yes	2

For the UP delay, we measure the application RTT over the default radio bearer. It not only considers the impact of the FH link, but also the transmitter and receiver processing time at the RRU and DU of both downlink and uplink directions. Hence, we use the ping utility with a 8192 bytes packet size and 0.2 s inter‐departure time to characterize the delay in Figure 16‐14. We observe that the average RTT in a C‐RAN deployment is a little higher than the one in a legacy eNB/D‐RAN deployment. However, in the two‐hop cases (i.e., A2 to A5, B1 and B2), the long tail distribution is exhibited due to the extra route from the user to the gateway that reduces the time or transmitter/receiver processing. In this sense, once the processing cannot be finished within the available time then the re‐transmission scheme will increase the user plane delay.

16.6.4 Deployment Environment

An RRU prototype that comprises all necessary components is shown in Figure 16‐15. It contains the Pico‐ITX or other smaller motherboard (e.g., UpBoard with Intel Atom quad‐core processor), Power over Ethernet (PoE+) to support power supply, wiring for 1 Gigabit/sec Ethernet, RF front‐end components (PA, LNA, Switch), 10 MHz/PPS frequency synchronization cable, baseband‐to‐RF radio unit (e.g., USRP B200‐mini) and RF front‐end circuits.

In Figure 16‐16, the physical deployment of an indoor scenario is shown. Two distribution switches are placed and connected to the aggregation switch. As an extension, the planned outdoor deployment using a large number of RRUs (i.e., up to 64 RRU elements) and higher FH capacity is depicted in Figure 16‐17. This deployment showcases the coordination of the indoor and outdoor network segments and the orchestration on a larger scale.