Alternatives to Silicon: Will Our Best Be Anywhere Good Enough in Time?

M. J. Kelly

Centre for Advanced Photonics and Electronics, Dept. of Engineering
University of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 0FA, U.K.

1.   Introduction

The 2005 edition of the International Technology Roadmap for Semiconductors¹ draws attention to the need for post-CMOS devices within a decade. I want to argue from several premises that we are most unlikely to be ready in time. If we assume that the ITRS will be as generally accurate in the near future as it has proved in the recent past, then 45 nm and even 32 nm CMOS seem destined to arrive on time. (See Section 5 if this assumption is incorrect.) The individual transistors have been demonstrated for some years and large-scale integration has also been demonstrated. It is only the further grind of refining the technology that is left, and no one has shown any show-stoppers: the predicted ones seem to have been overcome, even if the heat dissipation means that not all devices are clocking as fast as they might.

The Roadmap is fairly sanguine about all the radical alternative technologies, but the longer CMOS continues, the harder it will be for any alternative device ideas to be good enough to take up from CMOS and continue the progress of Moore’s law for computing power. Only two, engineered tunnel barriers and nano-floating gates, seem to offer even the prospects of complementing CMOS in the future. All the others will fall away because of cost, complexity, performance, or manufacturability, or indeed all of these at once.

The engineered tunnel barriers and the nano-floating gate technologies build on much research into tunneling and quantum dots over the last decade, and it is from these studies that I will extrapolate here. I am not convinced that we have enough time to beat either of these technologies into shape to make higher performance circuits and systems at ever lower cost.

2.   Tunneling

In Si CMOS today, tunnel currents contribute to gate and other leakage, something to be suppressed. If tunnel currents are to be exploited, we will have to engineer the barriers that control them. Many attractive prototype devices have been demonstrated over the last three decades that use tunnel currents as integral to their operation, but none has entered low-cost volume production. The main problem is our inability to achieve satisfactory reproducibility of device performance within and between wafers. Several efforts have been made to produce small runs of tunnel devices, and while the in-wafer uniformity of the dc I–V characteristics can be controlled to ±5%, the wafer-to-wafer reproducibility of the same characteristics is still woefully inadequate.² I have studied a single barrier diode structure in the AlAs/GaAs materials system that has immediate applications in automotive radar systems: low sensitivity to ambient temperature of the range from -50 °C to +80 °C, low added noise and a detection efficiency and dynamic range that matches Schottky diodes – see Fig. 1. There are typically 30% variations in the current densities for fixed forward bias between wafers prepared a month apart, even under the regime of a rapid ex-situ calibration of the MBE machine to improve the precision of the actual growth of tunnel barriers.² This variability has to come down to below 10% before automated pick-and-place manufacture will be contemplated. Already this implies that tunnel barriers have to be grown with an accuracy, precision and reproducibility of order ±0.1 monolayer.

Figure 1.  The conduction band profile of the ASPAT diode (a) in the absence of an applied bias, showing the doping densities and thicknesses of the epitaxial layers, and (b) under forward bias.

Most recently, I have examined the interface roughness of tunnel barriers. We consider an ideal AlAs tunnel barrier, e.g. exactly an integer number N of monolayers thick in GaAs. Next we consider one interface layer that has a composition Al_xGa_1-xAs, where x is the Al content. We denote by T_N and T_N+1 the transmission probability of a typical electron of a given energy through an ideal barrier of N and (N+1) monolayers, respectively. If the Al is uniformly distributed across the interface layer, the tunnelling probability will be T_N exp[−xln(T_N+1/T_N)]. If the Al is segregated into areas of full coverage and areas of no coverage, the transmission probability will be (1−x)T_N + xT_N+1. The difference between these two values can be as much as 10–15% for values of (T_N+1/T_N) ~ 3 appropriate to AlAs barriers when x ~ 0.5, as illustrated in Fig. 2. The lateral scale of this segregation is also important. The typical bias across the tunnel barrier is of order 0.1 V during operation. From this, the de Broglie wavelength of the tunnelling electron is order 10 nm, and in turn the coherence area of the tunnelling electron is of order (10 nm)². This is the lateral scale on which the segregation of Al must occur, and this is not unreasonable for 500 °C growth, where lateral movement of order 0.1 μm is observed. If we consider both interfaces as having fractional coverage, we are examining columns of AlAs that could be between N and (N+2) atoms deep, and the above analysis goes through using (T_N+1/T_N)². This exacerbates the degree of variability, and the only hope is to aim to grow integer layer thickness tunnel barriers, a study of which is now underway. Unless and until this project works, we will not be able to begin to engineer tunnel barriers as a low-cost process for mainstream silicon. Or course, if either interface is more than one monolayer wide, the variability of tunnel current gets even worse.

Figure 2.  A schematic of the variation of relative tunneling probability through a single fractional layer of AlGaAs as one interface of an AlAs barrier in GaAs. It is assumed that one interface of the barrier is perfectly sharp, while the other barrier includes a monolayer of composition Al_xGa_1-xAs. Curved lines correspond to statistically uniform Al coverage; straight lines to Al segregation into regions large compared to coherence coherence area of the tunneling electron. Calculations are for T_N+1/T_N=0.5 and 0.25, normalized to tunneling through an ideal AlAs barrier with two ideal interfaces (x = 0).

Finally, test diodes for these studies have been >10 μm in diameter, which means that the segregated model is well defined. If the tunnel barrier has a diameter of only 0.02 μm, and is in the Si/SiO₂ system, the segregated model is not well defined, and studies of ID resonant tunnelling shows a much greater degree of irreproducibility than encountered in the studies described above.³

3.   Quantum dots

Nanometer-scale floating gates are nothing but quantum dots buried in the gate dielectric. A survey of the literature on quantum dots indicates that for dots of order of 5 nm in diameter, there is a 15% standard deviation in the volume of quantum dots in most materials systems, and this value has remained remarkably constant for 15 years.⁴ To get the best out of quantum dots in lasers, photon sources, nano-floating gates, etc., this standard deviation has to come to nearer 5%. This is equivalent to about ±1 monolayer in just one of the spatial dimensions. We are going to have to do better than that. One way might be to pattern the substrate and rely on this to grow dots in hollows, so that the control over dot area is at least determined by lithography rather than surface accretion. This will leave the dot height to be the focus of precision growth. Studies of precision etching will be required to see if adequate area control can be delivered. Again, until and unless the standard deviation in quantum dot volume is brought closer to 5%, we will not have nano-floating gates of sufficient uniformity to feature in the beyond-CMOS era. Is there a Gödel-like theorem here, based on kinetics and thermodynamics, that precludes quantum dots of less than a lower limit of variability from being grown at 500°C?

4.   Split-gate devices

Future CMOS transistors at 0.02 μm gate length will have lithographic features on the same scale as the split-gate devices used to study one-dimensional transport in semiconductors. Recently, studies⁵ of split-gate devices have show that the standard deviation of the threshold voltage in GaAs/AlGaAs HEMTs is of order 6% in the dark (rising to 20% when illuminated) and the standard deviation of the width of the first quantisation plateau in the conductance is of order 15% in light or dark. Although these results are compounded by the statistical position of dopants in the supply layer, the contribution from lithographic variations is at least 50%, and again this value is unacceptably large.

5.   How many gates?

Finally, if we imagine a post-CMOS regime taking over at or after the 32 nm generation of devices, by this stage there will be of order 10¹⁰ gates per chip. Both the engineered tunnel barrier and the quantum dots will have to be engineered to 6σ precision to this level of complexity, starting form where we are now. We will need to be thinking of >10¹² gates if the alternative technology is going to last for more than one or two generations.

6.   What happens if we are not ready in time?

There are at least two preceding technologies that have progressed under a Moore’s law regime, the shaft horsepower of marine turbines during 1895–1942 and the “people momentum” of jet passenger aircraft during the 1950’s and 1960’s. In both cases, it was a combination of cost and technical difficulty that together brought a halt to progress, as illustrated in Fig. 3. The last two ships (USS Iowa and USS Midway) were built for the Pacific theatre in World War II, and bombed by enemy aircraft. The 40 MW level has never been exceeded. In the case of the aircraft, the speed of sound limited the growth in the 1960’s to passenger numbers, and with the jumbo jet that has been flat since 1969. While supersonic aircraft fly faster, they have a smaller figure of merit.

Figure 3.  (a) The shaft horsepower of marine turbines, and (b) the people momentum of jet passenger aircraft (maximum passenger number n multiplied by velocity v in km/hour), showing a Moore’s law phase for earlier technologies.

In both cases, the marine and aircraft industries did not come to a grinding halt, but rather diversified, so that there is a proliferation of types of ship and plane, more carefully chosen for specific applications. For flying, the discriminators now are fuel efficiency, the in-flight experience and the eco-friendliness of the aircraft.

This diversification is already happening with the ITRS Roadmap with the “More than Moore” axis, where the raw computing power is secondary to the range of applications and services that can be provided on a single handset. The “More than Moore” axis is enabled almost entirely by semiconductors other than silicon, using superior materials properties to achieve higher power and frequency operation.

It is likely that the endpoint of computational power available to the consumer might come from improvements of software, architecture, and hardware-software co-design. One can also ask where hardware research is best placed in a post-CMOS regime. Will the discriminating feature between electronic systems migrate from the processor to the display?

The basics of quantum computing seem to be making strides, but the moves towards manufacturability have not begun in earnest, so that the effort may yet not bear fruit.

Acknowledgments

I thank my many co-workers on the topics raised here.

References

1. See http://www.itrs.net/Common/2005ITRS/Home2005.htm
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3. M. Tewordt, V. J. Law, M. J. Kelly, et al., “Electron-state lifetimes in submicron diameter resonant tunneling diodes,” Appl. Phys. Lett. 59, 1966 (1991).
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5. Z. Yang, G. A. C. Jones, M. J. Kelly, H. Beere, and I. Farrer, “Manufacturability of split-gate transistor devices – initial results,” Semicond. Sci. Technol. 21, 558 (2006).