V
Valid bit
address translation, B-46
block identification, B-7
Opteron data cache, B-14
paged virtual memory, B-56
segmented virtual memory, B-52
snooping, 357
symmetric shared-memory multiprocessors, 366
Variables
and compiler technology, A-27 to A-29
CUDA, 289
Fermi GPU, 306
locks via coherence, 389
loop-level parallelism, 316
memory consistency, 392
NVIDIA GPU Memory, 304–305
procedure invocation options, A-19
register allocation, A-26 to A-27
in registers, A-5
synchronization, 375
TLP programmer’s viewpoint, 394
VCs See Virtual channels (VCs)
Vector architectures
definition, 9
DLP
basic considerations, 264
definition terms, 309
gather/scatter operations, 279–280
multidimensional arrays, 278–279
multiple lanes, 271–273
programming, 280–282
vector execution time, 268–271
vector-length registers, 274–275
vector load/store unit bandwidth, 276–277
vector-mask registers, 275–276
vector processor example, 267–268
VMIPS, 264–267
GPU conditional branching, 303
vs. GPUs, 308–312
mapping examples, 293
multimedia instruction compiler support, A-31
vs. Multimedia SIMD Extensions, 282
peak performance vs. start-up overhead, 331
power/DLP issues, 322
vs. scalar performance, 331–332
strided access-TLB interactions, 323
Vector Functional Unit
vector add instruction, 272–273
vector execution time, 269
vector sequence chimes, 270
VMIPS, 264
Vector Instruction
DLP, 322
Fermi GPU, 305
gather-scatter, 280
instruction-level parallelism, 150
mask registers, 275–276
Multimedia SIMD Extensions, 282
multiple lanes, 271–273
Thread of Vector Instructions, 292
vector execution time, 269
vector processor example, 268
Vectorizable Loop
characteristics, 268
Grid mapping, 293
Livermore Fortran kernel performance, 331
mapping example, 293
NVIDIA GPU computational structures, 291
Vectorized code
multimedia compiler support, A-31
vector architecture programming, 280–282
vector execution time, 271
VMIPS, 268
Vectorized Loop See also Body of Vectorized Loop
definition, 309
GPU Memory structure, 304
mask registers, 275
NVIDIA GPU, 295
vector vs. GPU, 308
Vector Lane Registers, definition, 292
Vector loops
NVIDIA GPU, 294
processor example, 267
strip-mining, 303
vector vs. GPU, 311
vector-length registers, 274–275
vector-mask registers, 275–276
Vector-mask control, characteristics, 275–276
Vector Processor
caches, 305
compiler vectorization, 281
DLP processors, 322
example, 267–268
functional units, 272
gather-scatter, 280
vs. GPUs, 276
loop-level parallelism, 150
loop unrolling, 196
memory banks, 277
multiprocessor architecture, 346
NVIDIA GPU computational structures, 291
peak performance focus, 331
performance comparison, 58
PTX, 301
vs. SIMD Processor, 294–296
stride, 278
strip mining, 275
vector execution time, 269–271
vector/GPU comparison, 308
vector kernel implementation, 334–336
VMIPS, 264–265
Vector Registers
definition, 309
gather-scatter, 280
multimedia compiler support, A-31
Multimedia SIMD Extensions, 282
multiple lanes, 271–273
NVIDIA GPU, 297
NVIDIA GPU ISA, 298
performance/bandwidth trade-offs, 332
processor example, 267
strides, 278–279
Very Long Instruction Word (VLIW)
clock rates, 244
ILP, 193–196
loop-level parallelism, 315
multiple-issue processors, 194, L-28 to L-30
sample code, 252
Virtual address
address translation, B-46
AMD64 paged virtual memory, B-55
AMD Opteron data cache, B-12 to B-13
ARM Cortex-A8, 115
cache optimization, B-36 to B-39
GPU conditional branching, 303
Intel Core i7, 120
mapping to physical, B-45
memory hierarchy basics, 77–78
miss rate vs. cache size, B-37
Opteron mapping, B-55
Opteron memory management, B-55 to B-56
and page size, B-58
page table-based mapping, B-45
translation, B-36 to B-39
Virtual functions, control flow instructions, A-18
Virtualizable architecture
Intel 80x86 issues, 128
system call performance, 141
Virtual Machines support, 109
VMM implementation, 128–129
Virtualizable GPUs, future technology, 333
Virtual machine monitor (VMM)
characteristics, 108
requirements, 108–109
Virtual Machines ISA support, 109–110
Xen VM, 111
Virtual Machines (VMs)
Amazon Web Services, 456–457
cloud computing costs, 471
ISA support, 109–110
protection, 107–108
protection and ISA, 112
server benchmarks, 40
and virtual memory and I/O, 110–111
WSCs, 436
Xen VM, 111
Virtual memory
basic questions, B-44 to B-46
block identification, B-44 to B-45
block placement, B-44
block replacement, B-45
vs. caches, B-42 to B-43
classes, B-43
definition, B-3
fast address translation, B-46
Multimedia SIMD Extensions, 284
multithreading, 224
paged example, B-54 to B-57
page size selection, B-46 to B-47
parameter ranges, B-42
Pentium vs. Opteron protection, B-57
protection, 105–107
segmented example, B-51 to B-54
strided access-TLB interactions, 323
terminology, B-42
Virtual Machines impact, 110–111
writes, B-45 to B-46
Virtual methods, control flow instructions, A-18
VLIW See Very Long Instruction Word (VLIW)
VLR See Vector-length register (VLR)
VLSI See Very-large-scale integration (VLSI)
VMCS See Virtual Machine Control State (VMCS)
VMIPS
basic structure, 265
DLP, 265–267
double-precision FP operations, 266
gather/scatter operations, 280
ISA components, 264–265
multidimensional arrays, 278–279
Multimedia SIMD Extensions, 282
multiple lanes, 271–272
vector execution time, 269–270, G-6 to G-7
vector vs. GPU, 308
vector-length registers, 274
vector load/store unit bandwidth, 276
vector processor example, 267–268
VLR, 274
VMM See Virtual machine monitor (VMM)
VMs See Virtual Machines (VMs)
Voltage regulator modules (VRMs), WSC server energy efficiency, 462
Volume-cost relationship, components, 27–28
VOQs See Virtual output queues (VOQs)
VRMs See Voltage regulator modules (VRMs)
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