Chapter 5

Getting the Hang of Flip-Flops

In This Chapter

Unlocking the key to latches

Finding out about flip-flops

Building basic flip-flop circuits

If the title of this chapter brings up images of strolling on the beach in high summer without tripping over, we apologise. The flip-flops that we’re concerned with aren’t the sort you wear on your feet, but the electronic kind. A flip-flop is a circuit that stores data, and as such flip-flops are the basis of modern computers.

In this chapter, you discover how to work latches which allow you to make logic circuits, and then go on to build simple flip-flops which allow you to make much faster logic circuits.

Looking at Latches

A latch is a logic circuit that has two inputs and one output. One of the inputs is called the SET input and the other is called the RESET input.

Latch circuits can be active-high or active-low. The difference is determined by whether the operation of the latch circuit is triggered by high or low signals on the inputs (refer to Chapter 2 of this minibook for an explanation of high and low in the context of logic circuits):

Active-high circuit: Both inputs are normally tied to ground (low) and the latch is triggered by a momentary high signal on either of the inputs.

Active-low circuit: Both inputs are normally high and the latch is triggered by a momentary low signal on either input.

In an active-high latch, both the SET and RESET inputs are connected to ground. When the SET input goes high, the output also goes high. When the SET input returns to low, however, the output remains high. The output of the active-high latch stays high until the RESET input goes high. Then, the output returns to low and goes high again only when the SET input is triggered again.

In other words, the latch remembers that the SET input has been activated. If the SET input goes high for even a moment, the output goes high and stays high, even after the SET input returns to low. The output returns to low only when the RESET input goes high.

On the other hand, in an active-low latch the inputs are normally held at high. When the SET input momentarily goes low, the output goes high. The output then stays high until the RESET input momentarily goes low.

In fact most latch circuits have a second output that’s simply the first output inverted. So whenever the first output is high, the second output is low, and vice versa. These outputs are usually referred to as Q and .

The notation is usually pronounced ‘bar Q’ or ‘Q bar’, though just to confuse you some people pronounce it ‘not Q’. The horizontal bar symbol over a label is a common logical shorthand for inversion. That is, is the inverse of Q. If Q is high, is low, and if Q is low, is high.

You can create an active-high latch fairly easily from a pair of NOR gates, as shown in Figure 5-1. (As we explain in Chapter 2 of this minibook, the output of a NOR gate is high if both inputs are low; otherwise, the output is low.) In this circuit, the SET input is connected to one of the inputs of the first NOR gate and the RESET input is connected to one of the inputs of the second NOR gate. The trick of the latch circuit is that the output of the NOR gates are cross-connected to the remaining NOR gate inputs. In other words, the output from the first NOR gate is connected to one of the inputs of the second NOR gate, and the output from the second NOR gate is connected to one of the inputs of the first NOR gate.

Figure 5-1: Schematic diagram for an active-high latch.

Figure 5-2 shows the schematic for an active-low latch. As you can see, the only difference between this schematic and the one shown in Figure 5-1 is that the active-low latch uses NAND gates instead of NOR gates. Notice also in this diagram that the inputs are referred to as and rather than SET and RESET, which indicates that the inputs are active-low.

Figure 5-2: Schematic diagram for an active-low latch.

Projects 5-1 and 5-2, later in this section, show you how to build simple active-high and active-low latch circuits using a 4001 Quad 2-Input NOR Gate IC (integrated circuit) and a 4011 Quad 2-Input NAND Gate IC. The Q and outputs are used to drive light-emitting diodes (LEDs) so that you can see the state of the latch, and both inputs are controlled by normally open pushbuttons so that you can trigger the latch by momentarily pressing the buttons. Figures 5-3 and 5-4 depict the assembled active-high latch and the assembled active-low latch, respectively.

When you compare the schematic diagrams between these two projects, you see only two differences between them:

Gates: The active-high circuit uses a 4001 IC, which contains NOR gates, whereas the active-low uses a 4011 IC, which contains NAND gates.

Resistor and switch positions: The positions of R1 and R2 and SW1 and SW2 are reversed. In the active-high circuit, the resistors connect the two gate inputs to ground and the switches short the gate inputs to +6 V. In the active-low circuit, the resistors connect the gate inputs to +6 V and the switches short the gate inputs to ground.

Both these circuits use simple pushbutton switches to provide the trigger inputs, but we’re sure that you can easily imagine other sources for the trigger pulse. For example, in a home alarm system, the input in an active-low latch may come from a window switch that breaks contact when the window is open, and the input may come from a key lock on the alarm system’s control panel.

Figure 5-3: The assembled active-high latch (Project 5-1).

Figure 5-4: The assembled active-low latch (Project 5-2).

A latch with a SET and RESET input is often called an SR latch. The term RS latch is also used.

In some cases, you may need a latch in which one of the inputs is active-high and the other is active-low. For example, in the alarm system the key lock may send a high signal when the alarm is to be reset. Thus, the input for the alarm latch is active-low, but the RESET input is active high.

You can easily meet this requirement by adding an inverter to one of the inputs, as shown in Figure 5-5. Here, we use NAND gates to create an active-low latch but add a NOT gate to invert the RESET input. Thus, the input of this inverter is active-low and the RESET input is active-high.

Figure 5-5: A latch in which is active-low and RESET is active-high.

Going Over Gated Latches

A gated latch is a latch (check out the preceding section for details) with a third input that must be active in order for the SET and RESET inputs to take effect. This third input is sometimes called ENABLE, because it enables the operation of the SET and RESET inputs.

You can connect the ENABLE input to a simple switch. Then, when the switch is closed, the SET and RESET inputs are enabled; when the switch is open, any changes in the SET and RESET inputs are ignored.

Alternatively, you can connect the ENABLE input to a clock pulse. For example, you can connect the output of a 555 timer circuit to the ENABLE input, so that the latch inputs are operational only when the 555 timer’s output is high. Note that the ENABLE input is often called the CLOCK input. (For more information about 555 timer circuits, refer to Book III, Chapter 2.)

You can add an ENABLE input to a latch easily enough, by adding a pair of NAND gates as shown in Figure 5-6. Here the SET and RESET inputs (the SR latch) are connected to one input of each of the two NAND gates. The ENABLE input is connected to the other input of each NAND gate. Then, the output from these gates is used as the inputs to the basic latch circuit.

Figure 5-6: A gated SR latch.

Another common type of gated latch is called a gated D latch, which has just two inputs: DATA and ENABLE. When a high is received at the ENABLE input, the DATA input is copied to the output. Even if the ENABLE input then goes low, the output remains unchanged. The output can’t be changed until the ENABLE input goes high.

To create a gated D latch from a gated SR latch, you simply connect the SET and RESET inputs together through an inverter, as shown in Figure 5-7. Thus, the SET and RESET inputs are always opposite of one another. When the DATA input is high, the SET input is high and the RESET input is low. When the DATA input is low, the SET input is low and the RESET input is high.

Figure 5-7: A gated D latch.

Project 5-3 describes how to build a gated D latch using two 4011 Quad 2-Input NAND Gates. Two 4011 chips are required because the NAND gate requires a total of five gates (four NAND gates and one NOT gate) and each 4011 provides just four gates. In Chapter 2 of this minibook, you discover that you can create a NOT gate from a NAND gate by tying the two inputs of the NAND gate together. In this project, you use that technique to create the NOT gate.

Figure 5-8 shows you the assembled gated D latch. To operate it, use the first button (the one in row 4) as the DATA input and the second button (in row 8) as the ENABLE input, as follows:

Set the Q output to high: Press and hold the DATA input button, and then press and release the ENABLE input button to activate the latch. The first LED lights to indicate that the output is high.

Set the Q output to low (which sets the output to high): Press and release the ENABLE button without pressing the DATA button. The first LED goes out to indicate that the Q output is low and the second LED lights to indicate that the output is high.

Figure 5-8: The assembled gated D latch (Project 5-3).

Introducing Flip-Flops

The fact that the name of one of the fundamental building blocks of modern computing machines suggests indecision is a little odd, but the reason for its moniker becomes clear in this section.

A flip-flop is a special type of gated latch (see the preceding section). The difference between a flip-flop and a gated latch is that in a flip-flop, the inputs aren’t enabled merely by the presence of a high signal on the CLOCK input. Instead, they’re enabled by the transition of the CLOCK input. Thus, at the moment that the CLOCK input transitions from low to high, the inputs are briefly enabled. When the clock stabilises at the high setting, the output state of the flip-flop is latched until the next clock pulse.

Flip-flops are often said to be edge-triggered, because the edge of the clock signal is what triggers the flip-flop. When used in clock-driven computer circuits, edge-triggering is an important characteristic because it helps circuit designers maintain better control over the timing in circuits that contain hundreds or perhaps thousands of flip-flops.

The circuitry that enables a flip-flop to respond to just the leading edge can be pretty complicated. One of the simplest methods is to feed the clock input into a NAND gate, passing one of the legs through an inverter (see Figure 5-9). This approach works because all logic gates have a very small delay between the time a signal arrives at the input and the correct signal arrives at the output.

Figure 5-9: The clock transitions from low to high.

Here we guide you through what happens when the clock transitions from low to high in Figure 5-9:

1. Initially, the clock input is low. The inverter causes the first input to the NAND gate (marked ‘1’ in the figure) to be high, while the second input is low. Because the inputs aren’t both high, the output from the NAND gate at point 2 in the figure is high. The second inverter inverts the NAND gate output and so the final output from the circuit at point 3 is low, just like the clock input.

2. When the clock input goes high, the second input to the NAND gate goes high immediately. However, it takes a tiny fraction of a second for the inverter to respond, and so for that period the output from the inverter is still high. Thus, both inputs to the NAND gate are high for a few ms, which causes the output from the NAND gate at point 2 in the figure to go low. Then, the second NOT gate inverts the NAND gate output, causing the output at point 3 to go high for a brief moment.

3. When the first NOT gate catches up and its output goes low (at point 1 in the figure), the NAND gate responds to the low and high input by setting its output to high at point 2. The second NOT gate then inverts that output at point 3.

The net result of the circuit in Figure 5-9 is that long clock pulses are turned into short clock pulses. The duration between the pulses remains the same, but the high part of the pulse becomes much shorter.

Flip-flops are designed for use in circuits that use steady clock pulses. An easy way to provide clock pulses for a flip-flop circuit is to use a 555 timer IC, as we describe in Book III, Chapter 2. However, the input source for the CLOCK input of a flip-flop doesn’t have to be an actual clock; it can also be a one-shot input triggered by a pushbutton.

As with latches, several different types of flip-flops exist. Here are the most common:

SR flip-flop: Similar to an SR latch (check out the earlier Figure 5-6). Besides the CLOCK input, an SR flip-flop has two inputs, labelled SET and RESET. If the SET input is high when the clock is triggered, the Q output goes high. If the RESET input is high when the clock is triggered, the Q output goes low.

In an SR flip-flop, both the SET and RESET inputs shouldn’t be high when the clock is triggered. This situation is considered an invalid input condition, and the resulting output isn’t predictable if this condition occurs. In short, it won’t work.

D flip-flop: Has just one input in addition to the CLOCK input. This input is called the DATA input. When the clock is triggered, the Q output is matched to the DATA input. Thus, if the DATA input is high, the Q output goes high, and if the DATA input is low, the Q output goes low.

Most D-type flip-flops also include S and R inputs that let you set or reset the flip-flop. Note that the S and R inputs in a D flip-flop ignore the CLOCK input, and so if you apply a high to either S or R, the flip-flop is set or reset immediately, without waiting for a clock pulse.

JK flip-flop: A common variation of the SR flip-flop. A JK flip-flop has two inputs, labelled J and K. The J input corresponds to the SET input in an SR flip-flop and the K input corresponds to the RESET input.

The difference between a JK flip-flop and an SR flip-flop is that both inputs can be high in the former. When both the J and K inputs are high, the Q output is toggled, which means that the output alternates between high and low. For example, if the Q output is high when the clock is triggered and J and K are both high, the Q output is set to low. If the clock is triggered again while J and K remain high, the Q output is set to high again, and so on, with the Q output alternating from high to low at every clock tick.

T flip-flop: A JK flip-flop whose output alternates between high and low with each clock pulse. Toggles are widely used in logic circuits, because you can combine them to form counting circuits that count the number of clock pulses received.

You can create a T flip-flop from a D flip-flop by connecting the output directly to the D input. As a result, whenever a clock pulse is received, the current state of the Q output is inverted (that’s what the output is) and fed back into the D input, causing the output to alternate between high and low.

You can also create a T flip-flop from a JK flip-flop simply by hard-wiring both the J and K inputs to high. When J and K are high, the JK flip-flop acts as a toggle.

Although you can construct your own flip-flop circuits using NAND gates, an easier option is to use ICs that contain flip-flops. One common example is the 4013 Dual D Flip-Flop. This chip contains two D-type flip-flops in a 14-pin DIP (that is, a dual inline package). Table 5-1 lists the pinouts – what each pin does.

When you use one of the flip-flops in a 4013 IC, be sure to connect any unused inputs to ground. All unused inputs in CMOS logic chips need to be connected to ground, but for simple breadboard circuits the ground connections aren’t usually required. However, the DATA and CLOCK inputs of a 4013 flip-flop don’t work properly if you don’t ground the SET and RESET inputs.

Building flip-flop projects

Project 5-4 shows you how to use a 4013 IC to create a basic D flip-flop. This circuit works much the same as the D-type latch you create in the earlier Project 5-3, except that it requires only one IC rather than two and the wiring is much simpler. That’s because the engineers who designed the 4013 IC crammed all the wiring between the individual NAND gates in the IC, so that you don’t have to wire the gates together on the breadboard. Instead, all you have to do is hook up the inputs and the outputs and watch the circuit work. Figure 5-10 shows the assembled circuit.

Figure 5-10: The assembled D flip-flop circuit (Project 5-4).

Project 5-5 shows you how to build a T flip-flop in which each press of a button causes an output LED to alternate between on and off. For this project, the output from the flip-flop is connected to the DATA input. Then, each time the CLOCK input goes high, the inverted output from the output is fed into the DATA input, causing the Q output to invert. Figure 5-11 shows the assembled circuit.

Figure 5-11: The assembled T flip-flop circuit (Project 5-5).

Debouncing a clock input

When you use a mechanical switch to trigger the clock input of a flip-flop, the switch is very likely to have some mechanical bounce. This bounce happens when the switch contacts don’t close completely cleanly; instead, the contacts bounce a little bit when they first touch each other.

Even though these bounces are usually just a few ms apart, they can end up confusing the flip-flop, which thinks that each bounce of the switch contacts is a separate press of the button. So instead of just turning the LED attached to the Q output from off to on, a single press of the button may turn it from off to on, and then back off, and then on, and then off again and so on until the switch settles down into its fully-closed position.

You can debounce a mechanical switch – that is, eliminate the bounce effect – in a number of different ways. The easiest method is to connect the mechanical switch to a one-shot timer circuit that uses an RC network (with a resistor and a capacitor; see Book II, Chapter 3) to create a very short time interval such as 10 or 20 ms. Though short, this interval is enough to eliminate the negative bouncing effect.

For more information about how to build a one-shot circuit using a 555 timer IC, refer to Book III, Chapter 2.