3.1.1 Introduction to VLSI

Very large-scale integration (VLSI) is a type of integration. Millions of transistors are fabricated in one single IC under this category. Microprocessors and micro-controllers also come under this VLSI category. Due to the complexity of the circuitry, these types of circuits are not possible to verify, fabricate, or breadboard. These circuits require a special type of tool or software for verification and fabrication. It is very difficult to design computer-aided techniques (CAD) with VLSI digital circuits. Therefore, VLSI-CAD has been introduced to solve these types of complexity.

3.1.2 Analog and Digital VLSI

VLSI is also an HDL. It is used to simulate digital and analog signals. But here, we will discuss only digital design. Analysis and design of analog mixed signal (AMS) is not included in this book. The basics of design and analysis of HDLs are described in this chapter.

3.1.3 Machine Language and HDLs

Machine language and HDLs are those languages used in digital design to perform all types of operations. We know that all operations are performed by machine language in a digital system. These two languages play a very important role in the design of digital systems. These languages are also used to design high-frequency synthesizers for communications. The next subsection describes the design methodologies of any circuit for simulation and synthesis.

3.1.4 Design Methodologies

Design methodology is an initial stage which represents design methodology sub-blocks. There are two types of design methodologies.

i) Top-down design methodology

In this design methodology, we can define top-level design block and then sub-level blocks. Further, sub-blocks are divided into leaf-cells. These leaf-cells cannot be further divided. This design method is called top-down design methodology (Figure 3.1).

ii) Bottom-up design methodology

In this design methodology, we can define the bottom-level design block available to us. With the help of leaf-cells, we can build bigger macro cells. These bigger cells can be used to design higher levels of blocks. This design method is called bottom-up design methodology (Figure 3.2).

3.1.5 Design Flow

This section describes the design flow of the VLSI IC circuits (Figure 3.3). The design specification is the main parameter to design any VLSI IC circuit. First, the rectangular block describes the specifications of the design. Next, the block describes the behavior of the design to be used in HDL. A functional verification block is used to verify RTL synthesis and simulation. It also tests Verilog code for logic synthesis. The next block is the preparation of a gate level netlist for logical verification and testing. If testing or verification fails, then codes will be tested again. Floor planning, automatic place and route are important procedures before the physical layout. The next step is physical layout; once this is complete, the next step is layout verification. And, finally, the last and final step to complete the process is implementation. If the layout is verified, we can say that the circuit can be fabricated on chip.

3.2.1 Gate Level

In the gate level of abstraction, a module is designed with logic gates and these gates are interconnected through nets. A description of this level is similar to the gate-level diagram. When circuits are simple, this level of abstraction is used for design.

3.2.2 Dataflow Level

In the dataflow level of abstraction, specific dataflow is used for design. In this method, we know how dataflows between hardware registers and how data will be processed in the circuit.

3.2.3 Behavioral Level

A behavioral level of abstraction is also called an algorithmic level. The behavioral level is the highest level of abstraction. Using this method, a module can be designed using the desired algorithm without concern about hardware details. This level of abstraction is similar to programing in C language.

3.2.4 Switch Level

Switch level is the lowest level of abstraction. In this, design can be implemented among the switches, storage nodes, interconnecting wires, and input/output blocks. With this method, we should have knowledge about switch-level implementation in Verilog. It is difficult to design complex circuits using this method. This method is generally used to design low-power devices.

3.3.1 Comments

Comments are used to understand the program and documentation. There are two types of comments in Verilog. ZFirst is a one-line comment and the next are multiple-line comments.

Y = A & B; //This is an example of a one-line comment
Z = #10(B | C); //time parameter
/* this is a multiple
line comment */
/* This is the testbench program
module tb();
reg a,b;
output y;
*/

3.3.2 Whitespace

There are three types of whitespace used in Verilog.

1. a) Blank spaces ()
2. b) Tabs ( )
3. c) Newlines ( )

In Verilog, whitespace is not ignored in strings.

3.3.3 Identifiers

Identifiers are used as reference names given to design so that objects can be used later in the program. These are made up from underscore (_), dollar sign ($), alphanumeric characters, and some special symbols. Identifiers cannot be started with special symbol like $, _ or numbers.

Example:

input clock; //clock in identifier
output q; //q is identifier

3.3.4 Escaped Identifiers

These are an expanded type of identifier. They begin with a backslash() special character and end with any whitespace. Whitespace and backspace cannot be considered as identifiers.

Example:

w-x+y+z

**LPU_Jalandhar*

3.3.5 Keywords

Keywords are case sensitive. These must be written in lowercase.

Example:

input a, b; //input is keywords
reg out; //reg is keywords
INPUT clock; //Illegal keywords, it must be in lowercase

3.3.6 Strings

These are a sequence of characters. String can be declared in double quotes only. However, it must be on a single line.

Example:

“Welcome to LPU Jalandhar”//it is a string
“xyz/abc”//it is string

3.3.7 Operators

There are three types of operator. These operators are used to perform binary operations.

Unary operation:

It precedes the operand. The symbol is (~).

Example:

Y = ~X;
Z = ~X && W;

Binary operation:

Binary operations perform between two operands.

Example:

Z = X && Y;
C = A | B;

Ternary operation:

Ternary operators have three operands.

Example:

Z = W ? X: Y;

3.3.8 Numbers

Numbers are used to perform various operations. There are two types of numerical systems.

Sized numbers

There is a format for sized numbers. This is used to perform these operations.

Syntax for a sized number:

<size>’ <base format> <number>

Example:

D or d = Decimal numbers = 0, 1, 2……9
O or o = Octal numbers = 0, 1………7
B or b = Binary numbers = 0,1
H or h = Hexadecimal numbers = 0, 1, 2……9, a,….e, f

Example:

4ʹb1010; //4-bit binary number
8ʹhbc; //8-bit hexadecimal number
16ʹd20; //16-bit decimal number

Unsized numbers

Unsized numbers are those numbers written without any format. They have a 32-bit default value.

Example:

12345; //32-bit decimal number by default
‘ha2; //32-bit hexadecimal number
‘o23; //32-bit octal number

3.4.1 Values

Verilog support only four values.

0 -> Logic zero, false condition
1 -> Logic one, true condition
x -> Unknown value
z -> High impedance, floating state

3.4.2 Nets

Nets connect the hardware elements. They are also called wires. Wire is a keyword. It connects inputs and output with its internal circuitry.

Example:

wire x; //declare as a net or wire
wire = 1ʹb1; //wire has 1 fixed value

3.4.3 Registers

Registers are an element of data storage, which store data temporarily for the purpose of simulation. These are hardware registers built from triggers in real circuits. They are keyword registered.

Example:

reg clear; //variable clear can hold its value
initial
begin
clear = 1ʹb0; //initialize clear to 0
#10 clear = 1ʹb1;
end

3.4.4 Vectors

Multiple bit widths can be represented as vectors. Reg or nets can also be represented as vectors.

These can be declared in the following format; [high#: low] or [low#: high#]. The left number in brackets will be the most significant bit (MSB) of the vector.

Example:

wire x; //it is scalar net
wire [7:0] y; //it is 8-bit bus
reg [0:31] addr; //it is 32-bit bus

3.4.5 Integer Data Type

This is represented as the keyword integer. In this data type, we can only use integer value.

Example:

integer count; //it is as integer data type

initial
count = 1; //

3.4.6 Real Data Type

This is represented as the keyword real. In this data type, we can only use real value.

Example:

real del; //it is a real data type
initial
begin
del = 4e8; //real no. notation
del = 2.13; //del assigned a value 2.13
end
integer i;
integer
i = del; //it is integer value so it get the value 2(rounded value)

3.4.7 Time Data Type

This is represented as the keyword time. In this data type, we can only use time parameters.

Example:

time delay; //define time
initial
delay = $time; //it saves the current simulation time

3.4.8 Arrays

The use of Array in Verilog is similar to C programing. It is allowed for integer, time, reg, and vectors. We cannot take array for real numbers.

Example:

integer count[7:0];
time point[1:100];
reg bus[31:0];

3.4.9 Memories

Memories can be represented as an Array of registers in Verilog. Each element of an Array is also called a Word. A Word may be one or more bits. In simulation, RAMs, ROMs, and other register files can be designed.

reg mes_size[0:1023];
reg [7:0] mem_addr[0:1023];