8.1.1 Delay Modeling

Three different types of delay modeling are available in Verilog:

1. Distributed-delay modeling
2. Lumped-delay modeling
3. Pin-to-Pin-delay modeling or Path-delay modeling.

8.1.2 Distributed-Delay Model

This type of delay is specified with each element of the circuit. In the case of combinational circuits, each gate has its propagation delay and is specified within the statement of all gates used in the gate-level modeling style of Verilog.

As an example in the following circuit diagram shown in Figure 8.1, the distributed delay is indicated inside the image of all the gates. The Verilog code for the same is shown in Program P8.1.

//Program P8.1
module distributed_delay (F,A,B,C,D);
output F;
input A,B,C,D;
wire w1,w2;
or #3 x1(w1,A,B);
or #3 x2(w2,C,D);
and #2 x3(F,w1,w2);
endmodule

The distributed delay can also be specified in the dataflow modeling style within the assignment statement as shown in Program P8.2 which is a re-written program of Program P8.1 in dataflow style for the same circuit shown in Figure 8.1.

//Program P8.2
module distributed_delay (F,A,B,C,D);
output F;
input A,B,C,D;
wire w1,w2;
assign #3 w1 = A&B;
assign #3 w2 = C&D;
assign #2 F = w1&w2;
endmodule

8.1.3 Lumped-Delay Model

Lumped delay is the overall delay associated with a particular circuit or module. As shown in Figure 8.2, only one delay is specified in the gate whose output is the final output of the circuit, which is calculated based on the overall delay from input to output (see Figure 8.1). Lumped delay is normally specified on the output gate. The Verilog code for the same is specified in Program P8.3.

//Program P8.3
module lumped_delay (F,A,B,C,D);
output F;
input A,B,C,D;
wire w1,w2;
assign w1 = A&B;
assign w2 = C&D;
assign #5 F = w1&w2;
endmodule

If we compare Program P8.2 and Program P8.3, it can easily be seen that the delay specified for the AND gate is the sum of delays associated with the OR gate and AND gate.

8.1.4 Pin-to-Pin-Delay Model

Delay can also be specified in the pattern of delays from individual input to output. This type of delay specification is known as pin-to-pin delay or path delay. Figure 8.3 represents the possible paths from individual inputs to the output of the circuit shown in Figure 8.2.

Let us assume that the associated delay with each path is as follows:

path A-w1-F, delay = 5
path B-w1-F, delay = 6
path C-w2-F, delay = 7
path D-w2-F, delay = 8

Pin-to-pin delay or path delay is specified in the Verilog module using specific blocks. The specify block in any module can be introduced by using keywords specify and endspecify.

The statements for pin-to-pin delays or path delays can be written within these keywords. Program P8.4 shows the format of specify block.

//Program P8.4
module path_delay (F,A,B,C,D);
output F;
input A,B,C,D;
wire w1,w2;
specify

(A = > F) = 5;
(B = > F) = 6;
(C = > F) = 7;
(D = > F) = 8;
endspecify

assign w1 = A&B;
assign w2 = C&D;
assign #5 F = w1&w2;
endmodule

8.2.1 Combinational UDPs

Combinational UDPs are those UDPs in which the output is determined by a logical combination of the inputs as in any combinational circuit. The only difference is that the UDP has only one output but the combinational circuit can have more than one.

//Program P8.6
primitive my_and (f, a, b);
output f;
input a, b;
table

//a b: f

0 0: 0;
0 1: 0;
1 0: 0;
1 1:1;
endtable

endprimitive

//Program P8.7
primitive my_and2(f, a, b);
output f;
input a, b;
table

//a b: f
0 0: 0;
0 1: 0;
1 0: 0;
1 1:1;
0 x: 0;
x 0: 0;
endtable

endprimitive

//Program P8.8
primitive mux2x1 (f, a, b, s);
output f;
input a, b, s;
table

//a b s: y
0 ? 0: 0;//“?” can be “0” or “1” or “x”
1 ? 0: 1;//“?” can be “0” or “1” or “x”
? 0 1: 0;//“?” can be “0” or “1” or “x”
? 1 1:1;//“?” can be “0” or “1” or “x”
endtable

endprimitive

//Program P8.9
module half_adder (a,b,sum,carry);
input a,b;
output sum,carry;

xor (sum,a,b);
my_and2 (carry, a,b);
endmodule

8.2.2 Sequential UDPs

Sequential UDPs are those UDPs in which the next output is decided by the combination logic of the current inputs and current output. Sequential UDPs are different from combinational UDPs in the following terms:

1. the output port needs to be declared as reg.
2. the output needs to be initialized by some value, either “0” or “1.”
3. the values of inputs, current output, and next output indicated in the table are separated by a semicolon.

The sequential UDPs can be further divided into two types: Level sensitive and edge sensitive.

//Program P8.10
primitive dff (q, d, clock, rst);
output q;
input d, clock, rst;
reg q;
initial

q = 0;
table

//d clock rst: current q: next q
? ? 1: ?: 0;//reset condition
0 1 0: ?: 0;//clk level high
1 1 0: ?: 1;//clk level high
? 0 0: ?: -;//clk level low
endtable

endprimitive

//Program P8.11
primitive EDff (q, d, clk, rst);
output q;
input d, clk, rst;
reg q;
initial q = 0;
table

//d clk rst: current q: next q
? ? 1: ?: 0; //reset condition
? (0?) 0: ?: -; //ignore + ve transition of the clk
? (x1) 0: ?: -; //ignore unknown + ve transition of the clk
? (1x) 0: ?: -; //ignore unknown –ve transition of the clk
1 (10) 0: ?: 1; //next output appears at –ve edge of the clk
0 (10) 0: ?: 0; //next output appears at –ve edge of the clk
(??) 0 0: ?: 0; //ignore change in d when clk is stable
endtable

endprimitive

8.2.3 Shorthands in UDP

The different shorthands that can be used in creating the UDP are shown in Table 8.1. So, wherever we have used the shorthand symbol, the meaning can be obtained from this table (if not explained in the text, try to use these symbols in creating different UDPs).

8.3.1 Difference between Task and Function

A task is defined as a set of instructions/statements for performing a particular functionality and that will be used in the design repeatedly. For example, a particular task includes shifting the contents from one memory location to another, performing some arithmetical operations and saving the result at a different memory location.

A function is normally used to evaluate an expression/formula which gives a single output for a particular set of inputs. For example, a function can be created for an equation 4 × ² + 3y² + xy which needs to be evaluated many times for the different values of x and y. That is why the function returns only one single value when invoked.

The differences between task and function are summarized in Table 8.2. Understanding the differences mentioned in Table 8.2 will be more effective when we consider the examples given in the upcoming sections.

Some similarities between task and function are:

1. Both function and task are defined in a module and belong to that particular module.
2. Wires are not used in any task or function. They are constructed only from behavioral statements.
3. Initial and always statements are not used in task and function.
4. Invoking of task and function is done inside the initial and always block or via another task or function.

8.3.2 Syntax of Task and Function Declaration

//Program P8.12 Task_Declaration_Syntax
task <task_name>;

< input-declaration>;
< output-declaration>;
< inout-declaration>;
< parameter-declaration>;
< reg-declaration>;
< time-declaration>;
< integer-declaration>;
< real-declaration>;
< event-declaration>;
begin
<statement_or_null>;
end
endtask

Declaration of the task starts with the keyword task and ends with keyword endtask. Task declaration is described in detail via Program P8.12. The name of the task is declared just after the keyword task followed by a semicolon (;). Input, output, and inout are declared to pass the values to and from the task. The rest are declared as per the requirement in the task statements. All declarations in any task are optional including input, output, and inout. A sequence of statements describing the task are declared between begin and end.

//Program P8.13 Function_Declaration_Syntax
function <range_or_type> <function-name>;
< input-declaration>;
< parameter-declaration>;
< reg-declaration>;
< time-declaration>;
< integer-declaration>;
< real-declaration>;
<statement including function-name>
endfunction

Declaration of function starts with keyword function and ends with keyword endfunction. Function declaration is described in detail via Program P8.13. The name of the function is very important because the return value is assigned to the function-name. That is why range or type can also be declared with the name of the function. Only input declaration is there and there is no output or inout. The rest are declared as per the requirement in the function statements. The function statement must include “function-name=” followed by the expression of input combinations. At least one input is mandatory in any function. A sequence of statements describing the function are declared between begin and end.

8.3.3 Invoking Task and Function

Declared task and function can be invoked in any module using the format given in Programs P8.14 and P8.15, respectively.

//Program P8.14 Task invocation Syntax
task_name (< outputs_from_the_task>, < input_to_the_task>);


//Program P8.15 Function Invocation Syntax
name_of_function (<inputs_to_the_function>);

8.3.4 Examples of Task Declaration and Invocation

To understand the declaration and invocation of task examples of task bitwise_oper is shown in Program P8.16.

//Program P8.16
module operation(ab-and, ab-or, ab-xor,a,b);
input [15:0] a, b;
output [15:0] ab-and, ab-or, ab-xor;
reg [15:0] ab-and, ab-or, ab-xor;
always @(a or b)
begin
bitwise_oper(ab-and, ab-or, ab-xor, a, b);//Task Invocation
end
task bitwise_oper;//Task declaration
output [15:0] ab-and, ab-or, ab-xor;
input [15:0] a, b;
begin
#10 ab_and = a & b;
ab_or = a | b;
ab_xor = a ^ b;
end
endtask
endmodule

8.3.5 Examples of Function Declaration and Invocation

To understand the declaration and invocation of task and function, an example of function check_parity is shown in Program P8.17.

//Program P8.17
module parity(parity,address);
input [31:0] address;
output parity;
reg parity;
always @(address)
begin
parity = check_parity(address); //function invocation
$display(“Parity calculated = %b”, check_parity(address)); //function invocation
end
function check_parity; //function declaration
input [31:0] addr;
begin
check_parity = ^address;
end
endfunction
endmodule