INDEX
access time
accessing patterns
adaptive branch prediction
advanced encryption standard
advanced high-performance bus
AES
AHB
AMBA
analytic bus models
application, specific
instruction processors
integrated circuit
application studies
application throughput requirements
arbitration
architecture
architecture description
area
area model
ARM pipeline
array processors
ASICs
ASIP
ASOC
aspect ratio
associative mapped
asynchronous crossbar interconnect
asynchronous system
audio
autonomous optimization control
baseline dynamic network
baseline SOC area model
battery capacity
battery power
bimodal
block size
blocking
branch
elimination
history
management techniques
prediction
table buffer
target buffer
target capture
branch prediction
dynamic
static
branch speedup
branches
breaks
BTB
buffer
design
mean request
buffers
bus
bridge
transaction
varieties
wrappers
bus based approach
bus versus NOC
bypassing
cache
directory
hits
index
misses
offset
tag
cache data
cache memory
CAS
CGRA
chaining
Chebyshev’s inequality
chip floor planning
chip implanted credit card
CLBs
clock overhead
clock skew
coarse grained reconfigurable architecture
code density
column address strobe
combined prediction method
communication bandwidth
communication latency
communications laser
comparing networks
completion signal
complex programmable logic device
concurrent processors
condition code
configurability
configurable logic block
contention time
control flow scheduling
copy-back
CoreConnect bus
cost-performance ratio
CPLD
custom instructions
customisation
customizing instruction processors
cycle
cycle time
D-caches
data dependencies
data flow scheduling
data interlocks
data type modifiers
dataflow
dataflow graph
DCT
DDR SDRAM
defect density
defects
deployment
design complexity
design effort
design fault
design for testability
design iteration
design mapping
design target miss rate
detecting instruction concurrency
diameter of the network
die
die area
die floorplan
digital still camera
direct mapping
direct networks
directory hit
dirty bit
dirty line
distance
distributed memory
divide unit
DRAM
DSP
DSP processors
DTMR
dynamic memory controller chip
dynamic network
dynamic pipelined processor
dynamic prediction
dynamic random access memory
dynamic strategy
ECC
economics of a processor
eDRAM
802.16
embedded DRAM
embedded processor
emotion engine
error
correcting codes
correction
detection
essential dependency
exceptions
execution unit
failure
fault
FDIV
feature size
fetch on demand
field programmable gate array
FIFO
first in–first out
fixed strategy
flash
flight
FMAC
forwarding
FPGA
fruit fly
fully associative mapping
fundamental resolution
gate delay
general-purpose processors
geometric block code
global miss rate
GPP
H.263
H.264
Hamming code
hit ratio
hypercube
I-buffer
I-caches
ideal and practical scaling
ILP
image compression
imprecise interrupt
index bits
initial design
initial system design
instance-specific design
instruction (action) retry
instruction decoder
data interlocks
instruction packets
instruction set
architecture
mnemonic
instruction unit
instruction window
instruction-level parallelism
integrated
cache
Intel Pentium
intellectual property
interconnect
architectures
interface
network
interleaved caches
interleaved memory
interlock unit
interlocks
interrupts
Itanium
JPEG compression
(k, d) networks
least recently used
Leon
line
line replacement
line size
lithography
Little’s theorem
load-store architecture
local miss rate
logical inclusion
LRU
Makimoto’s wave
manufacturing faults
mapping designs onto reconfigurable devices
marginal utility
Markov’s inequality
maximum rate buffer
maximum request rate buffers
mean request rate buffers
memory bandwidth
buffers
chip
consistency
design
model
module
memory timing controller
microarchitecture
MicroBlaze
MIMD
modeling product economics
module access time
module cycle time
motion
motion estimation
MP3 audio decoding
multi-level cache
multiple clock domains
multiple-issue machines
multiple-issue pipelined processor
multiprogrammed environment
multiprogramming effects
multistage interconnection network
NAND
net die area
network interface unit
network on a chip
networked ASOC
nibble mode
Nios
NOC
NOC layered architecture
nonblocking
nonblocking cache
NOR
not-in-TLB
rate
time
offered occupancy
offered request rate
on-chip peripheral bus
on-die memory design
OPB
OpenRISC
OpenSPARC
optimal pipelining
optimized design
optimum pipeline
ordering dependency
out-of-order execution
output dependency
page mode
parity
performance
physical fault
physical word sizes
pipeline delays
pipelined processor
PlayStation
PLB
Poisson
distribution
distribution of defects
fault equation
post-deployment
power
power consumption
power operating environments
prefetch
prefetching cache
principle of inclusion
printed batteries
process address
processor
core selection
customization approaches
cycle
local bus
sub-units
product costs
product economics
protocols
prototyping
quality-of-service
quantization
random replacement (RAND)
RAS
RAW
rbe
re-use
read after write
read-only memory
rechargeable batteries
reconfigurable
designs
devices
fabric
functional units
interconnects
logic
technologies
reconfiguration
overhead analysis
register bit equivalent
register bypassing
register-memory architecture
reliability
rename registers
reorder buffer
requirements
reservation stations
result bypassing
RF
RFID
RISC
ROM
routing architecture
row address strobe
saturating counter
scavenged energy
scheduling
scratchpad memory
scrubbing
SDRAM
SECDED
sectored cache
self-optimization
self-verification
sensing
sequentiality
SER
set associative mapping
shared memory
SIMD
architectures
array
simple processor
simple sequential processor
SimpleScalar toolset
situation-specific optimization
smart card
Smart Dust
SOC
memory considerations
standard buses
system model
soft and firm processor
soft error rate
soft processor
software configurable processors
software defined radio
solo miss rate
spatial locality
specifications
split cache
split I and D caches
static
interlocks
power
prediction
strategy
static networks
static pipelined processor
Strecker’s model
stride
structured ASIC
superscalar
machines
processors
switching power
synchronous system
system design process
system effects
system on a board
systems engineering
tag
temporal locality
tenured buses
3D graphics processors
thumb instructions
TLB
TMR
trace scheduling
transaction effects
transaction processing
translation lookaside buffer
triple modular redundancy
true inclusion
2D grid
two-level adaptive
two-level cache
types of pipelined processors
unified bus
unified cache
VCI
vector
chaining
processor
registers
vector functional units
video compression
virtual address
virtual component interface
virtual-to-real translation
visual
VLIW
wafer
WAR
WAW
wormhole routing
write after read
write after write
write assembly cache
write back
write-through cache
yield