Given the complexity of many processor configurations, it is not always possible to predict performance or the area required for many designs without the help of simulation or prediction tools. In this text, we provide simple tools that can give reasonable estimates of many design parameters.

The SimpleScalar tool set is used for exploring the design space for instruction processors. Its backend has been precompiled to support four architectures: Alpha, ARM, PISA (a variant of MIPS), and x86.

Figure A.1 shows the setting for the SimpleScalar web interface. Figures A.2 and A.3 present two simulated results using different L1 cache configurations and different translation lookaside buffer (TLB) configurations.

Figure A.1 Web interface for selecting different user options.

Figure A.2 Variations of different TLB settings against simulated IPC.

Figure A.3 Variations of different L1 cache settings against simulated IPC.

This web interface provides the following key features to users:

• enabling different instruction set architectures (ISAs) such as PISA, ARM, and x86;
• enabling different benchmark programs such as math.c, fmath.c, and llong.c;
• enabling different SimpleScalar simulators for various processor information; and
• providing a dynamic and real-time update to the generated figure from the web user browser.

If we want to produce a figure from the SimpleScalar web interface, we need to first select the architecture, then select the option according to the type of simulation that we want, such as getting the L1 cache or the TLB information. Finally, we can choose the simulated instructions per cycle (IPC) value or area information.

As shown in Figure A.2, the x-axis shows different TLB values and the y-axis shows different simulated IPC values. Each line in the plot refers to a single configuration of the L1 cache value.