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by Wayne Luk, Michael J. Flynn
Computer System Designs: System-on-Chip
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PREFACE
LIST OF ABBREVIATIONS AND ACRONYMS
1 Introduction to the Systems Approach
1.1 SYSTEM ARCHITECTURE: AN OVERVIEW
1.2 COMPONENTS OF THE SYSTEM: PROCESSORS, MEMORIES, AND INTERCONNECTS
1.3 HARDWARE AND SOFTWARE: PROGRAMMABILITY VERSUS PERFORMANCE
1.4 PROCESSOR ARCHITECTURES
1.5 MEMORY AND ADDRESSING
1.6 SYSTEM-LEVEL INTERCONNECTION
1.7 AN APPROACH FOR SOC DESIGN
1.8 SYSTEM ARCHITECTURE AND COMPLEXITY
1.9 PRODUCT ECONOMICS AND IMPLICATIONS FOR SOC
1.10 DEALING WITH DESIGN COMPLEXITY
1.11 CONCLUSIONS
2 Chip Basics: Time, Area, Power, Reliability, and Configurability
2.1 INTRODUCTION
2.2 CYCLE TIME
2.3 DIE AREA AND COST
2.4 IDEAL AND PRACTICAL SCALING
2.5 POWER
2.6 AREA–TIME–POWER TRADE-OFFS IN PROCESSOR DESIGN
2.7 RELIABILITY
2.8 CONFIGURABILITY
2.9 CONCLUSION
3 Processors
3.1 INTRODUCTION
3.2 PROCESSOR SELECTION FOR SOC
3.3 BASIC CONCEPTS IN PROCESSOR ARCHITECTURE
3.4 BASIC CONCEPTS IN PROCESSOR MICROARCHITECTURE
3.5 BASIC ELEMENTS IN INSTRUCTION HANDLING
3.6 BUFFERS: MINIMIZING PIPELINE DELAYS
3.7 BRANCHES: REDUCING THE COST OF BRANCHES
3.8 MORE ROBUST PROCESSORS: VECTOR, VERY LONG INSTRUCTION WORD (VLIW), AND SUPERSCALAR
3.9 VECTOR PROCESSORS AND VECTOR INSTRUCTION EXTENSIONS
3.10 VLIW PROCESSORS
3.11 SUPERSCALAR PROCESSORS
3.12 PROCESSOR EVOLUTION AND TWO EXAMPLES
3.13 CONCLUSIONS
4 Memory Design: System-on-Chip and Board-Based Systems
4.1 INTRODUCTION
4.2 OVERVIEW
4.3 SCRATCHPADS AND CACHE MEMORY
4.4 BASIC NOTIONS
4.5 CACHE ORGANIZATION
4.6 CACHE DATA
4.7 WRITE POLICIES
4.8 STRATEGIES FOR LINE REPLACEMENT AT MISS TIME
4.9 OTHER TYPES OF CACHE
4.10 SPLIT I- AND D-CACHES AND THE EFFECT OF CODE DENSITY
4.11 MULTILEVEL CACHES
4.12 VIRTUAL-TO-REAL TRANSLATION
4.13 SOC (ON-DIE) MEMORY SYSTEMS
4.14 BOARD-BASED (OFF-DIE) MEMORY SYSTEMS
4.15 SIMPLE DRAM AND THE MEMORY ARRAY
4.16 MODELS OF SIMPLE PROCESSOR–MEMORY INTERACTION
4.17 CONCLUSIONS
5 Interconnect
5.1 INTRODUCTION
5.2 OVERVIEW: INTERCONNECT ARCHITECTURES
5.3 BUS: BASIC ARCHITECTURE
5.4 SOC STANDARD BUSES
5.5 ANALYTIC BUS MODELS
5.6 BEYOND THE BUS: NOC WITH SWITCH INTERCONNECTS
5.7 SOME NOC SWITCH EXAMPLES
5.8 LAYERED ARCHITECTURE AND NETWORK INTERFACE UNIT
5.9 EVALUATING INTERCONNECT NETWORKS
5.10 CONCLUSIONS
6 Customization and Configurability
6.1 INTRODUCTION
6.2 ESTIMATING EFFECTIVENESS OF CUSTOMIZATION
6.3 SOC CUSTOMIZATION: AN OVERVIEW
6.4 CUSTOMIZING INSTRUCTION PROCESSORS
6.5 RECONFIGURABLE TECHNOLOGIES
6.6 MAPPING DESIGNS ONTO RECONFIGURABLE DEVICES
6.7 INSTANCE-SPECIFIC DESIGN
6.8 CUSTOMIZABLE SOFT PROCESSOR: AN EXAMPLE
6.9 RECONFIGURATION
6.10 CONCLUSIONS
7 Application Studies
7.1 INTRODUCTION
7.2 SOC DESIGN APPROACH
7.3 APPLICATION STUDY: AES
7.4 APPLICATION STUDY: 3-D GRAPHICS PROCESSORS
7.5 APPLICATION STUDY: IMAGE COMPRESSION
7.6 APPLICATION STUDY: VIDEO COMPRESSION
7.7 FURTHER APPLICATION STUDIES
7.8 CONCLUSIONS
8 What’s Next: Challenges Ahead
8.1 INTRODUCTION
I. THE FUTURE SYSTEM: AUTONOMOUS SYSTEM-ON-CHIP
8.2 OVERVIEW
8.3 TECHNOLOGY
8.4 POWERING THE ASOC
8.5 THE SHAPE OF THE ASOC
8.6 COMPUTER MODULE AND MEMORY
8.7 RF OR LIGHT COMMUNICATIONS
8.8 SENSING
8.9 MOTION, FLIGHT, AND THE FRUIT FLY
II. THE FUTURE DESIGN PROCESS: SELF-OPTIMIZATION AND SELF-VERIFICATION
8.10 MOTIVATION
8.11 OVERVIEW
8.12 PRE-DEPLOYMENT
8.13 POST-DEPLOYMENT
8.14 ROADMAP AND CHALLENGES
8.15 SUMMARY
APPENDIX: Tools for Processor Evaluation
REFERENCES
Index
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