R
Race-to-halt, definition, 26
Rack units (U), WSC architecture, 441
RAID (Redundant array of inexpensive disks)
data replication, 439
memory dependability, 104
WSC storage, 442
RAR See Read after read (RAR)
RAS See Row access strobe (RAS)
RAW See Read after write (RAW)
RDMA See Remote direct memory access (RDMA)
Read after read (RAR), absence of data hazard, 154
Read after write (RAW)
data hazards, 153
dynamic scheduling with Tomasulo’s algorithm, 170–171
hazards, stalls, C-55
hazards and forwarding, C-55 to C-57
instruction set complications, C-50
microarchitectural techniques case study, 253
MIPS FP pipeline performance, C-60 to C-61
MIPS pipeline control, C-37 to C-38
MIPS pipeline FP operations, C-53
MIPS scoreboarding, C-74
ROB, 192
Tomasulo’s algorithm, 182
unoptimized code, C-81
Read miss
AMD Opteron data cache, B-14
coherence extensions, 362
memory hierarchy basics, 76–77
memory stall clock cycles, B-4
miss penalty reduction, B-35 to B-36
Opteron data cache, B-14
vs. write-through, B-11
Read operands stage
ID pipe stage, 170
MIPS scoreboarding, C-74 to C-75
out-of-order execution, C-71
Realizable processors, ILP limitations, 216–220
Real memory, Virtual Machines, 110
Real-time performance, PMDs, 6
Reduced Instruction Set Computer See RISC (Reduced Instruction Set Computer)
Reductions
commercial workloads, 371
cost trends, 28
loop-level parallelism dependences, 321
multiprogramming workloads, 377
T1 multithreading unicore performance, 227
WSCs, 438
Redundancy
Amdahl’s law, 48
chip fabrication cost case study, 61–62
computer system power consumption case study, 63–64
index checks, B-8
integrated circuit cost, 32
integrated circuit failure, 35
simple MIPS implementation, C-33
WSC bottleneck, 461
WSC storage, 442
Redundant array of inexpensive disks See RAID (Redundant array of inexpensive disks)
Redundant power supplies, example calculations, 35
Register definition, 314
Register fetch (RF)
MIPS data path, C-34
MIPS R4000, C-63
pipeline branches, C-41
simple MIPS implementation, C-31
simple RISC implementation, C-5 to C-6
Register file
Fermi GPU, 306
field, 176
hardware-based speculation, 184
longer latency pipelines, C-55 to C-57
MIPS exceptions, C-49
MIPS R4000, C-64
MIPS scoreboarding, C-75
multithreading, 224
precise exceptions, C-59
RISC classic pipeline, C-7 to C-8
RISC instruction set, C-5 to C-6
speculation support, 208
structural hazards, C-13
vector architecture, 264
Register-memory instruction set architecture
architect-compiler writer relationship, A-30
dynamic scheduling, 171
Register prefetch, cache optimization, 92
Register renaming
dynamic scheduling, 169–172
hardware vs. software speculation, 222
ideal processor, 214
ILP hardware model, 214
ILP for realizable processors, 216
instruction delivery and speculation, 202
microarchitectural techniques case study, 247–254
name dependences, 153
vs. ROB, 208–210
ROB instruction, 186
sample code, 250
SMT, 225
speculation, 208–210
superscalar code, 251
Tomasulo’s algorithm, 183
WAW/WAR hazards, 220
Register result status, MIPS scoreboard, C-76
Register tag example, 177
Relative speedup, multiprocessor performance, 406
Relaxed consistency models
basic considerations, 394–395
compiler optimization, 396
WSC storage software, 439
Release consistency, relaxed consistency models, 395
Reliability
Amdahl’s law calculations, 56
example calculations, 48
modules, SLAs, 34
MTTF, 57
redundant power supplies, 34–35
transistor scaling, 21
Relocation, virtual memory, B-42
Remote node, directory-based cache coherence protocol basics, 381–382
Reorder buffer (ROB)
dependent instructions, 199
dynamic scheduling, 175
FP unit with Tomasulo’s algorithm, 185
hardware-based speculation, 184–192
ILP exploitation, 199–200
ILP limitations, 216
Intel Core i7, 238
vs. register renaming, 208–210
Repeat interval, MIPS pipeline FP operations, C-52 to C-53
Replication
cache coherent multiprocessors, 354
centralized shared-memory architectures, 351–352
coherence enforcement, 354
R4000 performance, C-70
RAID storage servers, 439
TLP, 344
virtual memory, B-48 to B-49
WSCs, 438
Reproducibility, performance results reporting, 41
Requested protection level, segmented virtual memory, B-54
Request-level parallelism (RLP)
basic characteristics, 345
definition, 9
from ILP, 4–5
MIMD, 10
multicore processors, 400
multiprocessors, 345
parallelism advantages, 44
server benchmarks, 40
Reservation stations
dependent instructions, 199–200
dynamic scheduling, 178
example, 177
fields, 176
Intel Core i7, 238–240
loop iteration example, 181
microarchitectural techniques case study, 253–254
speculation, 208–209
Response time See also Latency
performance considerations, 36
performance trends, 18–19
server benchmarks, 40–41
user experience, 4
WSCs, 450
Restorations, SLA states, 34
Returns
Amdahl’s law, 47
cache coherence, 352–353
compiler technology and architectural decisions, A-28
hardware primitives, 388
invocation options, A-19
procedure invocation options, A-19
return address predictors, 206
RF See Register fetch (RF)
Rings
process protection, B-50
RISC (Reduced Instruction Set Computer)
architecture flaws vs. success, A-45
basic concept, C-4 to C-5
cache performance, B-6
classic pipeline stages, C-6 to C-10
code size, A-23 to A-24
development, 2
ISA performance and efficiency prediction, 241
operations, 12
pipelining efficiency, C-70
simple implementation, C-5 to C-6
simple pipeline, C-7
Sun T1 multithreading, 226–227
Virtual Machines ISA support, 109
Virtual Machines and virtual memory and I/O, 110
RLP See Request-level parallelism (RLP)
ROB See Reorder buffer (ROB)
Row access strobe (RAS), DRAM, 98
Row major order, blocking, 89
RR See Round-robin (RR)
Ruby on Rails, hardware impact on software development, 4
..................Content has been hidden....................
You can't read the all page of ebook, please click here login for view all page.