Index
As this ebook edition doesn't have fixed pagination, the page numbers below are hyperlinked for reference only, based on the printed edition of this book.
A
Acceleration Request Entry (ARE) 188, 265
Acceleration Request Queue (ARQ) 188
Acceleration Requests (ARE) 317
Accelerator Coherency Port (ACP) 312
accelerators port
used, for extending cache coherency at SoC level 88, 89
Accellera SystemC
used, for system modeling 171, 172
ACE-4
used, for extending cache coherency at SoC level 89
ACE bus protocol
cache line states, rules 73
evolution 71
overview 71
system implementation, example 77
Advanced Encryption Standards (AES) 328
Advanced Host Controller Interface (AHCI) 23
Advanced Peripheral Bus (APB) 52
Advanced System Bus (ASB) 52
Advance High-performance Bus (AHB) 52
Advance Microcontroller Bus Architecture (AMBA) 49, 52
AMBA4 59
AMBA Adaptive Traffic Profile (ATP) 53
AMBA AXI-4 Coherency Extension (ACE) 53
AMBA AXI protocol 59
AMBA AXI-Stream Protocol Specification
reference link 67
AMBA Distributed Translation Interface (DTI) 53
AMBA Generic Flash Bus (GFB) 53
analog-to-digital converter (ADC) 125
APB bus protocol
characteristics 54
evolution 54
overview 54
system implementation, example 58
application processor unit (APU) 13
Application-Specific Integrated Circuit (ASIC) 359
application-specific standard products (ASSPs) 4
ARM AMBA interconnect protocols 52
ARM AMBA standard
ARM CPUs 332
hardware security paradigm 332
ARM eXtensible Interface (AXI-3) 53
ARM Security Technology
reference link 337
ARM Synchronization Primitives Development
reference link 86
ARM Trace Bus (ATB) 53
ARM TrustZone architecture
software security aspects 336, 337
audio-video broadcast (AVB) 6
automated test equipment (ATE) 26
auxiliary processor unit (APU) 10
AXI-4 and AXI-3 protocol specifications
reference link 65
AXI bus protocol
characteristics 59
evolution 59
multi-channel topology 60
overview 59
supported transactions 64
system implementation, example 65
AXI bus protocol, interface signals 60
AXI bus global signals 61
AXI low-power interface signals 64
AXI read address channel signals 62, 63
AXI read data channel signals 63
AXI write address channel signals 61
AXI write data channel signals 62
AXI write response channel signals 62
AXI coherent extension (ACE) port 20
AXI INTC software
software control mechanisms 273, 274
AXI Interrupt Controller (AXI INTC) 202
AXI Isolation Block (AIB) module 23
AXI Stream bus protocol
characteristics 66
evolution 66
handshake sequences 66
interface signals 67
overview 66
supported transactions 68
system implementation, example 70
types 66
AXI Stream bus-supported transactionsbyte stream 68
continuous aligned stream 68, 69
continuous unaligned stream 69
sparse stream 70
AXI Verification IP (VIP)
reference link 226
AXI with Coherency Extensions 71
B
barrier transactions 77
Battery Backed RAM (BBRAM) 332
Board Support Package (BSP) 341
setting up 252
bootloader, for FreeRTOS
generating 351
Build All command 290
built-in self-test (BIST) blocks 26
byte stream style 68
C
cache coherency
extending, at SoC level with accelerators port 88, 89
extending, at SoC level with ACE-4 and CCI 89
implementing, in CPUs 88
overview 87
protocols overview 87
Cache Coherent Interconnect (CCI) 20, 77
used, for extending cache coherency at SoC level 89
cache maintenance operations (CMOs) 59
cache maintenance transactions 76
CCIX consortium
reference link 120
CCIX protocol 120
architectural features 121, 122
layers 122
link layer 123
PCIe data link layer 123
PCIe physical layer 123
PCIe transaction layer 123
reference link 123
central DMA engines
chip select (CS) signal 94, 144
Clock Cycles (CC) 318
Closed-Circuit Television (CCTV) 379
Coherent Hub Interface (CHI) protocol 53
coherent transactions 76
communication protocol layers 374
mapping, onto FPGA-based SoCs 378, 379
complex SoC subsystem
building, with Vivado IDE 312-316
Compute Express Link (CXL)
reference link 119
configurable logic blocks (CLBs) 3
configuration and security unit (CSU) 9
continuous aligned stream style 68, 69
Cortex-A9
compilation options, setting 282-285
executable file, building 282-286
Cortex-A9 ACP port
system coherency, addressing with 320
Cortex-A9 CPU ACP
CPUs
cache coherency, implementing 88
Credited eXtensible Stream (CXS) protocol 53
cross-triggering debug capability
adding, to FPGA SoC design 42, 43
Cross Trigger Interface (CTI) 42
Cross Trigger Matrix (CTM) 42
Cyclic Redundancy Check 32-bit (CRC32) 161
Cyclic Redundancy Check (CRC) 99, 330
D
data access
atomicity 86
data byte 66
Data Link Layer Packet (DLLP) 105
data path models
data stream 66
DDR DRAM memory device 142, 143
DDR memory controller 138, 139
arbitration algorithm 141, 142
features 140
high priority read (HPR) 142
microarchitectural blocks 138
SoC interface characteristics 139
DDRP PHY controller
features 140
DDR SDRAM 126
design capture 31
design constraints 216
design for test (DFT) 26
Design Rules Check (DRC) 40, 43
design under test (DUT) 41
digital local loops (DLLs) 8
Digital Signal Processing (DSP) 381
using, in SoC and hardware acceleration mechanisms 364
direct current (DC) 99
directly mapped cache 133, 134
Direct Memory Access (DMA) 366
PCIe subsystem data exchange protocol example 111-113
distributed software microarchitecture
buy queue (BuyQ) 266
DMA descriptor recycle queue (DDRQ) 267
Management Data queue (MgmQ) 266
market data queue (MdataQ) 266
quantitative analysis 274
sell queue (SellQ) 266
system performance estimation 274
Distributed Virtual Memory (DVM) 71
DMA Descriptor Recycling Queue (DDRQ) 166, 188
DMA Descriptors Recycling Task (DDRT) 166, 188
DMA engines 81
data movements 82
IP-integrated DMA engines 81
standalone DMA engines 84
DMA operation descriptor 82
domain 46
Double Words (DWs) 107
DSP techniques
Zynq-7000 SoC FPGA Cortex-A9 processor cluster DSP capabilities 361
Zynq-7000 SoC FPGA DSP slices 363
Zynq-7000 SoC FPGA logic resources and DSP improvement 362, 363
E
Electronic Trading Market (ETM) 158, 187, 257, 355
Electronic Trading Market Protocol (ETMP) 187, 263, 267
Electronic Trading System (ETS) 158, 187, 312, 342
Embedded OS software design flow
for Xilinx FPGA-based SoCs 342-351
embedded software
profiling, with Vitis IDE 305, 306
running, with emulation platform 294, 295
emulation platform
used, for debugging SoC test software 300-304
used, for running embedded software 294, 295
end-to-end cyclic redundancy check (ECRC) 105
Ethernet header
fields 116
Ethernet interconnect 114
speeds, historical evolution 115
Ethernet interface
of Zynq-7000 SoC 117
Ethernet interface driver functions
reference link 272
Ethernet MAC 271
DMA engine software control mechanisms 271, 272
operation setup 273
Ethernet protocol
overview 115
reference link 117
ETS SoC boot application project
Board Support Package (BSP), setting up 261, 262
ETS SoC Cortex-A9
data exchange mechanisms 265-269
software microarchitecture 275
ETS SoC Cortex-A9 core0 application project
Board Support Package (BSP), setting up 256-260
ETS SoC design
FPGA bitstream generation 230, 231
hardware image generation 230
hardware verification, with test bench 228, 229
implementation constraints, specifying 223, 224
implementation options, specifying 222
implementing 230
implications, of using ACP interface 322-325
synthesis options, specifying 218, 219
verification test bench, customizing 226, 227
verifying, with RTL simulation 225
ETS SoC hardware microarchitecture 187
ETS SoC hardware subsystem
design capture 192
integrating, into FPGA top-level design 224
IPs, adding in PL block 202-216
IPs, configuring in PL block 202-216
Vivado project, creating 192-197
ETS SoC MicroBlaze PP application project
Board Support Package (BSP), setting up 252-255
software microarchitecture 276
ETS SoC processors
distributed software microarchitecture, defining 263
hardware microarchitecture, simplified view 264
ETS SoC projects
linker script, specifying 279, 280
ETS SoC system
address map 269
MicroBlaze PP system address map 269, 270
Executable and Linkable (ELF) 293
eXecute-in-Place (XIP) 22
External Multiplexed Input Output (EMIO) 117
F
field-programmable gate array (FPGA) 3
DSP techniques, performing with 359, 360
Finite State Machine (FSM) 218
First Stage Boot Loader (FSBL) 328, 352
flip-flops 7
floating-point unit (FPU) 14
forward error correction (FEC) 99
FPGA-based SoC
communication protocol layers mapping 378, 379
control system hardware 381-383
DSP computation, accelerating with FPGA logic 364
FPGA devices
video and image processing implementation 366
FPGA hardware design flow 30
bitstream generation 33
design specification 31
FPGA configuration 34
netlist functional simulation 32
product requirements phase 30
RTL behavioral simulation 32
RTL design 31
RTL design synthesis 32
timing analysis 33
timing simulation 33
FPGA hardware design tools 34
Dynamic Function eXchange 36
Logic Synthesis 35
verification and debug 36
Vitis High-Level Synthesis 35
Vivado Implementation 36
Vivado IP Integrator 35
Vivado Simulator 35
FPGA implementation constraints
types 221
FPGA logic
used, for accelerating DSP computation in FPGA-based SoCs 364, 365
FPGA partial reconfiguration
exploring, as alternative method 170
reference link 170
FPGA SoC board
FPGA SoC design
cross-triggering debug capability, adding to 42, 43
FPGA SoC device
general characteristics 156, 157
FPGA SoC hardware
FPGA SoC hardware design tools 36
FPGA top-level design
ETS SoC hardware subsystem, integrating into 224
frame 66
frame check sequence (FCS) field 115
full power domain (FPD) DMA 21
Full System (FS) mode 173
functions, SoC
G
gem5 framework
URL 173
used, for system modeling 172
general interrupt controller (GIC) 15, 20
General-Purpose AXI (GP AXI) 339
General-Purpose (GP) 365
General Purpose Input Output (GPIO) 94
Generic Interrupt Controller (GIC) 201
generic Quad-SPI (GQSPI) controller 22
Gen-Z consortium
reference link 118
Gen-Z fabric 120
Gen-Z protocol 118
architectural features 119, 120
geometry processor (GP) 21
Gigabit Media Independent Interface (GMII) 117
graphical user interface (GUI) 172
graphics processing unit (GPU) 8, 118
H
hardware-to-software 157
Hash Message Authentication Code (HMAC) 328
high-bandwidth memory (HBM) 7
High-Performance AXI (HP AXI) 339
high-performance computing (HPC) 6
High-Performance (HP) 365
high priority read (HPR) 142
high-speed mode 130
Hybrid Memory Cube (HMC) 8
I
Imperas, DEV - Virtual Platform Development and Simulation
reference link 31
input/output (I/O) 152
Institute of Electrical and Electronics Engineers (IEEE) 171
Instruction Set Architecture (ISA) 121, 173
integrated circuits (ICs) 93, 152
integrated design environment (IDE) 34
Integrated Logic Analyzer (ILA) 36
Intellectual Property (IP) 49, 152, 361
Inter-Integrated Circuit (I2C) 153
serial clock (SCL) 96
serial data line (SDA) 96
Internet of Things (IoT) 327
Internet Protocol (IP) 158
adding, in PL block for ETS SoC hardware subsystem 202-216
configuring, in PL block for ETS SoC hardware subsystem 202-216
Inter Processor Communication (IPC) 197, 253
Interrupt Controller (INTC) 197
Interrupt Status Register (ISR) 265
I/O peripherals (IOP) block 13
IP-integrated DMA engines 81
advantages 82
overview 81
topology 82
IP Integrator 192
Issuing Capability (IC) 130, 322
K
Key Performance Indicators (KPIs) 41, 52
L
L2 Shared Cache (L2S$) 130
L3 Common Cache (L3C$) 130
legacy off-chip interconnects
legacy Quad-SPI (LQSPI) controller 22
Level 1 Data Cache (L1D$) 130
Level 1 Instruction Cache (L1I$) 130
link cyclic redundancy check (LCRC) 123
Linux virtual machine
used, for installing Vivado tools 178
Local Area Network (LAN) 379
Local Memory Bus (LMB) 208
lookup tables (LUTs) 7
low power domain (LPD) DMA 21
M
machine learning (ML) algorithms 34
management task 161
Market Database Manager Task (MDMT) 188
Market Data Information (MDI) 190
market data queue 162
Market Data Queue (MDQ) 188
Market Management (MM) 190
maximum payload size (MPS) 114
maximum read request size (MRRS) 114
Media Processing Engine (MPE) 361
memory and storage controllers, Zynq-7000 SoC 138
memory built-in self-test (MBIST) blocks 26
memory management unit (MMU) 10
memory read (MRd) 114
memory update transactions 76
memory write (MWr) 114
MESI cache 88
message-based interrupts (MSI/MSI-X)
reference link 114
microarchitectural blocks, DDR controller
DDRC 138
DDRI 138
DDRP 138
MicroBlaze Debug Modem (MDM) 210
MicroBlaze IPC
data exchange mechanisms 265-269
MOESI 88
Monitor mode 336
multi-gigabit transceivers (MGTs) 8
Multiple Data Multiple Engines (MDMEs) 190
Multiplexed Input Output (MIO) 117
N
NEON 361
Network-on-Chip (NoC) 50
network processor (NP) 170
non-project mode (NPM) 34
non-recurring engineering (NRE) 5, 23, 152
non-return-to-zero (NRZ) transceivers 120
non-snooping transactions 76
Non-Volatile Memory (NVM) 352
Normal software execution mode 336
null byte 66
NXP
URL 97
O
OCP interconnect protocol 78
interface signals 79
overview 78
supported transactions 80
OCP Specification License
reference link 78
on-chip bus
overview 50
on-chip bus, lanes
address lane 50
control lane 50
data lane 50
on-chip interconnects
on-chip memory controller (OCM) 10, 132, 145
features and configuration parameters 145, 146
system view 145
one-time programmable (OTP) 126
OpenCL 170
Open Core Protocol (OCP) 49, 78
Open SystemC Initiative (OSCI) 171
Open Systems Interconnect (OSI) 115
Operating System (OS) 375
Oracle VirtualBox
Ownership field 165
P
packet 66
Packet Processors (PPs) 202
PCIe 8b/10b encoding
reference link 99
PCIe controller
example 110
reference link 111
PCIe end points (EPs) 100
PCIe interconnect
system performance considerations 114
system topologies 99, 100, 101, 104
PCIe memory read (MRd) request 110
PCIe protocol layers 105
data link layer 106
PCIe root complex (RC) 100
PCIe specification
reference link 106
PCIe subsystem data exchange protocol example
Peripheral Component Interface Express (PCIe) 98, 126
Peripheral Component Interface eXtended (PCI-X) 98
Physical Layer Packet (PLP) 105
Place and Route (P&R) 32
Platform Architect framework
reference link 172
position byte 66
Power, Performance, and Area (PPA) 217
synthesis tools parameters, affecting 218
tools parameter implementation, affecting 221, 222
pre-fetching 83
processing elements (PEs) 157
processor cache fundamentals 130, 131
processor cache organization 131, 132
directly mapped cache 133, 134
set-associative cache 135
terminology 132
topology 132
Processor Configuration Access Port (PCAP) 329
processor local bus (PLB) interface 10
processor MMU
processor subsystem (PS) 95, 110
creating, with Vivado IP Integrator 39, 40
Programmable Logic Controllers (PLCs) 380
Central Processing Unit (CPU) 380
Communications Interfaces (CIs) 380
history 380
Input and Output (IOs) 380
Memory Unit (MU) 380
Processing Subsystem (PS) 380
using 381
Programmable Logic (PL) 188, 312, 327, 368
project mode (PM) 34
Proof of Concept (PoC) 38
Protocol Data Unit (PDU) 375
PS block
configuring, for ETS SoC hardware subsystem 197-202
PS interconnect 23
full-power domain (FPD) 23
low-power domain (LPD) 23
pulse-amplitude modulation (PAM) 99
Q
QEMU framework
used, for system modeling 173
QSPI flash controllers
generic Quad-SPI (GQSPI) controller 22
legacy Quad-SPI (LQSPI) controller 22
Quality of Service (QoS) 59, 107, 141
Quick Emulator (QEMU) 294
using, in Vitis IDE with ETS SoC project 295-299
R
radio-frequency integrated circuit (RFIC) 125
read completion (RdC) 114
Read-Only Memory (ROM) 217
Real-Time Operating System (RTOS) 342, 381
real-time processing unit (RPU) 19
Reduced Gigabit Media Independent Interface (RGMII) 117
Rivest Shamir Adleman (RSA) 328
RTL simulation
used, for verifying ETS SoC design 225
S
Scatter Gather DMA operation 85
Secure Configuration Register (SCR) 337
Secure Hash Algorithm (SHA) 330
Secure Monitor Call (SMC) 336
Secure software execution mode 336
Semi-Soft algorithm 169
approach, using in Zynq-based SoCs 169
FPGA partial reconfiguration, exploring as alternative method 170
OpenCL 170
system-level alternative solutions, using 169, 170
Serial Peripheral Interface (SPI) 94, 153
master in slave out (MISO) 94
master out slave in (MOSI) 94
overview 94
reference link 94
serial clock (SCLK) 94
Slave select (SS) 94
set-associative cache 135
Single Data Multiple Engines (SDMEs) 190
Single Event Upsets (SEUs) 231
Single Instruction Multiple Data (SIMD) 361
Snoop Control Unit (SCU) 87, 131, 321
snoop transactions 76
SoC and hardware acceleration mechanisms
DSP, using 364
SoC architecture
exploration phase, characteristics 156, 157
SoC-based FPGA
using, for edge detection in video applications 367, 368
using, for machine vision applications 368, 369
SoC design
HDL files, generating 40
SoC hardware
creating, with Vivado IP Integrator 37, 38
initializing, and testing with user software applications 277
SoC hardware and software partitioning 158
electronic trading system 158-164
SoC hardware microarchitecture
developing 187
SoC, in ASIC technologies 23, 24
design capture 24
floorplanning 27
functional or formal verification 26
high-level design steps 24
performance and manufacturability verification 27
placement 27
power analysis 26
routing 27
RTL design 25
RTL synthesis 26
static timing analysis 26
test insertion 26
SoC interface
characteristics 127
definition, by function 125, 126
functions 125
quantitative considerations 129
SoC level
accelerators port, using to extend cache coherency 88, 89
cache coherency, extending with ACE-4 and CCI 89
SoC PS block
communication interfaces 155
dedicated hardware functions 156
memory and storage controllers 155
SoC PS Cortex-A CPU 154
SoC software design flow
steps 236
SoCs PS processors block
features 153
SoC system
SoC Technical Reference Manual (TRM)
reference link 13
SoC test software
emulation platform, used for debugging 300-304
sparse stream style 70
stacked silicon interconnect (SSI) 5
standalone DMA engines
overview 84
static memory controller (SMC) 16, 144
configuration parameters 144
features 144
microarchitecture diagram 144
Static Random-Access Memory (SRAM) 217
switching nodes 376
Synopsys Platform Architect
reference link 31
used, for system modeling 172
synthesis options
specifying, for ETS SoC design 218, 219
Syscall Emulation (SE) mode 173
SystemC/TLM2.0
used, for system modeling 173
System in a Package (SiP) 24
system-level alternative solutions
System Memory Management Unit (SMMU) 77
system modeling
with Accellera SystemC 171, 172
with gem5 framework 172
with QEMU framework 173
with Synopsys Platform Architect 172
with SystemC/TLM2.0 173
T
Technical Reference Manual (TRM) 89
tightly coupled memory (TCM) 20
Time Domain Multiplexing (TDM) 36
TLM2.0
used, for system modeling 171, 172
TLP completion with data (CplD) 110
trading algorithm task 161
Transaction Layer Packet (TLP) 105
transaction-level modeling (TLM) 171
translation look-aside buffer (TLB) 137
translation tables 137
Transmission Control Protocol and Internet Protocol (TCP/IP) 158, 377
triple timers/counters (TTCs) 20
U
Ubuntu Linux VM
reference link 179
used, for installing Vivado 186, 187
Universal Asynchronous Receiver Transmitter (UART) 153
universal serial bus (USB) 126
user application
User Datagram Protocol (UDP) 355
user software applications
building, to initialize and test SoC hardware 277
V
Verification IP (VIP) 225
Video Direct Memory Access (VDMA) 366
video processing systems
generic architecture 367
Virtex-5 FXT 11
virtual channel (VC) 123
Virtual Component Interface (VCI) 78
Virtual Machine (VM) 178
virtual prototype (VP) 25, 171
Virtual Socket Interface Alliance (VSIA) 78
Vitis 44
Vitis IDE
ETS SoC MicroBlaze software project setup 242-245
ETS SoC PS Cortex-A9 software project setup 246-251
ETS SoC software project setup 239-242
features 44
used, for profiling embedded software 305, 306
Vitis IDE embedded software design flow
overview 46
Vitis IDE, with ETS SoC project
Vivado 34
installing, on Ubuntu Linux VM 186, 187
Vivado IDE
complex SoC subsystem, building with 312-316
ETS SoC XSA archive file generation 236-239
Vivado IP Integrator 35
HDL files, generating for SoC design 40
used, for creating processor subsystem 39, 40
using, to create SoC hardware 37, 38
Vivado ML Edition
reference link 186
Vivado project
creating, for ETS SoC hardware subsystem 192-197
Vivado tools
hardware specification 178
installing, on Linux virtual machine 178
Operating Systems (OSs) 178
W
watchdog timer (WDT) 20
wireless local area network (WLAN) 126
X
Xilinx AXI VDMA engine
reference link 367
Xilinx Design Constraints (XDCs) 35, 222
Xilinx FPGA-based SoCs
using, in Embedded OS software design flow 342-351
Xilinx FPGA device features
ARM-based processing subsystem 8
configuration and system monitoring 8
design clocking 8
encryption 9
external interfaces 8
external memory interfaces 8
logic elements 7
overview 6
signal processing 7
storage 7
Xilinx FPGA devices
historical overview 5
IC 4
overview of device families 6
vertical markets 5
Xilinx SoC
history 9
Xilinx SoC FPGAs
survey, based on ARM CPU 13
Xilinx Zynq-7000 SoC family hardware features 13
Zynq-7000 I/O peripherals block 18
Zynq-7000 SoC interconnect 18
Zynq-7000 SoC memory controllers 15
Xilinx Zynq Ultrascale+ MPSoC family
overview 19
Zynq UltraScale+ MPSoC APU 20
Zynq UltraScale+ MPSoC DMA channels 21
Zynq UltraScale+ MPSoC GPU 21
Zynq-UltraScale+ MPSoC interconnect 23
Zynq UltraScale+ MPSoC IOP block 23
Zynq-UltraScale+ MPSoC IOs 22
Zynq UltraScale+ MPSoC memory interfaces 21
Zynq UltraScale+ MPSoC PMU 21
Zynq UltraScale+ MPSoC RPU 20
Zynq UltraScale+ MPSoC VCU 21
Z
Zynq-7000 SoC I2C controller
overview 97
reference link 98
Zynq-7000 SoC interfaces 138
DDR memory controller 138
on-chip memory controller (OCM) 145
static memory controller (SMC) 144
Zynq-7000 SoC memory controllers 15
QSPI flash controller 17
Static memory interfaces 16
Zynq-7000 SoC SPI controller
overview 95
reference link 95
Zynq-based SoCs
Semi-Soft algorithm approach, using 169
Zynq-UltraScale+ MPSoC IOs 22
PCIe interface 23
SATA interface 23
Zynq UltraScale+ MPSoC memory interfaces 21
DDR memory controller 22
OCM memory 22
QSPI flash controller 22
static memory interfaces 22