The system must provide an interface, which offers less than 5 ns jitter for use in coherent averaging because the maximum sampling rate is 200 MSPS. This interface should provide access to the incoming sample, a high-speed memory interface, and the time in samples because the pulse was triggered. As the bulk of the system is implemented in FPGA logic, the system is able to guarantee strict hard real-time demands in hardware; however, software interrupt and scheduling latencies should be contained to avoid buffer overruns when copying data from the ADC to the memory or network. The maximum delay for a software application running on the RUSSP is 100 μs or 10 KHz. This ensures that the software is able to process a response before the next response is acquired.

In the RUSSP design, the XUPV5's XC5VLX110T FPGA is used for signal processing. The double data rate 2 (DDR2) memory controller is used for volatile data storage during processing. The compact flash is used for nonvolatile storage of the FPGA and software configuration. The serial port is used for debugging and configuration. The gigabit Ethernet controller provides remote data and control communication. The benefit of using a Virtex-5 FPGA such as the XC5VLX110T over other FPGAs is the inclusion of DSP48 blocks. DSP48 blocks provide constant multiply and accumulate (MAC), two operand multiply, and division capabilities. The ability to execute MAC operations greatly increases the maximum operating frequency of digital filter implementations. The system is capable of storing up to 256 MB of data in the DDR2 memory for future analysis. The DDR2-400 used in RUSSP has a maximum theoretical bandwidth of 3200 MB/s and interfaces to the RUSSP though the MPMC (multiport memory controller) provided by Xilinx (2011). The gigabit Ethernet controller is connected to the processor using the PLB (processor local) bus interface and an SDMA (soft direct memory access) PIM (personality interface modules) of the MPMC. The SDMA PIM provides high-speed scatter–gather DMA (direct memory access) transfers to the Ethernet MAC so that the processor is free to process even when data are being copied into or out of main memory. The gigabit Ethernet is connected to the local network and provides ample bandwidth for simultaneous command/control and data capture. The main bottleneck in RUSSP is the throughput of the PLB bus inside the FPGA SoC. Therefore in future iterations of this design, integration of DMA peripherals will be used to reduce data transfers across the PLB bus.

The RUSSP system communicates with the user using TCP/IP on top of gigabit Ethernet. The RUSSP system is theoretically capable of providing wired gigabit Ethernet communication at 125 MB/s. Given a packet of 1500 bytes, the total overhead for IP and Ethernet is ∼4%. Given another 1% of overhead for TCP, leaves a total of 118.75 MB/s for data transmission.

A block diagram of the FPGA embedded system is shown in Fig. 9.4. The FPGA SoC is based around the PLB. PLB is a standard from IBM, which defines how components interconnect with one another in a standard bus topology. The SoC includes the following cores from Xilinx: A MPMC, universal asynchronous receiver transmitter (UART), gigabit Ethernet, System Advanced Configuration Environment compact flash controller, timer, clock generators, and a Microblaze processor.

The MPMC provides high-speed memory access to the system. It provides this through PIM. PIMs allow the memory to transfer data using some common patterns. There are PIM modules for PLB, Advanced Microcontroller Bus Architecture, DMA, Frame Buffer, Cachelink, Locallink, and a raw native interface. Three PIMs are used in our design. A Cachelink PIM is used to interface the MPMC with the processor caches. A PLB PIM is used to provide access to memory for the PLB bus peripherals. A DMA PIM is connected to the gigabit Ethernet MAC to provide high-speed data transfers.

The software runs on a Xilinx Microblaze processor. The Microblaze processor is a 32 bit reduced instruction set CPU, which is unique because it allows the engineer to make modifications to its functionality during synthesis. Notably, the processor can be configured to include a memory management unit, which is a requirement of the Linux kernel. The Microblaze core can be customized to include a floating-point unit and streaming interface to either fast simplex link or Advanced eXtensible Interface stream interfaces. This allows the core to have additional pseudo instructions added to the instruction set. 12 KB data and 4 KB instruction caches were chosen to strike a balance between resource usage and performance. The cache is backed by the MPMC, which interfaces to the DDR2 memory.

A timer/counter, interrupt controller, and UART are present in the base system to accommodate the requirements of Linux. The timer counter provides timer interrupts to the software system, the interrupt controller allows multiple interrupts to be received and decoded by the software system, and the UART provides a basic interface to the system for debugging.

The ADC uses LVDS (low-voltage differential signaling) when interfacing to the FPGA. LVDS is a differential signaling methodology, which uses a small current to generate a voltage at the receiver. The LVDS generates a 3.5 mA current on either the negative or positive net depending on the polarity of the signal. This is then transformed into a voltage using a terminating resistor. The key to making a reliable and high-speed connection between the FPGA and the ADC is to use the DIFF_TERM attribute of the FPGAs input/output block for each LVDS pair in the constraints file. This attribute turns the built-in, 100 Ω, differential termination resistor on Xilinx (2010).

Initially, the connections between the ADC and the FPGA can be represented by Fig. 9.5. The maximum operating frequency is governed by the delay, which depends on the length of wire and delay of the ADC. Because the edge rate of the ADC is significant with respect to the length of wire, the line must be treated as a transmission line. The transmission line has a delay of 170 ps/inch according to the measurement obtained in this study, which compares an 18 versus 12 inch coaxial wire. For this arrangement, the total skew is ∼6.23 ns and limits the connection to a maximum sampling rate of 160.50 MHz.

To meet the 200 MHz requirement of RUSSP system, the recovered clock feature of the ADC was implemented as shown in Fig. 9.6. The recovered clock is aligned with the data, which ensures that minimal clock skew is present (assuming equal length data/clock traces). This allows the ADC to operate at its maximum operational frequency.

The combined effects of Rayleigh scattering and stochastic scattering are known as clutter. Clutter is a combination of the many echoes that are produced in the microstructures of a material (i.e., grains). When an ultrasound wave scatters from grains, it produces a stationary scatter, which represents these grain scatterers. When the aggregate of all of the scatterer echoes are combined, they produce a static noise that hides the target echo. Therefore, these scatterings must be filtered from the signal to increase the SNR for the classification or detection system and enable accurate detection of the target. When a measurement is taken using a number of different narrowband pulses with different frequencies, the clutter echoes become randomly distributed across the pulse frequencies and can be filtered using statistical processing. For the performance evaluation of RUSSP, there is an emphasis on a postprocessing methodology called pass-through absolute minimization. Pass-through absolute minimization takes advantage of the special properties of absolute minimization (Newhouse et al., 1982) in improving the SNR but maintains the sign of the original signal such that the response can be classified by other signal processing method such as chirplet signal decomposition (CSD).

The SSP procedure has five steps as shown in Fig. 9.7. The first part is data acquisition. The second step, fast Fourier transform (FFT) gives the frequency spectrum of the received echo signal. Third step, several filters split the spectrum into different frequency bands. Next step, inverse FFT (iFFT) gives the time domain signal of each individual frequency band. The signals from each individual frequency band are first normalized and then passed into a postprocessing block for detection. This detection processor can employ different techniques such as averaging, minimization, order-statistic filters (e.g., minimization), or Bayesian classifiers (Saniie et al., 1988, 1991; Saniie and Nagle, 1992; Saniie, 1992). SSP has been successfully applied to ultrasonic flaw/target detection applications because of its robust performance.

The chirplet signal can be defined as

The method for extracting chirplet parameters utilizes the chirplet transform

The first step of this method is to extract an estimated b based on the maximum value in the time domain. Then, the parameter a, which has the highest correlation at t = b, can be used as an initial estimate. From these two values, the γ₂ parameter can be estimated, followed by γ₁, θ, and finally β. This equation for the estimation algorithm is summarized below:

CSD block diagram for estimation of chirplet parameters is shown in Fig. 9.8.

Initially, a basic averaging implementation was developed. However, it was not possible to meet timing with this original design. To explore the design space for timing closure, the original implementation was extended to support parallel operations. In the current configuration, the coherent averaging block is parallelized by a factor of four and can be represented by Fig. 9.10. Because of the concurrent nature of this design, the implementation is able to reliably meet timing requirement in this system.

Coherent since the slower distributed RAM was unable to meet the 200 MHz timing requirement, the coherent averaging block implements its memory using block RAMs (BRAMs). In Xilinx FPGAs, BRAMs are faster but have a one-cycle delay for access. Therefore, it takes two clock cycles for an accumulation to occur. The first cycle is a read cycle, and the second is a write cycle. During the read cycle, the BRAM exports the value to a register. During the write cycle, the incoming data are added to the value in the register and stored back in the BRAM.

As the SSP algorithm uses a significant number of FFTs, it is important that the FFT implementation must be highly area-efficient. The most efficient IP core available for implementing an FFT/iFFT is the Xilinx Radix 2-Lite FFT IP core (FFT, 2012). At a transform size of 4096 points, this IP core has a latency of 57,539 cycles; however, it uses only two DSP48 components, 7 BRAMs, and ∼250 slices. This low resource usage allows up to 13 FFTs to be implemented in tandem with the other components of the RUSSP.

The SSP implementation has synthesis parameters, which can be altered in EDK for changing the number of channels and the maximum number of samples. In the current configuration, the SSP algorithm uses 12 channels and 4096 samples, which is the maximum number possible given the DSP48 resources available on the FPGA. For the SSP processing, the number of FFTs required is equal to the number of channels plus one. In the current configuration, the implementation has 13 FFTs instantiated in the FPGA.

Control registers specify the number of samples to use, the start, width and offset of the SSP algorithm. The implementation makes use of a memory, which is used to load the samples into the SSP algorithm and store them after processing. The memory has two ports; one is connected to the SSP algorithm block as shown in Fig. 9.11; the other is connected to the PLB bus and is addressable by the processor.

In Fig. 9.12, the results from a four-channel instantiation of the SSP algorithm are shown. The flaw echo, located at around sample number 1750, is present in each of the channels and has unchanged amplitude. This is because the flaw echo is not a composite signal in contrast to the clutter signal, which is highly dependent on the frequency span of narrow bands. By using a pass-through absolute minimization processing block, the flaw signal maintains many of its original properties, but the frequency dependent scattering signal is substantially reduced.

The primary goal of the current implementation of the CSD algorithm is to reduce the execution time as much as possible while maintaining an adequate SNR for echo estimation. The main performance impediment for CSD is the correlation operations, which require regenerating a chirplet with different parameters thousands of times during each parameter estimation step in the algorithm. By precomputing a table of these values and manipulating this table to perform the operation, the computation time was drastically reduced. This was accomplished by finding expressions, which could have shared parts and extracting them from the inner loops. Furthermore, this CSD implementation takes advantage of estimation techniques to reduce the overall computation time. By using lookup tables for cosine, sine, and tangent, the total execution time was substantially reduced with only a slight reduction in accuracy.

The CSD algorithm is enhanced by altering the nondeterministic operations such as step 5 and step 8 from the listing in Section 9.4.3. In step 5 and step 8, the reiteration of the algorithm if the error condition is not met makes it impossible to reliably determine the total execution time. To gain determinism, the reiteration condition is changed such that a finite number of iterations are performed. In our case, the number of time-of-arrival and frequency reestimates (step 5) is two and a total of 15 echoes are extracted (step 8). These parameters ensure a total SNR of the regenerated signal equal to ∼10 dB. In Fig. 9.13, the echoes from the CSD algorithm are regenerated and compared with the echoes in the original signal.

The RUSSP meets timing for all critical nets in the system. The system has a total of three main clock domains: the processor clock, the ADC clock, and the SSP clock. The processor clock meets timing at 100 MHz, the ADC clock meets timing at 200 MHz, and the SSP clock meets timing at 100 MHz. The total execution time of the SSP implementation with a total of 2048 samples as measured from the processor is 16 ms. The testing methodology for the SSP execution times is based on the clock_gettime(CLOCK_MONOTONIC) function. This function returns wall clock time in a monotonic fashion such that alterations due to network time protocol or other clock tuning would have no effect on the results.

Execution times for the CSD algorithm are listed in Table 9.2. These results show a nearly linear increase in execution time with respect to number of echoes.