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by Yang Li, Yu Sasaki, Kazuo Sakiyama
Security of Block Ciphers
Cover
Title Page
Copyright
Preface
Book Organization
About the Authors
Chapter 1: Introduction to Block Ciphers
1.1 Block Cipher in Cryptology
1.2 Boolean Function and Galois Field
1.3 Linear and Nonlinear Functions in Boolean Algebra
1.4 Linear and Nonlinear Functions in Block Cipher
1.5 Advanced Encryption Standard (AES)
Further Reading
Chapter 2: Introduction to Digital Circuits
2.1 Basics of Modern Digital Circuits
2.2 Classification of Signals in Digital Circuits
2.3 Basics of Digital Logics and Functional Modules
2.4 Memory Modules
2.5 Signal Delay and Timing Analysis
2.6 Cost and Performance of Digital Circuits
Further Reading
Chapter 3: Hardware Implementations for Block Ciphers
3.1 Parallel Architecture
3.2 Loop Architecture
3.3 Pipeline Architecture
3.4 AES Hardware Implementations
Further Reading
Chapter 4: Cryptanalysis on Block Ciphers
4.1 Basics of Cryptanalysis
4.2 Differential Cryptanalysis
4.3 Impossible Differential Cryptanalysis
4.4 Integral Cryptanalysis
Further Reading
Chapter 5: Side-Channel Analysis and Fault Analysis on Block Ciphers
5.1 Introduction
5.2 Basics of Side-Channel Analysis
5.3 Side-Channel Analysis on Block Ciphers
5.4 Basics of Fault Analysis
5.5 Fault Analysis on Block Ciphers
Acknowledgment
Bibliography
Chapter 6: Advanced Fault Analysis with Techniques from Cryptanalysis
6.1 Optimized Differential Fault Analysis
6.2 Impossible Differential Fault Analysis
6.3 Integral Differential Fault Analysis
6.4 Meet-in-the-Middle Fault Analysis
Further Reading
Chapter 7: Countermeasures against Side-Channel Analysis and Fault Analysis
7.1 Logic-Level Hiding Countermeasures
7.2 Logic-Level Masking Countermeasures
7.3 Higher Level Countermeasures
Bibliography
Index
End User License Agreement
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Index
abstraction level
active
active byte
active byte with respect to the difference
addition chain
additive inverse
AddRoundKey
AES
AES-128
AES-192
AES-256
AES-comp
AES-pprm1
algorithmic noise
all property
AND
arithmetic logic unit
asynchronous-style design flow
attack complexity
attack model
balanced property
basic impossible characteristic
binary field
block
block cipher
Boolean domain
Boolean functions
Boolean masking
burst access mode
carry-select adder
ciphertext
clock
clock edge
clock jitter
clock period
clock signal
clock skew
clockwise collision
clockwise collision analysis
codebook
combinatorial logics
complementary metal-oxide-semiconductor (CMOS)
constant property
controller
correlation power analysis (CPA)
correlation-enhanced power analysis collision attack
counter mode
countermeasures
critical fault injection intensity
critical path delay
cryptology
cryptosystems
CTR mode
data
data signals
datapath
decryption oracle
delay flip flop (DFF)
design automation (DA)
determining bit
diagonal
dictionary attack
difference
difference of means (DoM)
differential characteristic
differential distribution table (DDT)
differential fault analysis (DFA)
differential power analysis (DPA)
distinguishing attack
divide-and-conquer
dynamic timing analysis (DTA)
encryption
encryption oracle
equivalent transformation of the subkey addition
evaluation function
evaluation phase
exhaustive search
extended binary field
false path
fault attack (FA)
fault model
fault sensitivity (FS)
fault sensitivity analysis (FSA)
filtering
filtering power
finite filed
finite state machine (FSM)
full adder (FA)
Galois field
gate equivalent
Hamming distance (HD) model
Hamming weight (HW) model
hiding logics
higher-order integral cryptanalysis
hold buffer
hold time
implementation attacks
impossible differential cryptanalysis
indistinguishability
input difference
INV
inverse diagonal
inversion
involution
irreducible polynomial
key lifetime
key recovery resistance
key schedule function (KSF)
key space
latency
layout
leakage model
least significant bit (LSB)
linear functions
logic synthesis
logical gates
loop architecture
loop-unrolled
mask
masked AND
masking countermeasures
masking logics
maximum distance separable
memory
message
MixColumns
mode of operation
module
most significant bit (MSB)
multiple impossible differential characteristics
multiplicative inverse
negative edge
negative logic
netlist
non-profiling analysis
nonlinear functions
normal basis
OR
oracle
output difference
parallel architecture
path delay
physical attacks
pipeline architecture
pipeline stall
plaintext
plaintext recovery resistance
polynomial basis
positive edge
positive logic
precharge phase
precharge value
profiling analysis
pseudo-Random Permutation
queries
random switching logic (RSL)
ranking test
reduced instruction set computer (RISC)
register file
register transfer level (RTL)
reset
reset signal
right pairs
ripple-carry adder
round function
round operation
S-box
scalability
selection function
sequential logics
setup time
shares
ShiftRows
side-channel attack (SCA)
side-channel information
signal toggles
signal-to-noise ratio
simple power analysis (SPA)
spatial duplication
state
static random access memory (SRAM)
static timing analysis (STA)
structure
SubBytes
subkey space
subkeys
substitution table
substitution-permutation network (SPN)
synchronous design
tamper-proofed device
temporal duplication
threshold implementation (TI)
throughput
time
traces
transfer gate (TG)
true paths
truth table
Verilog HDL
Vernam cipher
wave dynamic differential logic (WDDL)
whitening
wide trail strategy
wires
write enable signal
wrong pairs
XOR
zero-value analysis
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