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by Sanjay Ranka, Ann Gordon-Ross, Arslan Munir
Modeling and Optimization of Parallel and Distributed Embedded Systems
Cover
Title Page
Copyright
Dedication
Preface
About This Book
Highlights
Intended Audience
Organization of the Book
Acknowledgment
Part One: Overview
Chapter 1: Introduction
1.1 Embedded Systems Applications
1.2 Characteristics of Embedded Systems Applications
1.3 Embedded Systems—Hardware and Software
1.4 Modeling—An Integral Part of the Embedded Systems Design Flow
1.5 Optimization in Embedded Systems
1.6 Chapter Summary
Chapter 2: Multicore-Based EWSNs—An Example of Parallel and Distributed Embedded Systems
2.1 Multicore Embedded Wireless Sensor Network Architecture
2.2 Multicore Embedded Sensor Node Architecture
2.3 Compute-Intensive Tasks Motivating the Emergence of MCEWSNs
2.4 MCEWSN Application Domains
2.5 Multicore Embedded Sensor Nodes
2.6 Research Challenges and Future Research Directions
2.7 Chapter Summary
Part Two: Modeling
Chapter 3: An Application Metrics Estimation Model for Embedded Wireless Sensor Networks
3.1 Application Metrics Estimation Model
3.2 Experimental Results
3.3 Chapter Summary
Chapter 4: Modeling and Analysis of Fault Detection and Fault Tolerance in Embedded Wireless Sensor Networks
4.1 Related Work
4.2 Fault Diagnosis in WSNs
4.3 Distributed Fault Detection Algorithms
4.4 Fault-Tolerant Markov Models
4.5 Simulation of Distributed Fault Detection Algorithms
4.6 Numerical Results
4.7 Research Challenges and Future Research Directions
4.8 Chapter Summary
Chapter 5: A Queueing Theoretic Approach for Performance Evaluation of Low-Power Multicore-Based Parallel Embedded Systems
5.1 Related Work
5.2 Queueing Network Modeling of Multicore Embedded Architectures
5.3 Queueing Network Model Validation
5.4 Queueing Theoretic Model Insights
5.5 Chapter Summary
Part Three: Optimization
Chapter 6: Optimization Approaches in Distributed Embedded Wireless Sensor Networks
6.1 Architecture-Level Optimizations
6.2 Sensor Node Component-Level Optimizations
6.3 Data Link-Level Medium Access Control Optimizations
6.4 Network-Level Data Dissemination and Routing Protocol Optimizations
6.5 Operating System-Level Optimizations
6.6 Dynamic Optimizations
6.7 Chapter Summary
Chapter 7: High-Performance Energy-Efficient Multicore-Based Parallel Embedded Computing
7.1 Characteristics of Embedded Systems Applications
7.2 Architectural Approaches
7.3 Hardware-Assisted Middleware Approaches
7.4 Software Approaches
7.5 High-Performance Energy-Efficient Multicore Processors
7.6 Challenges and Future Research Directions
7.7 Chapter Summary
Chapter 8: An MDP-Based Dynamic Optimization Methodology for Embedded Wireless Sensor Networks
8.1 Related Work
8.2 MDP-Based Tuning Overview
8.3 Application-Specific Embedded Sensor Node Tuning Formulation as an MDP
8.4 Implementation Guidelines and Complexity
8.5 Model Extensions
8.6 Numerical Results
8.7 Chapter Summary
Chapter 9: Online Algorithms for Dynamic Optimization of Embedded Wireless Sensor Networks
9.1 Related Work
9.2 Dynamic Optimization Methodology
9.3 Experimental Results
9.4 Chapter Summary
Chapter 10: A Lightweight Dynamic Optimization Methodology for Embedded Wireless Sensor Networks
10.1 Related Work
10.2 Dynamic Optimization Methodology
10.3 Algorithms for Dynamic Optimization Methodology
10.4 Experimental Results
10.5 Chapter Summary
Chapter 11: Parallelized Benchmark-Driven Performance Evaluation of Symmetric Multiprocessors and Tiled Multicore Architectures for Parallel Embedded Systems
11.1 Related Work
11.2 Multicore Architectures and Benchmarks
11.3 Parallel Computing Device Metrics
11.4 Results
11.5 Chapter Summary
Chapter 12: High-Performance Optimizations on Tiled Manycore Embedded Systems: A Matrix Multiplication Case Study
12.1 Related Work
12.2 Tiled Manycore Architecture (TMA) Overview
12.3 Parallel Computing Metrics and Matrix Multiplication (MM) Case Study
12.4 Matrix Multiplication Algorithms' Code Snippets for Tilera's TILEPro64
12.5 Performance Optimization on a Manycore Architecture
12.6 Results
12.7 Chapter Summary
Chapter 13: Conclusions
References
Index
End User License Agreement
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End User License Agreement
Index
Action set
Adaptive processors
Advanced configuration and power interface (ACPI)
Aerial–terrestrial hybrid sensor networks
Affinity
Alias
AMD Opteron
Amdahl's law
Analog-to-digital (A/D) converters
Analog-to-digital converters (ADCs)
Application decomposition
Application metrics
Application requirements
functional
nonfunctional
Application-Specific Integrated Circuits (ASICs)
Architectural evaluation
ARM Cortex A-9 MPCore
ARM11 MPCore
ASICs
Automotive
B-MAC
Bathtub curve
Bellman's equation
Benchmarks
Blocking
Bridging
Byzantine faults
Cache associativity
Cache coherence
Cache contention
Cache miss rates
Cache partitioning
Cache pressure
Cache thrashing
Caches
Cannon's algorithm
Capacity misses
Carbon nanotubes
Cardinality
Carrier sense multiple access (CSMA)
Chip locality
Chip multiprocessors (CMPs)
Clock gating
Cloud computing
CMOS
Code encapsulation
Code generation
Code integration
Coherence
Commercial off-the-shelf (COTS)
Communication energy
Comparison-based fault detection
Compiler directives
Composable lightweight processors (CLPs)
Composable multicore architecture
Computational density
Computational density per watt
Conjoined-core CMPs
Controller area network (CAN)
Cooperative caching
Cosimulation
Cost
design cost
lifetime cost
nonrecurring engineering (NRE) cost
per-product cost
total cost
unit cost
Coverage factor
Critical section
Crossbow IRIS mote
Cyber-physical system (CPS)
Data decomposition
Data forwarding
Dataflow
Decision epochs
Decision problem
finite horizon
infinite horizon
Decision rule
Declarative routing protocol (DRP)
Design complexity
Design metrics
Design space
Design time
Deterministic
Deterministic dynamic program (DDP)
Differential equations
Directed diffusion
Discount factor
Distributed fault detection
Distributed fault detection algorithm
Distributed memory programming
Drowsy cache
Duty cycle
Dynamic constitution
Dynamic distributed cache (DDC)
Dynamic optimizations
Dynamic power coordination
Dynamic power management (DPM)
Dynamic profiler
Dynamic profiler module
Dynamic redundancy
Dynamic thermal management (DTM)
Dynamic voltage and frequency scaling (DVFS)
global
local
Dynamic voltage scaling (DVS)
Effective response time
Efficiency
Electronic control units (ECUs)
Embarrassingly Parallel benchmark
Embedded
Embedded operating system
Embedded sensor nodes
compute-intensive tasks
lifetime
Embedded systems
application characteristics
application domains
characteristics
classification
distributed
interactive
multi-unit
parallel
parallel and distributed
reactive
single-unit
transformational
design challenges
design flow
design goals
Embedded wireless sensor networks (EWSNs)
application domains
applications
cluster
lifetime
multicore
single-core
Encryption
Energy
Energy aware routing (EAR)
Expected total discounted reward
Extensible markup language (XML)
External memory bandwidth
Fairness
False alarm rate
Fast Fourier transform (FFT)
Fault detection
Fault detection accuracy
Fault detection algorithm
Fault diagnosis system
Fault latency
Fault tolerance
metrics
Feedback-based optimizations
Field-Programmable Gate Arrays (FPGAs)
Fixed heuristic policies
FlexRay
Function inlining
Functional decomposition
Gaussian Elimination
General-purpose graphics processing units (GPGPUs)
Global optimizations
GRAdient routing (GRAd)
Graphics processing unit (GPU)
Greedy algorithm
Green computing
Green500
Hardware/software codesign
Hash-for-home
Helper threading
Heterogeneous architecture
Heterogeneous CMPs
High performance
High-performance computing (HPC)
high-performance embedded computing
High-performance embedded computing (HPEC)
High-performance energy-efficient embedded computing (HPEEC)
High-performance energy-efficient parallel embedded computing (HPEPEC)
Home tile
Horizontal data communication
HW/SW partitioning
Hyper-threading
Hypervisor
ILP wall
In-network aggregation
Information fusion
Omnibus model
Instruction-level parallelism (ILP)
Integration
Intel Sandy Bridge
Interconnection networks
direct
dynamic
indirect
packet-switched
photonic
static
wireless
Internal memory bandwidth
International Standards Organization (ISO)
International Technology Roadmap for Semiconductors (ITRS)
Intrusion detection
Invalidation-based fault detection
IRIS mote
Iso-MTTF
Isoreliability
Landmarks
Last-level caches (LLC)
hybrid
Last-level caches (LLC) (
continued
)
private
shared
Latency
fault latency
Leakage current
Linear
Little's law
Load balancing
Load distribution
Local optimizations
Loop unrolling
Loop-nest optimizations
Low-energy-adaptive clustering hierarchy (LEACH)
LU decomposition
Majority voting
MANTIS
Manycore
Market window
Markov chains
Markov Decision Process (MDP)
Markov models
Markovian
Massively multicore
Matrix multiplication
MDP-based policy
Mean lifetime
Mean time to failure (MTTF)
Mean value analysis
Medium access control (MAC)
Memory striping
Memory subsystem
Metropolis-Hastings algorithm
Microcontroller
Middleware
Model
Model encapsulation
Model translation
Model-based design
Modeling
discrete event
objectives
multiple objectives
paradigms
stochastic models
MPI
Multi-processor systems-on-chip (MPSoCs)
Multi-programmed workloads
Multi-threaded workloads
Multicore
Multicore embedded architectures
Multicore embedded sensor nodes
architecture
power unit
processing unit
Multicore Embedded Wireless Sensor Networks
application domains
architecture
N-modular redundancy (NMR)
Near-Threshold computing (NTC)
Neighborhood caching
Network coding
Network-on-chip (NoC)
Node degree
Nonmonotonic cores
ns-2
Nyquist sampling theorem
Objective function
Open Systems Interconnect (OSI) model
OpenGIS Consortium
OpenMP
Operating state
Operating system (OS)
Optimal reward
Optimality equation
Optimization
dynamic
multiobjective
parallel and distributed
static
Orthogonal frequency-division multiplexing (OFDM)
Page table
PAMAS
Parallel and distributed
Parallel and distributed embedded systems
application domains
Parallelism
Parameter optimization
Parameter tuning
Pareto optimality
Peak power
Performance
Performance criterion
Performance per unit area
Performance per watt
Periods
Petri net
PicOS
Poisson distribution
Policy
stationary
Policy iteration algorithm
Power
Power gating
Power wall
PowerDial
PowerPack
PowerQUICC III
Proactive checkpoint deallocation
Processing energy
Processing units
Processor operating modes
active mode
idle mode
Processor power states
halt state
operating state
sleep state
stop-clock state
Profiling statistics
Quality
Quality of service (QoS)
Query dissemination
Queueing discipline
first-come-first-served (FCFS)
non-preemptive
preemptive
priority
processor sharing
round robin
Queueing network theory
Queueing networks
closed
jobs
multi-chain
open
product-form
response time
single-chain
throughput
utilization
Radix sort
Random walk algorithm
Raytrace
Real-time
Real-time architecture and protocol (RAP)
Real-time dynamic voltage scaling (RT-DVS)
Reliability
Reward
Reward function
Reward ratio
Run time
serial
parallel
S-MAC
Safety-critical
Satellite-based wireless sensor networks
Scalability
Scheduling
reactive
Scheduling discipline,
see
Queueing discipline
Security
Sensing energy
Sensitivity analysis
Sensor faults
noisy faults
Sensor faults (
continued
)
outlier faults
stuck-at faults
Sensor field
Sensor node
actuator unit
communication unit
location finding unit
power unit
processing unit
sensing unit
storage unit
transceiver unit
Sensor nodes,
see
Embedded sensor nodes
Sensor protocols for information via negotiation (SPIN)
Sensor web
Sensor web enablement (SWE)
Sensors
Service centers
Service-oriented architectures (SoAs)
SESC
Shared memory programming
Shared-default
Sharing processors
SHARPE
Short-circuit current
Simple object access protocol (SOAP)
Simulated annealing algorithm
Simulation
Single-caching
Single-core
Singlets
Sink node
Smart caching
Software pipelining
Software-defined radio (SDR)
Space shuttle sensor networks
Speculative synchronization
Speculative threading
Speedup
SPLASH-2
Split power planes
State
State machines
finite-state machines (FSMs)
State space
State-charts
Static optimizations
Static redundancy
Stochastic processors
Suboptimal reward
Supercomputing
Symmetric multiprocessors (SMPs)
Synchronization
Synthetic workloads
System-wide response time
Systems-on-chip (SoCs)
3D multicore architecture
T-MAC
Task scheduling
Tasks
Telemedicine
Temperature
Test-based fault detection
Thermal capacitance
Thermal resistance
Thermal-aware
Thermal-constrained
Thread migration
Thread starvation
Thread-level parallelism (TLP)
Throughput
aggregate throughput
Throughput-intensive
Tianhe-2 supercomputer
Tile locality
Tiled manycore architecture (TMA)
Tiled multicore architectures (TMAs)
Time division multiple access (TDMA)
Time-to-market
TinyOS
TLB miss
TRAMA
Transaction
Transactional memory
Transfer function
Transition cost function
Transition probability distribution
Transition probability function
Translation look-aside buffer (TLB)
Tunable parameters
Tunneling
Unified modeling language (UML)
Validation
Verification
Vertical data communication
Very Long Instruction Word (VLIW)
Water-Spatial
Weight factors
Weighted majority voting
Wide dynamic execution
Wireless multimedia sensor networks
Wireless sensor networks (WSNs)
Wireless video sensor networks
Workload characterization
Worst-case execution time (WCET)
XML
Z-MAC
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