2.1 The Search for a Better Switch

A basic element in digital logic is a switch or an inverter comprising a pair of complementary metal oxide semiconductor (CMOS) nanotransistors (Figure 2.1a) whose resistances and change in a complementary manner in response to the input voltage V_in. As V_in changes from 0 to V_DD, the resistance of the “NMOS” transistor gets smaller while the resistance of the “PMOS” transistor gets larger making the output voltage

change from V_DD to 0 as shown in Figure 2.1b so that the output represents an inverted version of the input.

For some time now it has been recognized that one of the biggest obstacles to continued downscaling is the heat dissipated [1,2]. Every time a switch changes state, the charge stored in an input or an output capacitors gets dumped thus dissipating an energy of QV_DD. If there are N_act number of active switches switching at a frequency per second, the power dissipated can be written as

(2.1)

To estimate the energy QV_DD dissipated per switch, we could use the numbers for the Intel^® Core™ i3-530 Processor taken from their Web site at http://ark.intel.com/products/46472 [3]

Since the power dissipated cannot increase too much beyond 73 W we cannot increase the number of active switches N_act or their speed of operation very much, unless we discover switches that dissipate less energy without compromising the speed. It was this recognition that prompted the Semiconductor Research Corporation (SRC) together with the National Science Foundation (NSF) to launch the Nanoelectronics Research Initiative (NRI) in 2005 with the objective of exploring the possibility of realizing a better switch based on any known physical mechanism.

Outline: In this chapter we would like to share our perspective on the question of what constitutes a “transistor-like switch,” and how we could build one based on novel physical mechanisms and assess its performance. As an example of a radically different physical mechanism, we will focus on spintronics and nanomagnetics where there has been enormous progress in the last two decades. But we will try to phrase our discussion and conclusions in general terms so that it could be easily adapted to other phenomena as well.

The new discoveries in spins and magnets are already finding use in memory devices both to Read (R) information from magnets and to Write (W) information onto magnets. Many other new phenomena are being investigated for nanoelectronic memory as described in Part Two of this book. It seems natural to ask whether these advances in W&R units for memory devices could also translate into a new class of logic devices.

In Section 2.2 we start with a very brief and oversimplified discussion of the most common switch used to implement digital logic based on CMOS transistors stressing the key property of gain that allows us to interconnect them into complex circuits without the use of external amplifiers or clocks. To harness spins and magnets for logic applications one could either integrate them onto CMOS devices that provide the gain (see for example [4]) or try to design transistor-like spin–magnet devices having gain. It is the latter option that we will explore in this chapter.

We will argue that a CMOS switch can be viewed as an integrated W–R unit, using the word “Write” in a somewhat unconventional sense. The purpose is not to provide any new insight into CMOS, but to help understand how W and R units used for memory devices can be combined to build transistor-like switches.

In Section 2.3 we discuss the standard W and R devices used for magnetic memory devices and present one way to integrate them into a single unit where the input and output are electrically isolated, but we argue that such a unit would not provide the key transistor-like property of gain. We will then show (Section 2.4) that the recently discovered giant spin Hall effect (GSHE) could be used to construct a W–R unit with gain [5].

Other possibilities for transistor-like W–R units with gain are briefly discussed in Section 2.5 including all-spin logic (ASL) [6] along with new possibilities based on newly discovered phenomena. Indeed, with the growing research interest in STT-MRAM (spin transfer torque magnetic random access memory) for both stand-alone [7] and embedded memory applications [8,9] it is likely that many more new phenomena will be discovered that could be used to construct transistor-like W–R units for logic applications.

Also we should mention that there are other independent proposals like the trans-spinor [10] and m-logic [11] that could be viewed as examples of the same W–R paradigm for logic that we are discussing here.

In Section 2.6 we end with a brief discussion of how these alternative transistor-like switches could be evaluated in terms of possible applications. A key metric is the energy–delay product and we will argue that new materials and phenomena for W and R units are needed to provide any improvement over standard CMOS switches. On the other hand the nonvolatility and reconfigurability of switches based on magnets is a novel feature that could enable a whole new class of circuits very different from those currently possible.

2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain

To understand the key characteristics of a transistor-like switch it is useful to take a brief look at a standard transistor. The simplest transistor is an NMOS or a PMOS, but we choose a CMOS switch which combines the two into a single switch that performs a logic operation, namely NOT, and has an input–output characteristic resembling those obtained from the spin switches discussed later in the chapter.

A CMOS switch is made of an NMOS and a PMOS transistor, which constitute the voltage-controlled resistors and shown in Figure 2.1a. Let us briefly describe the characteristics of an NMOS and a PMOS transistor, which can then be combined to obtain the input–output characteristics of the CMOS inverter shown in Figure 2.1b.

NMOS transistor: The resistor in Figure 2.1a is an NMOS transistor whose resistance

is reduced by a positive input voltage V_in. For small input voltages the conductance () increases exponentially with V_in (see for example [12])

Also, the resistance is not constant and ideally the current saturates for large V_out. We could describe this behavior approximately as (: constant)

(2.2)

With the current saturates perfectly, which is what we would ideally like; but with we have a characteristic looking more like real transistors, with the current showing an increase with V_out due to “drain-induced barrier lowering (DIBL).”

PMOS transistor: The other resistor () in Figure 2.1a is a PMOS transistor whose resistance is increased by a positive input voltage and we will assume that the characteristics can be described by an expression similar to Equation 2.2 but with V_in and V_out replaced by (V_DD − V_in) and (V_DD − V_out) respectively.

(2.3)

In general the NMOS and PMOS need not be symmetric with the same constant I₀ appearing in both current expressions (see Equations 2.2 and 2.3) but we will ignore such “details”, since our objective is to use the simplest model just to illustrate the main points.

Switch characteristics: The input–output characteristics of a CMOS inverter are obtained by solving Equation 2.2 for (NMOS) and Equation 2.3 for (PMOS) simultaneously. For any particular V_in, we adjust V_out numerically so as to make . This leads to the switch characteristics shown in Figure 2.2 for different values of the parameter reflecting different degrees of current saturation as discussed earlier.

Gain: A key attribute of a logic unit is its gain defined as the change in the output voltage for a given change in the input voltage

(2.4)

A logic unit should have a gain >1 in order to drive another in a circuit. It is evident from Figure 2.2 that while with large values of the inverter has a sizeable gain, the gain if . Our is a parameter introduced (see Equations 2.2 and 2.3) to account for the drain voltage dependence of the current and is usually far bigger than one for any real transistor. And so the situation with is not of any real practical significance.

We are simply using the factor to make the point that in order to have gain >1, one needs an input–output asymmetry whereby the current is controlled largely by V_in, and very little by V_out. This is evident if we rewrite the current in Equation 2.2 for large V_out

showing that the factor represents the asymmetry in the response of the current to the input and output voltages. With , this asymmetry is lost and so is the gain.

Switch as a Write–Read pair: Before we move on, let us point out that a CMOS switch could be viewed as a Write–Read (W–R) pair, if we use the word Write in a somewhat unconventional sense. This viewpoint may seem artificial and probably does not provide any insight into the operation of CMOS switches. Our reason for introducing it is as an aid to understand how Write and Read units based on spins and magnets can be combined to form switches.

We could define the state of the complementary pair in terms of the ratio of the two resistances and :

(2.5)

and create two plots: the Write (W) characteristics showing as a function of the input voltage V_in (Figure 2.3a) and the Read (R) characteristics showing the output voltage V_out as a function of the state (Figure 2.3b).

The former describes the W operation whereby the state of the CMOS inverter is set according to the input voltage V_in, while the latter describes the R operation in that the supply voltage V_DD results in an output voltage V_out depending on the state as shown symbolically in Figure 2.3c:

(2.6)

Note that we are stretching the meaning of the Write operation somewhat, since the state S does not persist once the input V_in has been removed: Unlike real memory devices, the Read operation needs to be carried out while V_in is present. Our purpose here is simply to connect the language of memory devices involving W and R units to that of CMOS so that we can understand and adapt the key property of gain that distinguishes logic units.

To integrate W and R into a transistor-like switch, an input–output asymmetry seems important: the gain of a CMOS switch seems intimately related to the fact that the input voltage V_in is far more effective in controlling the state of the switch than the output voltage V_out. This input–output asymmetry and the resulting gain make a transistor very different from reversible Hamiltonian systems often discussed in the context of nanoscale systems. To harness spins and magnets for logic devices we have two broad options:

• Integrate them onto CMOS devices which provide the gain.
• Design transistor-like spin–magnet devices that have gain.

It is the latter possibility that we are discussing in this chapter.

2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain?

Since W and R units based on magnetic tunnel junctions (MTJs) are now well-known, it seems natural to ask whether these could be combined into a transistor-like switch. Before addressing that question let us briefly summarize how an MTJ-based W and R device works.

2.3.1 Operation of an MTJ

Figure 2.4a shows a simplified MTJ structure having one layer with a reference magnet separated by a tunnelling barrier from a free layer magnet of nanometre scale thickness whose magnetization represents the stored information. Figure 2.4b shows a typical resistance versus current characteristic of an MTJ taken from Kubota et al. [13] which illustrates the basic physical phenomena underlying both the R and W operations.

At low currents the resistance can have one of two values: The smaller one () corresponds to the P configuration with the two magnetizations parallel: while the larger one corresponds to the AP configuration with the magnetizations anti-parallel: . This phenomenon allows one to Read the state of the free magnet relative to the fixed magnet by applying a small voltage .

On the other hand Figure 2.4b shows that at sufficiently high positive currents the free layer switches from a P to an AP configuration while at high negative currents it switches from an AP to a P configuration. This phenomenon allows one to Write information contained in the polarity of the current onto the magnetization of the free layer.

Figure 2.5 shows the basic characteristics of the Write and Read unit based on MTJ device and their symbolic operations. The Write unit converts the input current V_in into the magnetization of the free magnet, while the Read unit converts the information stored in into an output current V_out given by

(2.7)

where V is the supply voltage and R_L is a fixed load resistance.

2.3.2 W–R Unit with Electrical Isolation

We can now proceed to combine an MTJ Read (R) device with a Write (W) device to obtain a composite unit as shown in Figure 2.6a where the magnet from R is coupled to the magnet from W through their dipolar magnetic field as indicated by a dashed line. This allows the information to propagate from input to output: An input current I_in switches the Write magnet () which in turn switches the Read magnet () through the dipolar coupling causing a change in the output current I_out as described by Equation 2.7. At the same time the input is electrically isolated from the output allowing these units to be interconnected to form large circuits. This feature has some similarity to m-logic [11] which proposes to use exchange coupling to couple input domains to the output.

The W–R unit in Figure 2.6a can be modelled with an equivalent circuit of the form shown in Figure 2.6c which leads to the overall input–output characteristic shown in Figure 2.6d.

2.4 Giant Spin Hall Effect: A Route to Gain

The GSHE is exhibited by materials with spin–orbit coupling where the flow of charge current is accompanied by a spin current in the perpendicular direction, such that the spin current density equals the charge current density times the spin Hall angle [14]:

so that

(2.8)

The spin Hall angle is usually quite small, but recently a number of GSHE materials have been discovered which have values as high as 0.3 [15]. More interestingly, a proper choice of geometry with L t can give values of in excess of one, corresponding to a spin current that exceeds the current .

We can make use of this natural gain provided by the GSHE material, by replacing the MTJ-based Write unit in Figure 2.6a with the one shown in Figure 2.7a. To get better magnetic coupling between the Write and Read magnets it may be advisable to stack them vertically as shown in Figure 2.7b. In any case the W–R unit can be modelled with an equivalent circuit of the form shown in Figure 2.7c obtained by combining the W unit with a separate equivalent circuit for the R unit. Here is the conductance of the MTJ device and it can be related to and representing the sum and difference respectively of the parallel and anti-parallel conductances.

(2.9)

The parameters and can be related to experimentally reported quantities like the tunnelling magnetoresistance (TMR)

(2.10a)

or the polarization

(2.10b)

The input–output characteristic (Figure 2.7d) was obtained from the equivalent circuit in Figure 2.7c using the same method as described in [5] with the spin currents coupled to the Landau–Lifshitz–Gilbert (LLG) equation for the magnet pair . For a small supply voltage V (→0) the characteristic is symmetric about the origin but it shifts to the left as V is increased because the spin current I_s injected by the Read unit makes it easier to switch from +1 to −1 than to switch from −1 to +1. Indeed if the voltage were too large we would not have a useful switch. But the GSHE allows us to use a relatively small and still have gain.

The key point is that the gain from the GSHE allows the use of a relatively low voltage. A Write unit based on an ordinary spin–torque device (like the one discussed in the last section) has a spin current that is less than the charge current , corresponding to a less than one and thus requires a much larger voltage to drive the next unit.

2.4.1 Concatenability

Although the switch in Figure 2.7 exhibits gain and input–output isolation, it is not “concatenable” because the output from the Read unit is purely positive (assuming V is positive) and is not appropriate for driving the Write unit of the next stage which requires a bipolar input that takes on both positive and negative values. One can think of two broad approaches to addressing this concatenability issues:

• Design a Write unit that can be driven with purely positive voltages.
• Design a Read unit that produces a bipolar output.

One possible design, based on the second approach [5], is shown in Figure 2.8a. It requires a more complicated fabrication process since two MTJs are required: If they had the same resistance the output voltage would be zero since one is connected to +V and one to −V. But the two MTJs will never have the same resistance, since their fixed magnets are antiparallel, namely and . Depending on whether the free layer magnetization is parallel to or , one MTJ will be in its low resistance or P configuration while the other will be in its high resistance or AP configuration.

If the MTJ connected to +V is in its low resistance state then the output will be closer to +V and hence positive. If the MTJ connected to −V is in its low resistance state then the output will be closer to −V and hence negative. This dual MTJ Read unit should thus do what we want, namely convert positive or negative magnetization into a bipolar (that is, positive or negative) output voltage; and hence a bipolar output current.

For quantitative modelling we could use the equivalent circuit shown in Figure 2.8b, where and are the same as the ones used in Equation 2.9. This equivalent circuit shows that the open circuit voltage is proportional to , the component of along , giving an output current of

Figure 2.8c shows the input–output characteristic calculated using the equivalent circuit shown in Figure 2.8b and coupling the spin currents to the LLG equation for the magnet pair [5].

The gain can be estimated by noting that from Figure 2.8c

so that

(2.11)

For an approximate gain of ∼2, we need a voltage of

which only has a minor effect on the input–output characteristic (Figure 2.8c).

2.4.2 Proof of Gain and Directionality

A good test for switches with gain and directionality is the following. It should be possible to connect an odd number of such switches to form a ring oscillator (Figure 2.9). If the voltages on the Read units exceed the threshold value needed to drive the following Write unit, then each unit switches the next unit anti-parallel to itself. With an odd number of magnets, three in this case, in the loop, there is no way for all three units to be anti-parallel to each other and there is no satisfactory steady state. Unit 1 switches unit 2, which in turn switches unit 3, which goes on to switch unit 1 and the result is an oscillatory output as obtained from detailed simulation [5].

Such oscillations are well known using an odd number of CMOS switches, and should provide a good test for the properties of gain and directionality which ensure that a signal can propagate without losing strength or compounding errors.

2.5 Other Possibilities for Switches with Gain

So far we have seen two examples of switches, the standard CMOS switch and a proposed one based on spins and magnets. Both can be viewed as integrated W–R units where the input V_in or I_in writes the internal state which is then read to generate an output. As noted earlier, in the case of CMOS we are stretching the meaning of Write somewhat.

For the CMOS switch, the internal state can be defined in terms of the resistances of the NMOS and PMOS transistors, while for the spin switch represents the magnetizations of the magnet pair:

We have argued that a spin switch with gain could be implemented by combining a dual MTJ-based Read unit with a GSHE-based Write unit. However, this is by no means the only possibility. For example, the Write unit could involve a voltage-controlled multiferroic [16] as shown in Figure 2.10.

Note, however, that in order for one unit to be able to drive another, the output voltage V_out has to be large enough to switch the multiferroic, thus requiring a minimum voltage on the Read device. This voltage should not be too large, or the resulting spin current could control the magnet pair instead of the input voltage. As we have argued, a suitable degree of input–output asymmetry is needed and whether it can be achieved has to be assessed carefully for each individual proposal. Indeed many other phenomena like voltage-controlled magnetic anisotropy (VCMA) (see for example [17–19]) could potentially be used to design improved W units.

A key difference with the CMOS switch is that unlike the resistance of an NMOS or a PMOS transistor, the magnetization represents a nonvolatile state . However, it may be possible to use other mechanisms for voltage-controlled resistance based on phase transition phenomena (like the Mott transition) [20] which could provide a nonvolatile internal state like magnets.

2.5.1 All-spin Logic

Both the CMOS and the spin switch that we have described involve ordinary voltages and currents as the input and output variables and can be interconnected with ordinary wires to form circuits.

One could also envision switches based on spin voltages and spin currents as the input and output variables. An input spin current switches the Write magnet which through the dipolar coupling switches the Read magnet causing the output spin current to switch (Figure 2.11). This is similar to the all-spin logic (ASL) device [6,21] with the difference that the magnets and are electrically isolated in the present version. It was shown theoretically in [6,21] that switches with gain and directionality can be implemented with voltages as low as 10 mV.

Spin currents could in principle carry more information than ordinary currents and enable devices one step closer to quantum information processing. However, unlike ordinary charge currents, spin currents die out within a spin coherence length which can vary widely from tens of nanometers to tens of microns depending on the material and the temperature of operation. As it stands, this could still allow information transfer up to the first layer of interconnects (Metal layer 1, M1), but not for longer lengths (M2 and higher).

2.6 What do Alternative Switches Have to Offer?

We have tried to present a general perspective on how Write and Read units can be integrated into switches with gain. But what do these alternative switches have to offer relative to the standard CMOS switches that are widely used?

2.6.1 Energy–Delay Product

We started this chapter pointing out that a key roadblock on the path of miniaturization is the energy it takes to operate a switch. It is well-known that the switching energy can be reduced by going slow, so that the energy per se is not a fundamental property of a particular switch. It makes more sense to look at the energy–delay product. Consider for example [22] the charging of a capacitor through a resistance from a voltage , for which it is well known that

Combining the two relations we obtain

(2.12)

suggesting that the energy–delay product is determined simply from two quantities:

1. How much charge is being switched?
2. What is the resistance through which it is being switched?

For CMOS switches the resistance is ∼ tens of kilo-ohms, while the charge is more difficult to estimate. In our introduction we used system level numbers to estimate the quantity QV_DD as ∼3000 eV, suggesting that electrons, since V_DD volt. On the other hand if we look at the gate charge on an individual transistor it would be over an order of magnitude smaller. We believe the discrepancy is because the former estimate includes additional parasitic charges.

How does this compare with spin switches? Spin switches being all metallic structures usually have lower resistances of several tens of ohms. But the charge is ordinarily much larger, making much larger. It has been shown [23] that the minimum charge needed to switch a magnet through an ordinary spin–torque mechanism (Slonczewski spin transfer torque) is given by:

(2.13)

where N_s is the number of spins comprising the magnet which is related to the saturation magnetization through the relation

(2.14)

where μ_B is the Bohr magneton, is the volume of magnet.

Typical values of give an of about 100 spins in a volume of 1 nm³. This means that even a magnet as small as ∼10 × 10 × 1 nm has 10⁴ spins, and from the inequality in Equation 2.13, the charge is at least 20 000 electrons well in excess of the CMOS numbers.

How fundamental is the inequality in Equation 2.13? One could understand this inequality by noting that the process of switching a magnet with a stream of incident electrons can be written as

During switching the magnet spin changes by and it takes at least electrons to conserve spin.

This argument, however, assumes that there is no other source of spin and the phenomenon of GSHE allows us to bypass this argument since the strong spin–orbit coupling provides a source of spin.

An electron on its way through the GSHE material gets deflected towards the magnet, flips its spin, has its spin randomized and then is deflected again by the spin–orbit coupling towards the magnet and so on. In other words the same electron on its way through the GSHE material is incident repeatedly on the magnet and transfers many units of spin to it.

Indeed there is experimental evidence [14] that the GSHE material allows us to switch a magnet with less number of electrons than . It would seem that we could reduce the charge transferred from Equation 2.13 to

(2.15)

However, the GSHE gain depends on the length of the magnet (Equation 2.8) which also makes the magnet longer and increases N_s. The possible improvement is thus useful but not unlimited. It thus seems that magnet-based switches will not provide the low power solution we are looking for unless more suitable Write mechanisms can be identified. Moreover, the dual MTJ Read unit fails with respect to another impressive characteristic of the CMOS switch: negligible standby power. These are the issues that need increased attention in the coming years.

2.6.2 Beyond Boolean Logic

Barring a major improvement is it worth pursuing alternative switches? We believe the answer is yes because of many other nonconventional applications that may be possible.

Consider for example the reconfigurable correlator shown in Figure 2.12 which should provide an output that correlates the incoming signal with a reconfigurable reference signal stored in the of the switches that could be any string of +1's and −1's of length , being a large number.

Since the output current of each Read unit is a product of and it is determined by which are all added up to drive the output magnet. If the sequence is an exact match to , then the output voltage will be , since every will equal +1, being either (+1)*(+1) or (−1)*(−1). If matches , in , instances with mismatches, the output will be since every mismatch lowers output by 2. If we set the threshold for the output magnet to then the output will respond for all that matches the reference within a tolerance of errors. The inset in Figure 2.12 shows an example with .

This is a rather unique device which would allow us to correlate an input analog signal with a stored digital code to produce an analog output. This could be useful in mobile phones for decoding CDMA signals. Moreover it has an intriguing similarity to biological systems which correlate weak analog signals from cellular processes with a digital code stored in DNA molecules.

2.7 Perspective

But let us not go too far out on a limb with speculations. The objective here is simply to present our perspective viewing switches as Write–Read units underlining the key role played by gain and directionality in enabling large scale circuits. Hopefully this will help guide the search for new Write and Read mechanisms that could lead to fast low energy switches allowing miniaturization to continue for many more generations. But even otherwise, additional features like reconfigurability and nonvolatility could enable new functionalities currently not available. For example, the Spin Switch [5] could provide a compact implementation for neuron and synapse [24] as well as logic gates that compute with spins and magnets [25].

2.8 Summary

This chapter presents our perspective on how W and R devices in general, spintronic or otherwise, can be integrated into switches having gain and directionality like transistors. Such switches could be interconnected to build complex circuits without external amplifiers or clocks. We start with a very brief and oversimplified discussion about CMOS transistors and argue that a CMOS switch can be viewed as an integrated W–R unit having an input–output asymmetry that give it gain and directionality. Next we discuss the standard W and R units used for magnetic memory devices and present one way to integrate them into a single unit with the input electrically isolated from the output. But this integrated W–R unit would not provide the key property of gain. We then show that the recently discovered GSHE could be used to construct a W–R unit with gain and suggest other possibilities for spin switches with gain.

We end with a brief evaluation of these alternative switches in terms of possible applications. For conventional Boolean logic, at the present magnet-based switches will not provide the low power solution over standard CMOS switches unless more suitable Write mechanisms can be identified. On the other hand the nonvolatility and reconfigurability of switches based on magnets is a novel feature that could enable a new class of circuits that are very different from those currently possible.

Acknowledgments

It is a pleasure to acknowledge a number of colleagues who have contributed to this work in different ways over many years: Sayeef Salahuddin, Angik Sarkar, Srikant Srinivasan, and Deepanjan Datta. S.D. and V.Q.D. are grateful for support from the Institute for Nanoelectronics Discovery and Exploration (INDEX) and the NSF-sponsored Center for Science of Information.