17.2.1 Spin-FETs

It would be fair to say that the development of spin transistors has started from the proposal of the semiconductor electron wave analog of the electro-optic modulator proposed by Datta and Das [11], as shown in Figure 17.1. This is a three-terminal electronic device with source, drain, and gate contacts, where the source to drain current is controlled by applying a gate voltage. At first look, this device is very similar to the ordinary semiconductor transistor. However, the principle of operation of the spin-FET is completely different from the conventional transistors. The source and the drain are made of a ferromagnetic (or half-metallic) material working as polarizer and analyzer for the spin polarized current. The electrons are injected into a quasi one-dimensional semiconductor channel from the magnetic source. The initial spin polarization of the injected spins is supposed to be parallel to the polarization of the source. Then, the precession of the injected spins in the channel is controlled with a gate potential via the Rashba spin–orbit coupling effect. The precession angle θ is defined by the following [11]:

(17.1)

where m* is the effective electron mass, parameter α is the spin orbit coupling coefficient, L is the channel length, is Planck's constant. The probability that the electrons will be transmitted through the channel/drain interface depends on the relative orientation of the electron's spin with the drain magnetization and the rate of precession controlled by the gate voltage. This probability is maximized when the polarization of the incoming electrons is parallel to the magnetization of the drain (θ = 0), and the probability is at a minimum where the polarization of the incoming electrons and the drain are antiparallel (θ = π). Thus, the source–drain current oscillates as a function of the gate voltage similar to the intensity modulation in the electro-optic modulators.

Efficient spin injection into the semiconductor channel, long spin coherence length in the channel, strong Rashba coupling for spin polarization control and low scattering are the key requirements for spin-FET operation. The efficiency of the spin injection is defined by the spin polarization η: η = (N_↑ − N_↓)/(N_↑ + N_↓), where N_↑ and N_↓ is the number of the injected spin up and spin down electrons. In the ideal scenario, all of the injected electrons are of the same spin polarization η = 1. However, it is difficult to achieve high efficiency of spin injection from an ordinary ferromagnet (i.e., a ferromagnetic metal) to a semiconductor due to the conductivity (or impedance) mismatch problem [21]. This problem originates from the large difference in electrical conductivity between a ferromagnetic metal and a semiconductor. A possible solution to this problem is via the introduction of insulating tunnel barriers between the ferromagnetic and semiconductor, or making Schottky contacts with highly doped semiconductor thin layers [22]. Spin injection in the material systems with In_xGa_1−x, as have been studied widely and extensively during the past decade. Typically, experimentally detected spin polarization does not exceed a few percentage points with spin diffusion length L_s of several microns (i.e., η ∼ 5.7%, L_s ∼ 5.1 μm at 1.5 K [23]).

Being injected into a semiconductor channel, the spins of conduction electrons are subject to different relaxation mechanisms (i.e., Elliott–Yafet [24], D'yakonov–Perel' [25], Bir–Aronov–Pikus [26]) which reduce spin polarization. The most critical are the Elliott–Yafet relaxation processes due to scattering via phonons, impurities, boundaries, which are inherent in all semiconductors, and the D'yakonov–Perel' mechanism in compound semiconductors without a center of inversion symmetry, which is most prominent in III-V compound semiconductors. All the scattering mechanisms tend to equalize the number of spin up and spin down electrons in a nonmagnetic semiconductor channel. In turn, the decrease of spin polarization within the ensemble of conducting electrons reduces the On/Off ratio. For spin-FETs, it is critical to suppress the spin relaxation in the channel while keeping the maximum strength of the spin–orbit interaction. The suppression of spin relaxation can be achieved via electron confinement (i.e., making one-dimensional channel structures whose characteristic size is less than the bulk spin diffusion length) [27], or by utilizing the so-called persistent spin helix (PSH) condition [28]. In the PSH condition, spin polarization is conserved even after scattering events. This conservation is predicted to be robust against all forms of spin independent scattering, including electron–electron interaction. Recently, the PSH condition has been experimentally realized and spin life time enhancement by two orders of magnitude was observed near the exact PSH point (as shown in Figure 17.2) [29]. Though these experimental data demonstrate a significant progress towards the spin control in semiconductors, the achieved spin lifetime (10–100 ps) is still not long enough for any practical application.

Besides efficient spin injection and long spin coherence length, spin-FETs require certain channel materials with a strong spin–orbit interaction such as InGaAs, InAs, and InSb. The stronger the spin–orbit coupling α, the shorter is the channel length L at which spin polarization can be π-rotated at a given gate voltage (Eq. Eq. (17.1)). There are two kinds of spin–orbit interactions known as: (i) the Dresselhaus spin–orbit interaction [30], which originates from the lack of an inversion asymmetrical lattice structure, and (ii) the Rashba spin–orbit interaction [31], which originates from the sum of the effective electric fields at the interfaces and inside the confined structure. During the past two decades, Rashba spin–orbit interaction has been widely discussed and investigated [32]. The strength of the spin–orbit coupling is usually determined from observation of beatings in the Shubnikov–de Haas (ShdH) oscillations [33–35], the measurement of magnetoresistance in the regime of weak anti-localization in low magnetic fields [36], by the observation of Zeeman splitting energies in confined structures [37], as well as by analyzing the Raman spectrum [38], spin resonance [39] and cyclotron resonance [40]. It should be noted that the voltage-controlled spin–orbit interaction may come from the competition of two or more mechanisms (e.g., the change of the carrier concentration, or the modification of the confined electron's wave function). For example, the experimental data for In_0.75Ga_0.25As/In_0.75Al_0.25As hetero-structure show α to be almost constant near zero gate voltage and its decrease with negative Vg due to the change of the carrier concentration [33]. In contrast, the coupling constant α increases with the increase of negative gate voltage due to the modification of quantum well potential in a strained InGaAs/InP quantum wire [34]. In all cases, the maximum observed value of spin–orbit coupling strength does not exceed the tens of 10⁻¹² eVm, which implies certain limits on the gate length required for a π-phase modulation according to Equation 17.1. For example, taking α = 10 × 10⁻¹² eVm and the effective mass m* = 0.05, the minimum gate length of spin-FETs is 260 nm [41]. Theoretically, the strength of spin–orbit coupling can be enhanced by using the PSH condition where the total effective magnetic field induced both by the Rashba spin–orbit interaction and the Dresselhaus spin–orbit interaction is doubled, reducing the length by half. It is also expected that gate length can be reduced for p-type spin FETs due to the larger spin–orbit interaction value and gate controllability [42]. It is important to note, that the channel length of spin-FETs (the length required for π-phase modulation) must be shorter than the spin scattering length, which is a grand challenge for building room temperature operating prototypes.

The first working spin-FET prototype based on an InAs heterostructure was demonstrated in 2009 [43]. The prototype resembles a conventional lateral spin valve device for nonlocal measurements with two Ni₈₁Fe₁₉ electrodes on top of an InAs high-mobility channel (μ > 50 000 cm² V⁻¹ s⁻¹) of length 1.65 μm. This device shows an oscillatory conductance as a function of the applied voltage as was originally predicted by Datta and Das [11]. However, the origin of the observed spin signals is not yet clear [44–46]. Overall, efforts to implement a Datta–Das spin transistor operating at room temperature have not yet been successful. In spite of great efforts by multiple research groups, spin-FETs are far from practical realization due to the problems associated with efficient spin injection and control, and the lack of the efficient control of the spin precession by a gate voltage. It is expected that there will be further progress in improving spin injection efficiency and spin relaxation suppression. However, the low strength of the spin–orbit coupling will remain the main fundamental problem making spin-FETs inferior to conventional CMOS.

17.2.2 Spin-MOSFETs

The problems with spin precession control by applying an electric field have stimulated further search for spin transistors the operation of which does not rely on weak spin–orbit coupling. This class of spin transistors is known as spin-MOSFETs [14]. In contrast to spin-FETs, the channel of spin-MOSFET is composed of silicon with a very weak spin–orbit interaction. There is no voltage-controlled spin polarization rotation required for spin-MOSFET operation. Current modulation through the channel is achieved in a way similar to the ordinary MOSFET by changing the carrier concentration in the channel, though the concentration of spin up and spin down electrons may differ significantly due to the spin-dependent band structure. In contrast to spin-FETs with a fixed source/drain magnetic configuration, it is assumed that the magnetization of the source and drain in spin-MOSFETs can be changed during operation and provide additional control of the output current. The latter opens a variety of ways for spin-MOSFET construction by implementing different materials for the source and drain and by engineering the spin-dependent band structure. The different types of spin-MOSFETs can be classified by the structure of the source/drain and the channel (e.g., ferromagnetic semiconductor source/drain, half-metallic source and drain, and ferromagnetic semiconductor channel and a ferromagnetic or half-metallic ferromagnetic source/drain [41]). Each type of MOSFET possesses certain advantages and constrains. For instance, the use of ferromagnetic semiconductors for source and drain forming a pn junction with the Si channel can resolve the conductivity mismatch problem. At the same time, it would require a ferromagnetic semiconductor with a large spin polarization in order to obtain a large magneto-current. Besides that, there are currently no known room temperature ferromagnetic semiconductor materials. MOSFETs with ferromagnetic/half-metallic source/drain Schottky contacts can be operated as accumulation- and inversion-type channel devices. The operation of the spin MOSFETs with Schottky junctions is similar to the Schottky barrier MOSFETs [47,48], where the current modulation is via the gate-induced modification of the Schottky barrier width [41]. A more detailed description of the spin-MOSFETs operation can be found in References [14,41,49]. The calculated output characteristics of a spin-MOSFET with a Half-Metal source and drain are presented in Reference [14]. The simulation was performed under the assumptions of ballistic transport and complete spin polarization (100%) without any spin-flip scattering. Under these rather unrealistic assumptions, the spin-MOSFET shows excellent transistor behavior.

As there is no need for spin–orbit coupling in spin-MOSFET operation, the channel can be made of silicon providing a link among the new approach with the well-established technology [49]. During the past five years, there has been a significant progress towards more efficient spin injection into silicon, and, finally, spin injection and detection at room temperature has been observed [50]. Figure 17.3 shows experimental data obtained for a three-terminal device comprising a Ni₈₀Fe₂₀ contact, a high-quality amorphous Al₂O₃ tunnel barrier, and a heavily doped Si (effective carrier density of about 2 × 10¹⁹ cm⁻³) polarization [50]. The data clearly show that resistance changes with a characteristic Lorentzian shape at 300 K. These results together with several control experiments manifests room temperature spin accumulation in silicon [50]. Later on, spin injection in silicon has been confirmed by other groups [51,52]. Besides high spin injection efficiency, silicon shows a relatively long spin lifetime. In Figure 17.4, a collection of data for n-type silicon obtained via nonlocal measurements is shown. The spin lifetime at room temperature is around 0.1–1.0 ns, which is sufficient for device operation.

Though spin-MOSFETs have not yet been experimentally verified and there are many important issues to resolve, there has been important progress in increasing spin injection efficiency and observing a relative long spin lifetime. These achievements constitute an existence proof of spin-MOSFET operation at room temperature.

17.2.3 Pseudo-Spin FET

A number of problems associated with high spin injection efficiency into a semiconductor channel have stimulated a search for a hybrid device which would provide the same or similar output characteristics as a spin-MOSFET without the need for a magnetic source and drain. Such a device [referred to as a pseudo-spin-MOSFET (PS-MOSFET)] comprising an ordinary metal oxide semiconductor field-effect transistor (MOSFET) and magnetic tunnel junction has been proposed [53] and experimentally demonstrated [16]. The schematics of the PS-MOSFET are shown in Figure 17.5a. The MTJ is connected to the source of a MOSFET and feeds back its voltage drop to the gate. The degree of negative feedback depends on the resistance states of the MTJ. Thus, there are two possible values for the source–drain current at any fixed bias voltage depending on the magnetic configuration of the MTJ. The prototype PS-MOSFET was built by combining a bottom gate MOSFET and a MTJ with a full Heusler alloy (Co₂FeAl; CFA) electrode and an MgO tunnel barrier. The experimentally measured output characteristics of the fabricated PS-MOSFET are shown in Figure 17.5b [54]. The solid and dashed curves show the drain currents for parallel and anti-parallel MTJ configuration, respectively. Each curve follows depletion-type field effect transistor behavior. The drain current is higher for the parallel MTJ configuration over the entire linear and saturation regions. Experimental data in Figure 17.5c show the measured magnetoresistance as a function of V_d for the PS-MOSFET. The results show current-induced magnetization switching (CMIS) among the antiparallel (AP) and parallel (P) states. The obtained output characteristics are similar to the output characteristics simulated for the spin-MOSFET described above [41]. The successful demonstration of the PS-MOSFET has revealed an intriguing possibility of building hybrid logic devices possessing the standard transistor behavior combined with nonvolatility. It is highly expected that the development of PS-MOSFETs will be further elaborated within the next decade by benefiting from the rapid progress in MTJ improvement.

17.2.4 Graphene Spintronics

The quest for long spin lifetime has stimulated the study of spin transport in a variety of materials/nano-structures, which may be potentially used in spin-FETs. Here, we would like to refer to the most notable experimental works in this field.

Recently, a great deal of interest has been attracted to the potential utilization of graphene in spin-based devices. The most promising advantage of graphene is a long spin lifetime. According to theoretical predictions [55], spin lifetimes in a single and bilayer graphene sheets may exceed 100 ns at room temperature. Experimentally, a spin life time in the order of 1 ns at room temperature has been observed in both single- and bi-layer graphene [56]. The experimental data show a significant difference in the lifetime dependences for single-layer graphene (SLG) and bilayer graphene (BLG). In SLG, the spin lifetime varies linearly with the momentum scattering time as carrier concentration is varied, while the lifetime in BLG exhibit an inverse dependence [56]. Experimental data on room temperature spin lifetime in bilayer graphene are shown in Figure 17.6, indicating a strong lifetime decrease for samples with higher mobility. The major mechanisms of spin relaxation and the possibility of spin lifetime enhancement are currently under discussion and are currently not well understood.

The feasibility of using graphene as a tunneling barrier for MTJ [57] was also studied. The schematics of the device structure of SLG tunneling barrier and experimental data on the tunneling magnetoresistance are shown in Figure 17.7. Transport occurs by quantum tunneling perpendicular to the graphene plane and preserves a net spin polarization of the current from the contact so that the structures exhibit tunneling magnetoresistance to 425 K. These results demonstrate graphene capabilities as an effective tunnel barrier for both charge and spin-based devices. The unique electronic structure of graphene systems can be used to create pseudo-spin analogs of giant magnetoresistance and other established spintronics effects [8].

Despite the unique physical properties of graphene, its application in spin-based logic devices may be limited due to the following reasons. Low spin–orbit coupling (one of the reasons for long spin lifetime) makes graphene inefficient for spin-FETs. The absence of a bandgap makes the use of graphene channels in MOSFETs problematic because of the high Off current. The observed TMR in MTJ with graphene tunneling layer are orders of magnitude lower than for conventional MTJ with MgO. With all that, the long spin lifetime together with high mobility offered by graphene are most likely to be implemented in logic devices using spin polarized current for nanomagnets switching [58–60], to be discussed later in the text.

17.2.5 Organic Spintronics

The observation of long spin lifetime in organic semiconductors [61,62] has stimulated interest in organic materials as a possible medium to transport and control spin-polarized signals. Organic semiconductors are characterized by very low spin–orbit interaction, which, together with their chemical flexibility and relatively low production costs, makes them a promising materials system for spintronics applications [9]. So far, the most studied organic spintronic device is a spin valve comprising two ferromagnetic electrodes with an organic semiconductor layer in between. The typical thickness of the organic tunneling barrier is several nanometers or less allowing the observation of tunneling magnetoresistance. The first report on vertical injection organic spin valve was published in 2004 showing about 40% TMR at 11 K for (8-hydroxyquinoline)aluminum(III) (Alq3) [63]. Since then, many groups have confirmed similar MR from the devices with the same architecture, using both Alq3 and other OSC materials as a spacer layer (a review is given in Reference [64]). Remarkably, there are many discrepancies in reported results, which may be attributed to intrinsic material properties as well as to the interface quality and fabrication conditions [64,65].

Among the possible advantages offered by the Organic Spintronics is the possibility of building single-molecule spin-based devices. Recently, a giant magnetoresistance of 60% across a single, nonmagnetic hydrogen phthalocyanine molecule H₂Pc [66] was observed. The topographic image of the device and experimental data are shown in Figure 17.8. The H₂Pc molecules adsorbed onto two cobalt islands on the Cu(111) surface. The obtained I–V spectra clearly show the difference between parallel and anti-parallel oriented cobalt islands. This and other experimental reports [67] show significant progress in making organic spin-based devices.

Organic semiconductors are promising for spintronic application due to the long spin lifetime and the ability for efficient spin injection. At the same time, the spin diffusion length in organic semiconductors is limited to a range in the tens of nanometers due to the low mobility of organic crystals. Besides that, molecular spin-based devices are greatly affected by size variations and interface quality. Overall, it is difficult to expect that organic spintronics will provide any robust logic device in the foreseeable future which would be able to compete with CMOS.

17.2.6 Logic Circuits with Spin Transistors and Comparison with CMOS

The unique output characteristics provided by spin transistors opens new possibilities for logic circuit construction. For instance, the oscillation of the output current as a function of the gate voltage in spin-FETs is very useful for realization of specific logic functions such as XOR. At some point, the output characteristics of the device proposed by Datta and Das are similar to the ones of the single-electron transistor (SET) [68] and the logic circuits developed for SETs may be applicable for spin-FETs (e.g., one can compare the XOR circuit with SETs [69] and XOR circuit with spin-FETs [70]). Spin-MOSFETs possess great performance potential for reconfigurable logic by utilizing parallel/antiparallel configurations of source and drain [71]. There has been a growing interest in the MTJ-based nonvolatile logic circuits during the past five years [72–75]. However, the introduction of MTJ has certain side effects which limit the operating speed, reduce variability tolerance and static noise margin. Spin-MOSFETs and PS-MOSFETs may resolve some of the limitations inherent to the MTJ-based logic circuits [76]. Reconfigurable logic circuitry is another potential area of application for spin-MOSFETs and PS-MOSFETs [77]. Logic circuits consisting of spin-MOSFETs can be reprogramed by changing the magnetic configuration of source and drain of the individual transistors. The advantage of this approach is that the magnetization switching, which is a relatively slow process, is required only for reconfiguration, while the speed of operation itself is not limited by the magnetization switching time.

The most important question is whether or not spin transistors can outperform CMOS and provide a higher functional throughput? The optimistic projections predict significant improvement over the scaled CMOS for reconfigurable logic circuits (i.e., 6.8× improvements in delay, 32× active power, and 5.8× in area [71], or about 40% area–delay product improvement [77]). In all cases, the advantages are due to the nonvolatility provided by spin-MOSFETs. It is important to note that the potential improvements are directly related to the practically achievable magneto-current ratio. Figure 17.9 shows the estimates of the potential advantage of area–delay product as a function of the magneto current ratio, MC, defined as MC = (I_P − I_AP)/I_AP where I_P and I_AP are parallel and antiparallel currents, respectively. In turn, the magneto-current ratio is mainly defined by the spin scattering effects in the channel. Spin scattering generates a large amount of down-spin electrons, which increases the current in the antiparallel configuration, and eventually, degrades the MR ratio. According to the theoretical estimates [78], the MR ratio may exceed 1000 in the ideal channels without scattering, though the experimentally observed values are two orders of magnitude below. In Table 17.1, we summarize the key parameters of the different kinds of spin transistors, their most appealing characteristics, possible logic circuits, projected advantages over CMOS, and their current status of development.

In summary, spin transistors possess unique output characteristics, which are of potential for particular logic circuits. The oscillating output of the Spin-FET can be used for complex logic circuit construction (i.e., XOR gate) and for reducing the number of elements per circuit. Spin-MOSFETs and PS-FETs combine the characteristics of conventional transistors and a memory element, which can be utilized in nonvolatile and field programmable logic circuits [79,80]. The successful realization of room temperature operating PS-FET [81] brings the development of this device to the next circuit level. It is expected that the introduction of PS-FETs would reduce energy consumption though the use of relatively slow MTJ which would apply some restrictions on the circuit speed. The development of spin FETs may benefit from the advances in the development of novel materials (i.e., graphene- and organic-based spintronics). Table 17.1 summarizes the most appealing properties, key issues, and the level of development of Spin-FETs.

17.3.1 NanoMagnetic Logic

The nanomagnet logic (NML) is a variant of the edge-driven, quantum-dot cellular automata (QCA) architecture aimed to benefit from the local coupling among nano-cells. This concept was originally proposed for the electron-based cellular structure, where an elementary cell consists of four quantum dots, with two excess electrons that can tunnel between the dots tending to occupy diagonally opposite dots due to Coulomb repulsion [84]. The electronic version of QCA appeared to be impractical, like many other single-electron logic devices due to their great sensitivity to the inevitable size variations. This issue is addressed in the magnetic version of QCA (MQCA) [85], where an elementary cell is represented by a nanomagnet of a certain shape and material to exhibit a single domain behavior. When they are connected via strong exchange interaction, the spins of the nanomagnet show collective behavior, which is much more immune to structure variation than a single electron. Later, the concept of MQCA-NML has evolved in a number of works [86–90].

Logic “0” and “1” in NML are assigned to the two ground states of the nanomagnet (i.e., magnetization along or opposite to the easy-axis). Information transfer within the NML is accomplished via dipolar coupling among nearest-neighbor nanomagnets. An example of a nanomagnetic wire is shown in Figure 17.10. It is formed from a line of permalloy islands (70 × 135 nm) separated by an air gap of 25 nm. The nanomagnets are anti-ferromagnetically ordered due to the strong dipolar interaction. The operation of NML logic gates requires a clock magnetic field to modulate the barrier between magnetization states of the coupled nanomagnets. The clocking field can be applied along the hard axis of the nanomagnets as illustrated in Figure 17.10d [91]. The initial configuration is one of two collective ground states for the line of the dipole–dipole coupled magnets. Then, an external magnetic field is applied turning the magnetic moments of the nanomagnets horizontally into a neutral logic state (“null state”) against the preferred magnetic anisotropy (i.e., along the hard axes of the magnets). When the field is removed, the nanomagnets relax into the anti-ferromagnetically ordered ground state, as illustrated in Figure 17.10d. If the first magnet of the chain is influenced by an input device during relaxation, it will set the state of the whole chain via dipole–dipole interaction.

Logic functionality in the NML circuit is achieved via the specific geometric configuration of the nanomagnets. The structure of the three-input one-output majority gate is shown in Figure 17.11. The nanomagnets are arranged in two intersecting lines, such that the dipole coupling of the nanomagnets produces ferromagnetic ordering along the vertical line and antiferromagnetic ordering along the horizontal line. The nanomagnets are arranged to provide same-strength coupling to the central nanomagnet, which switches to the state corresponding to the majority of inputs. The MFM images of two possible input logic combinations are shown in Figure 17.11b–c. Such a majority gate can be reduced to a reconfigurable two-input AND/OR gate by setting the third input to a logic “0” or “1” (i.e., the MAJ gate operates as an AND gate if the third input is set to 0, and the same gate operates as an OR gate if the third input is set to 1). The NOT gate in NML comprises just two anti-ferromagnetically coupled nanomagnets, as the two magnets tend to be magnetized in the opposite directions corresponding to the 01 or 10 logic states. Figure 17.12 shows a recently reported NML fan-out (1 : 3) structure with gain provided by a magnetic clocking field. All other Boolean logic gates in NML can be built via Majority gates and Inverters.

During the past five years, there has been significant progress in NML component development and experimental demonstration [89]. A summary for the experimentally demonstrated logic gates is presented in Table 17.2.

Besides that, a great deal of efforts has focused on the NML circuits modeling and application-oriented architecture development [93,96–100]. The benchmarks on the circuit area, internal delay, energy per operation, and functional throughput are shown in Table 17.2. The estimates are shown for MAJ gate, which is the base block for NM logic. The area per circuit is shown in the characteristic lithography size (DRAM's half-pitch) F. Only internal delay is taken into consideration, and the energy per operation is shown without the energy required for the clock.

Energetically efficient clocking, magneto-electric interface, and fault tolerance are the key technological issues to be addressed. As of today, all of the reported NML prototypes were clocked by the external magnetic field produced by the electric current in the conducting contours (i.e., laboratory electromagnets). Energy losses in the magnetic field generating contours may significantly exceed the internal losses within the NML circuit. According to numerical estimates [101], the Joule heat losses in a conducting loop of resistance 10 ohms, generating a 267 Oe magnetic field for magnetization reversal in a 105 × 95 × 6 nm nanomagnet made of nickel will exceed 1.5 pJ. Thus, the energy losses of a single element may be 1000 times larger than the energy dissipated within the complete circuit (i.e., compare to the projected energy per operation in MAJ gate; Table 17.3). A similar problem arises for the magneto-electric interface. The input magnets in the NML circuits should be individually addressed to convert input electrical signal in the magnetization state (i.e., via spin transfer torque). The energy per switch in this case is also of the order of 0.5 pJ [101].

There are two major causes of errors in NML: static faults due to the manufacturing defects (e.g., magnet misalignment [102]) and dynamic faults due to the thermal noise. Both causes are most critical during the switching process when the nanomagnets relax from the “null” to the final state. This problem can be addressed by introducing nanomagnets with a magnetocrystalline biaxial anisotropy, which can be used to introduce a local energy minimum and to increase hard axis stability [103]. Fault tolerance can also be enhanced via adiabatic switching and/or field gradients [89]. The feasibility of building error-tolerant NML circuits is currently debated [89,101].

Overall, NML is one of the most explored approaches in the area of Spintronic Logic. NML logic gates (i.e., Inverters, Buffer lines, MAJ gates) have been experimentally demonstrated at room temperature [87]. It is expected that NML will continue to advance and more prototypes (i.e., two-bit Adder circuit) will be experimentally demonstrated within the next two years. Scalability and low power consumption are the main appealing properties of the NML approach, promising an overall power-performance advantage over the scaled CMOS. NML logic circuits might be employed for Boolean (systolic arrays) as well as for nonBoolean information processing [98,104]. The main technological issues of NML are associated with the circuit reliability and defect tolerance [105]. Thermal noise and fabrication-related imperfections can cause errors in signal transmission and logic function in NML circuits [106]. A more detailed description and analysis of NML logic will be given in Chapter 22.

17.3.2 All Spin Logic

The communication between the input and output nanomagnets can be accomplished via spin polarized currents [58]. Within this approach, nanomagnets share a common spin-coherent channel. Some of the magnets have fixed magnetization and some of them can be switched due to the spin torque produced by the spin polarized current. This approach has been further evolved in the All Spin Logic (ASL) [59]. The basic concept of switching in ASL is illustrated in Figure 17.13. There are shown two elementary magnetic cells connected via a spin-coherent channel. The cell comprises from the top to the bottom the following: metallic contact; magnetic free layer, and a tunneling layer. It is assumed that the free layer has two thermally stable magnetic configurations and can be used as a built-in memory. The cells communicate via a spin-polarized current propagating through the channel. In order to switch the cell on the right side, the cell on the left side generates a spin polarized current which flows through the channel and provides a torque on the magnetization of the output cell. There are two possible switching scenarios, as described in [59]: (i) the magnetization of the free layer of the output cell is switched if the strength of the torque exceeds certain threshold value; (ii) a supply voltage is applied to the output cell driving the magnetization of the free layer of the output cell in a metastable state. Then, the torque provided by the current defines the relaxation direction towards one of the two stable states. The use of voltage-assisted switching has certain advantages and allows for significant reduction of the spin polarized current required for switching, as the strength of the torque has to be just above the noise level in order to define the final state. There are several possible layouts for constructing cascadable ASL gates [59]. Shown in Figure 17.14, is an example of a circuit comprising two gates (four cells per gate). Each of the gates can function as a NAND/NOR or AND/OR gate. A variety of Boolean logic gates can be constructed by implementing different channel configurations and clocking schemes. The channel in ASL has to provide maximum spin coherence and can be made of semiconductors as well as metallic materials. Graphene may be the best candidate for application in ASL as it combines long coherence length with high mobility. Magnetologic gates with a hybrid graphene/ferromagnet material system have been recently proposed [60].

The ASL approach is free of constraints inherent to the schemes using dipole–dipole coupling and allows for much higher defect tolerance as the variations in the position of the elementary cells is of minor importance. It is also scalable since shorter distances between the input/output cells require less spin polarized currents for switching. The use of voltage-assisted switching may be an efficient amplification mechanism, taking energy from the conventional voltage supply. According to the theoretical estimates [107], ASL can potentially reduce the switching energy–delay product. The major issues of this scheme are associated with the electrical isolation among the electrically biased cells and the realization of the spin-coherent channel. It is desired to have spin-polarized currents flowing only between the input and the output cells though the potential difference may arise among the output cells or the cells of the different stages. No working ASL circuits have been prototyped to date.

17.3.3 Spin Wave Devices

Spin Wave Devices (SWD) are a type of magnetic logic exploiting collective spin oscillation (spin waves) for information transmission and processing [108,109]. The schematics of the SWD logic gate are shown in Figure 17.15. The circuit consists of: (i) magneto-electric cells, (ii) magnetic waveguides – spin wave buses, and (iii) a phase shifter. The magneto-electric cell (ME cell) is the element used to convert voltage pulses into the spin waves as well as to read out the voltages produced by the spin waves. The operation of the ME cell is based on the effect of magneto-electric coupling in multiferroics enabling magnetization control by applying an electric field and vice versa [82]. The principle of operation is the following. SWD receives initial information in the form of voltage pulses (e.g., +10 mV corresponds to logic state 0, and −10 mV corresponds to logic state 1). The polarity of the applied voltage defines the initial phase of the spin wave signal (e.g., positive voltage results in clockwise magnetization rotation and negative voltage results in counter clockwise magnetization rotation). Thus, the input information is translated into the phase of the excited wave (e.g., initial phase 0 corresponds to logic state 0, and initial phase π corresponds to logic state 1). Then, the waves propagate through the magnetic waveguides and interfere at the point of waveguide junction. For any junction with an odd number of interfering waves, there is a transmitted wave with a nonzero amplitude. The phase of the wave passing through the junction always corresponds to the majority of the phases of the interfering waves (e.g., the transmitted wave will have phase 0, if there are two or three waves with initial phase 0; otherwise, the wave will have a π-phase). As the transmitted wave passes the phase shifter, it accumulates an additional π-phase shift (e.g., phase 0 → π, and phase π → 0). Finally, the spin wave signal reaches the output ME cell. The output cell has two stable magnetization states. At the moment of spin wave arrival, the output cell is in the metastable state (magnetization is along the hard axis perpendicular to the two stable states). The phase of the incoming spin wave defines the direction of the magnetization relaxation in the output cell [82,109]. The process of magnetization change in the output ME cell is associated with the change of electrical polarization in the multiferroic material and recognized by the induced voltage across the ME cell (e.g., +10 mV corresponds to logic state 0, and −10 mV corresponds to logic state 1).

The operation of the SWDs is based on the spin wave interference, which provides the mechanism for phase-based data processing. During the past five years, three- and four-terminal SWDs exploiting spin wave interference have been experimentally demonstrated [110,111]. Figure 17.16a shows the top view of the four-terminal SWD. The sample consists of a silicon substrate, a 20 nm layer of Ni₈₁Fe₁₉, a 300 nm layer of silicon dioxide, and a set of five conducting wires on top. The distance between the wires is 2 μm. Three of the five wires are used as input ports, and the two other wires are connected in a loop to detect the inductive voltage produced by the spin wave interference. The direction of the current in the wires defines the phase difference between the excited spin waves (i.e., the waves have the same initial phase if the direction of the current is the same direction, and there is a π-phase difference if the current flows in the opposite direction). The plot in Figure 17.16b shows the output inductive voltage for different combinations of spin wave phases. The blue and red curves correspond to the case when all three waves are excited in phase, and the black and green curves correspond to the case when one of the waves has a π-phase difference with the others. The experimental data show the change of the phase of the output voltage as a function of the input combination (i.e., 000, π00, 0π0, 00π corresponds to the output phase 0, and πππ, 0ππ, π0π, ππ0 results in the change of the output phase voltage of π). This logic device operates as MAJ gate in the phase space. The data are taken at 95 Oe bias magnetic field (perpendicular to the spin wave propagation), 3 GHz frequency, and at room temperature.

The use of electric current wires for spin wave excitation appeared to be energetically inefficient (i.e., >pJ per spin wave), as only a small amount of energy is transferred into the spin wave. It would be much more efficient to utilize multiferroics for energy conversion between the electric and magnetic domains [112]. Recently, spin wave excitation and detection by synthetic multiferroic elements was experimentally demonstrated [113]. The schematics of the experiment and experimental data are shown in Figure 17.17. Two synthetic multiferroic elements were used to excite and detect a spin wave propagating in the permalloy waveguide (the distance among the excitation and the detection elements is 40 μm). The multiferroic element comprises a layer of piezoelectric (PZT) and a magnetostrictive material (Ni). An electric field applied across the piezoelectric produces stress, which, in turn, affects the magnetization of the magnetostrictive material. Thus, the applying of AC voltage to the multiferroic element results in magnetization oscillation (a spin wave). Vice versa, a change of magnetization in the magnetostrictive layer results in a voltage signal due to the produced stress. The experimental data in Figure 17.17b show the collection of data obtained at different operational frequencies and bias magnetic field. The utilization of multiferroics has resulted in the energy reduction to about 10 fJ per wave [113]. The major characteristics of the experimentally demonstrated SWD prototypes are summarized in Table 17.4.

The expected advantages of SWD technology include: (i) the ability to utilize phase in addition to amplitude for building logic devices with a smaller number of elements than required for transistor-based approach [82], and (ii) parallel data processing on multiple frequencies at the same device structure by exploiting each frequency as a distinct information channel [115]. Wave-based magnonic logic devices may complement CMOS in special task data processing (i.e., image processing), by exploiting wave interference for functional throughput enhancement. The major issues of SDW approach include the problems with energetically efficient spin wave excitation and detection, fast attenuation time (∼1 ns at RT), and spin wave dispersion [102]. All of the demonstrated prototypes utilize spin waves of micrometer scale wavelength, which makes them immune with respect to the waveguide structure imperfections. It is not clear if scaling to the deep sub-micrometer range would significantly affect the signal to noise ratio as well as the speed of propagation. At some point, the success of the SWD approach depends on the ability to detect and amplify spin waves (i.e., by multiferroic elements or spin torque oscillators), which can enhance SWD noise immunity.

17.3.4 Hybrid Spintronics and Straintronics Devices

A new approach to magnetization control via applied stress was recently proposed and became known as Hybrid Spintronics and Straintronics [116,117]. The essence of this approach is in the use of two-phase composite multiferroics comprising piezoelectric and magnetostrictive materials, where an electric field applied across the piezoelectric produces stress, which, in turn, affects the magnetization of the magnetoelastic material. Although work in this area can be traced back to the 1970s [118], composite multiferroics have been in a shadow of single-phase multiferroics (i.e., BiFeO₃ and its derivatives [119]) for a long time. The recent resurgence of interest in composite multiferroics is due to the technological flexibility, where each phase (piezoelectric or magnetostrictive) may be independently optimized for room temperature performance. More importantly, the strength of the electro-magnetic coupling in the two-phase systems can significantly exceed the limits of the single-phase counterparts [120]. During the past two years, there have been several experimental works showing magnetization rotation in two-phase multiferroics as a function of the applied voltage [117,121]. For instance, a reversible and permanent magnetic anisotropy reorientation was reported in a magnetoelectric polycrystalline Ni thin film and (011)-oriented [Pb(Mg_1/3Nb_2/3)O₃]_(1−x)−[PbTiO₃]_x heterostructure [117]. An important feature of the magneto-electric coupling is that the changes in magnetization states are stable without the application of an electric field and can be reversibly switched by an electric field near a critical value (i.e., 0.6 MV/m for Ni/PMN-PT). Such a relatively weak electric field promises the ultra-low energy consumption required for magnetization switching [122]. The estimates of power dissipation in a two-phase multiferroic material are shown in Figure 17.18 [116]. The dissipated energy is calculated as follows:

where C is the capacitance of the multiferroic element, which is defined by the dielectric properties of the piezoelectric layer, and the dimensions of the element, V is the voltage needed to generate the stress sufficient for magnetization reversal, and E_d is the energy dissipated in the nanomagnet due to Gilbert damping [116]. The voltage required for magnetization switching can be found by solving the Landau–Lifshitz–Gilbert (LLG) equation for particular materials or estimated, based on experimental data. The estimates predict values as low as tens of kT energy dissipated per switch at a nanosecond switching time. For example, the total energy dissipated is 45 kT for a delay of 100 ns and 70 kT for a delay of 10 ns. It is important to note that, according to the theoretical estimates [116], the energy dissipation increases sub-linearly with the switching speed. For example, in order to increase the switching speed by a factor of 10, the dissipation needs to increase by a factor of 1.6.

The ability to control magnetization by an electric field presents great potential for application of two-phase multiferroics in magnetic logic devices. Specifically, these elements may resolve the shortcoming associated with input–output isolation in the dipole-coupled NML circuits described in the previous section. In contrast to the global magnetic field provided by the electric current carrying wires, a multiferroic element allows for more local magnetization control. At the same time, stress-mediated electro-magnetic coupling eliminates the problem of the stray field. Another potential benefit of multiferroics is the possibility of building multi-state logic circuits by exploiting the biaxial magnetocrystalline anisotropy of the magnetoelastic material. An example of the four-state universal logic gate (NOR) using a linear array of three dipole-coupled magnetostrictive-piezoelectric multiferroic nanomagnets is described in Reference [123]. Similar ideas for using electric field-controlled nanomagnets can be implemented in other types of logic circuits (i.e., developed for NML).

It is expected that the development of multiferroic elements exploiting stress for magnetization switching will be intensively studied within the next two years and the estimates on ultra-low power dissipation will be experimentally validated. Another important question to be answered is whether or not stress-based multiferroic devices are capable of fast (GHz frequency range) switching.

17.3.5 Spin Torque-based Devices

The discovery of the spin torque effect [124] has resulted in the development of novel mechanism for magnetization switching, which has been successfully implemented in magnetic memory [125]. Spin torque devices (STD) comprise a stack of metallic ferromagnetic layers separated by the tunneling barrier. Passing electric current across the structure produces a spin torque affecting the magnetization of the ferromagnetic layers. Spin torque may result in the oscillation of magnetization (spin wave generation) or complete magnetization reversal of the one of the magnetic layer (i.e., the free layer) when the current density exceeds a certain threshold value. The fabrication technology is fully compatible with CMOS, which makes the spin torque device (STD) a promising candidate for implementation in logic circuits. There are two major approaches to spin torque-based devices: (i) digital devices, where logic states 0 and 1 are encoded into the magnetic state of the free layer(s) [83,126]; (ii) analog devices where logic state is associated with the frequency of the magnetic oscillation.

The schematics of the digital spin torque majority gate (STMG) are shown in Figure 17.19 [83]. There are four STD nanopillars connected via the common ferromagnetic layer. Three of the nanopillars (A, B, C in Figure 17.19) are used as the input gates, and the fourth nanopilalr (Out) is the output gate. Each of the input nanopillars and the output nanopillar has separate fixed layers which are pinned by the antiferromagnetic layers on top of them. Logic input is defined by the polarity of the voltage applied to the input gates (i.e., positive voltage corresponds to logic 1, and negative voltage corresponds to logic 0. The polarity of the applied voltage determines the direction of the spin torque affecting the magnetization of the common free ferromagnetic layer below the nanopillars. Thus, positive voltage forces the magnetization in the free layer to align parallel with the magnetization of the fixed layer, and negative voltage forces the magnetization to align in the opposite direction. As a result of the interplay between the three torque forces, the magnetization of the free layer changes according to the majority of the inputs. The numerical simulations in Figure 17.19 illustrate the process of magnetization change (domain wall motion) in the common layer. The input voltages are applied until the domain wall reaches the output cell. Once the direction of magnetization in the free layer reaches its steady-state configuration, the input voltages are turned off and the results of computation is stored in the magnetization state of the common layer. The read-out is accomplished by sensing the resistance across the output nanopillar (i.e., high resistance corresponds to logic 1 and low resistance corresponds to logic 0).

This approach looks very feasible from the technological point of view, as the material structure of the nanopillars in MAJ gate is similar to that in a typical magnetic tunnel junction [127]. The only technological challenge is associated with the electrical isolation of the STDs to prevent unnecessary electric currents, which can be possible resolved by utilizing a nonconducting ferromagnetic layer. The projected potential advantages over the CMOS are in are smaller area, low power, nonvolatility, reconfigurability, and radiation hardness [83]. The estimates on a full adder circuit built of STDs from Ref. [128] are shown in Table 17.5.

There are a few factors beneficial for STDs circuit. It has a higher density than CMOS, because 28 transistors are replaced by three majority gates. The STDs circuit has lower active power and zero standby power. At the same time, the use of domain wall motion for STD coupling would limit the switching speed and the switching energy. The efficiency of the STD devices is mainly defined by the magnitude of the electric current required for magnetization switching. So far, the best experimental results show about MA/cm² critical current density (CoFeB free layer [129]). On the one hand, the critical switching current is proportional to the device area and can be scaled down for nanometer size structures. On the other hand, there are certain limits on the size of the free layer to be switched (i.e., due to the thermal stability requirements), which would further restrict the minimum switching current. All these fundamental issues could narrow the potential applications of the domain wall-coupled STDs.

Another approach to STD coupling is via spin waves [130]. This approach is based on the property of nanometer scale spin torque devices generate spin waves in response to a d.c. electrical current [131,132]. Electric current passing through a spin torque nano-oscillator (STNO) generates spin transfer torque and induces auto-oscillatory precession of the magnetic moment of the spin valve free layer. The frequency of the precessing magnetization is tunable by the applied dc voltage due to the strong nonlinearity of the STNO. In case of two or more STNOs sharing a common free layer, the oscillations can be frequency and phase locked via the spin wave exchange [130,133]. Figure 17.20 shows the schematics of the devices with two STNOs (marked as A and B) and the experimental data illustrating the coupling. Figure 17.20c–d plots the evolution of the combined spectrum from both STNOs as current through contact B increases. The phase-locked state is characterized by a narrowing of the signal linewidth (Figure 17.20d) as the current exceed the threshold value. This phenomenon gives rise to the proposal on the logic devices based on coupled STNOs [134]. A majority logic gate based on phase locking of STNOs consists of a common free-layer metallic ferromagnetic nanowire on a metallic nonmagnetic bottom lead with several GMR or TMR junctions patterned on top of the free layer as shown in Figure 17.21. One of these junctions can serve as the gate output while the rest of the junctions are the gate inputs. All inputs are dc current-biased at a current level above the critical current for magnetization self-oscillations. To each input, signals of two frequencies f1 and f2 can be applied. Due to injection locking and spin wave interaction in the common free layer, the entire free layer precesses at either f1 or f2, depending on the input signal frequency applied to the majority of the inputs. Therefore, the output frequency of this logic gate is determined by the frequency applied to the majority of the input gates, and the device operates as a majority logic gate with the signal frequency as the state variable [135].

The unique properties of STDs are of great promise for future implementation. Being compatible with CMOS, STDs may serve as complementary logic units for general and special task data processing. The main challenge for the STD approach is to reduce the current required for switching and minimize active power consumption.

17.3.6 Current Status and Perspectives of Magnetic Logic Devices

In summary, magnetic devices provide an alternative approach to logic circuit construction by exploiting intrinsic nonlinearity of magnetic materials. In contrast to Spin-FETs, most magnetic devices do not require high-efficiency spin injection, and a number of room temperature operating prototypes has been demonstrated. Nonvolatility is the main advantage inherent to all schemes, which may potentially eliminate static power consumption. The future success of magnetic logic is mainly related to finding an energetically efficient mechanism for local magnetization control. Development and utilization of multiferroic materials is one of the promising approaches able to scale down energy per magnetization reversal to the atto Joule level. At the same time, the use of nanomagnets for information storage implies certain limits on the operational speed, which is restricted by the time required for magnetization reversal. It is unlikely that magnetic devices will be ever able to compete with CMOS in speed. Nevertheless, magnetic logic circuits can provide higher functional throughput or perform the same data processing tasks with lower energy consumption than CMOS by implementing complex logic functions and/or reconfigurability. For example, NML and ASL circuits are especially suited for adder and multiplier circuits as a part of arithmetic logic units (ALU). SWDs are most efficient for MAJ gate construction by exploiting wave interference and may be also promising for parallel data processing. STDs offer a variety of possible applications including nonvolatile digital circuits (i.e., MAJ gates) and analog dynamical phase-locking system for neuromorphic-type architectures. In Table 17.6, we summarize the most appealing properties, key issues, and the level of development of magnetic logic devices.