1.1 The dawn of the many-core era
1.2 Communication-centric cross-layer optimizations
1.3 A baseline design space exploration of NoCs
Part II: Logic implementations
Chapter 2: A single-cycle router with wing channels
Chapter 3: Dynamic virtual channel routers with congestion awareness
3.2 DVC with congestion awareness
3.3 Multiple-port shared buffer with congestion awareness
3.4 DVC router microarchitecture
3.5 HiBB router microarchitecture
Chapter 4: Virtual bus structure-based network-on-chip topologies
Part III: Routing and flow control
Chapter 5: Routing algorithms for workload consolidation
5.4 Destination-based adaptive routing
Chapter 6: Flow control for fully adaptive routing
6.4 Flow control and routing designs
6.5 Evaluation on synthetic traffic
6.6 Evaluation of parsec workloads
6.7 Detailed analysis of flow control
Appendix: logical equivalence of Alg and Alg + WPF
Chapter 7: Deadlock-free flow control for torus networks-on-chip
7.2 Limitations of existing designs
7.6 Evaluation on 1D tori (rings)
7.9 Discussion and related work
Part IV: Programming paradigms
Chapter 8: Supporting cache-coherent collective communications
8.2 Message combination framework
8.4 Router pipeline and microarchitecture
Chapter 9: Network-on-chip customizations for message passing interface primitives
9.4 Communication customization architectures
Chapter 10: Message passing interface communication protocol optimizations
10.4 Adaptive communication mechanisms