Index
Note: Page numbers followed by f indicate figures and t indicate tables.
A
Acknowledgment messages (ACKs)
20
Adaptive communication mechanism (ADCM)
323
baseline communication architecture
333,
334f
B
Balanced, adaptive multicast (BAM) routing
20
multicast routing algorithm
268
obligatory output ports
268
Bubble flow control (BFC)
21
Bufferless flow control
20–21
C
Cache-coherent collective communications
20
baseline configuration and variations
271,
272t
message combination mechanism
284
NoC multicast routing algorithm
284–285
overall network performance
273,
273f
Collective communication
294
Communication-centric cross-layer optimization method
interconnection layer
5–6
logic implementation layer
parallel programming paradigm layer
Communication customization architectures control messages
295
message buffer management
296
MU architecture (see MPI unit (MU))
Content-addressable memory (CAM)
264
D
Deadlock avoidance theory, 358
179
Deadlock-free flow control
Destination-based adaptive routing (DBAR)
19
Destination-based selection strategy (DBSS), 359
CMesh evaluation (see CMesh topology)
Deterministic routing algorithm
10,
11f
Dimensional order routing (DOR)
10,
11f,
269
Duato's theory, 358, 359
18,
19
Dynamically allocated multiqueue (DAMQ) buffer
22–23,
209
Dynamic virtual channel (DVC) routers
congestion metric aggregation module
88,
89f
flow control module
89,
90f
head-of-line (HoL) blocking
79
VC allocation module
90–91
Dynamic voltage and frequency scaling (DVFS)
32
E
Element interconnect bus (EIB)
27,
27f
Escape virtual channels (EVCs)
connected routing function
187
deadlock-free algorithm
187
direct and indirect dependency
187
extended VC dependency graph
187
F
Flit bubble flow control (FBFC)
22
virtual channels techniques
13,
13t
Fully adaptive routing algorithms
physical/virtual networks
176,
177t
H
Hierarchical bit-line buffer (HiBB)
hotspot and transpose patterns
101
nonuniform VC configuration
83,
84f
VC allocation and output port allocation
92–95,
93f,
94f
VC control module
92,
93f
I
Intel's 80-core Teraflops chip
290
K
L
Localized bubble scheme (LBS)
221,
221f
M
computation/communication-centric method
6–7
NoC interconnection layer
7–8,
7f
Message combination table (MCT)
multicast packet transmission
264,
265f
Message passing interface (MPI), 358
20
buffered communication
294
Cell Broadband Engine processor
292
hardware estimation, 350–351, 351
t
NAS Parallel Benchmarks (NPB 2.4) suite
344
sensitivity analysis, 350, 351
f, 352
f
synchronous communication
294
SystemC-based cycle-level NoC simulator
307
Microarchitecture designs
SIG manager and controller
66,
67f
virtual channel arbitration components
64–65,
65f
local processor core and NI
297,
297f
send and receive operations
298–299
N
Neighbors-on-path (NoP) design
19
Nondeterministic routing
10
O
Oblivious routing algorithm
10
On-chip interconnection networks
On-chip network (OCN)
29–30
Operand network (OPN)
28–29
P
Parallel programming paradigms ,
40–41
methodology and configuration
199,
201t
Port-selection-first (PSF) algorithms
Power processing element (PPE)
27
Prevention flow control
21
R
ADCM prediction accuracy, 350
f 348–349
Receiving buffer credit (RBC) table
337
Receiving policy unit (RPU)
337
Recursive partitioning multicast (RPM)
20,
262
Regional congestion awareness (RCA)
congestion propagation network
149–150
channel dispenser unit
57
cache-coherent collective communications
270,
271f
critical path delay and area
190,
190t
four-stage pipeline
15,
15f
structure, virtual channel
13,
14f
switch allocation and traversal
188–189
two-stage pipeline
15f,
16
virtual channel allocator
14
adaptive routing algorithm
144,
144f
deterministic routing
10,
11f
nondeterministic routing
10
synthetic traffic patterns
156
S
Shared memory programming, 358
Single-cycle router, wing channels, 357–358
area and power consumption
73f,
74
simulation infrastructures
66
zero-load latency
68f,
69
Sony/Toshiba/IBM cell processor
27–28,
27f
Store-and-forward (SAF) flow control
12,
12f,
13t
Synchronization signals, 359–360
Synthetic traffic patterns
baseline configuration and variations
195t,
196
T
Transaction-based bus communication
Tree-based multicast routing
20
U
Unicast routing designs
18–19
V
Valiant routing algorithm
9–10
Virtual bus on-chip network (VBON)
multicast communications
110
starvation and deadlock avoidance
124
Virtual channel arbitration components
64–65,
65f
Virtual cut-through (VCT) flow control
11,
12f,
13t
W
Whole packet forwarding (WPF), 358
19,
182–185