Home Page Icon
Home Page
Table of Contents for
Part III: Routing and flow control
Close
Part III: Routing and flow control
by Zhiying Wang, Wei Shi, Mingche Lai, Libo Huang, Sheng Ma
Networks-on-Chip
Title page
Copyright
Preface
About the Editor-in-Chief and Authors
Editor-in-Chief
Authors
Part I: Prologue
Part II: Logic implementations
Introduction
Chapter 2: A single-cycle router with wing channels
Abstract
2.1 Introduction
2.2 The router architecture
2.3 Microarchitecture designs
2.4 Experimental results
2.5 Chapter summary
Chapter 3: Dynamic virtual channel routers with congestion awareness
Abstract
3.1 Introduction
3.2 DVC with congestion awareness
3.3 Multiple-port shared buffer with congestion awareness
3.4 DVC router microarchitecture
3.5 HiBB router microarchitecture
3.6 Evaluation
3.7 Chapter Summary
Chapter 4: Virtual bus structure-based network-on-chip topologies
Abstract
4.1 Introduction
4.2 Background
4.3 Motivation
4.4 The VBON
4.5 Evaluation
4.6 Chapter summary
Part III: Routing and flow control
Introduction
Chapter 6: Flow control for fully adaptive routing
Abstract
6.1 Introduction
6.2 Background
6.3 Motivation
6.4 Flow control and routing designs
6.5 Evaluation on synthetic traffic
6.6 Evaluation of parsec workloads
6.7 Detailed analysis of flow control
6.8 Further discussion
6.9 Chapter summary
Appendix: logical equivalence of Alg and Alg + WPF
Chapter 7: Deadlock-free flow control for torus networks-on-chip
Abstract
7.1 Introduction
7.2 Limitations of existing designs
7.3 Flit bubble flow control
7.4 Router microarchitecture
7.5 Methodology
7.6 Evaluation on 1D tori (rings)
7.7 Evaluation on 2D tori
7.8 Overheads: power and area
7.9 Discussion and related work
7.10 Chapter summary
Part IV: Programming paradigms
Introduction
Chapter 8: Supporting cache-coherent collective communications
Abstract
8.1 Introduction
8.2 Message combination framework
8.3 Bam routing
8.4 Router pipeline and microarchitecture
8.5 Evaluation
8.6 Power analysis
8.7 Related work
8.8 Chapter summary
Chapter 9: Network-on-chip customizations for message passing interface primitives
Abstract
9.1 Introduction
9.2 Background
9.3 Motivation
9.4 Communication customization architectures
9.5 Evaluation
9.6 Chapter summary
Chapter 10: Message passing interface communication protocol optimizations
Abstract
10.1 Introduction
10.2 Background
10.3 Motivation
10.4 Adaptive communication mechanisms
10.5 Evaluation
10.6 Chapter summary
Part V: Epilogue
Chapter 11: Conclusions and future work
Abstract
11.1 Conclusions
11.2 Future work
Search in book...
Toggle Font Controls
Playlists
Add To
Create new playlist
Name your new playlist
Playlist description (optional)
Cancel
Create playlist
Sign In
Email address
Password
Forgot Password?
Create account
Login
or
Continue with Facebook
Continue with Google
Sign Up
Full Name
Email address
Confirm Email Address
Password
Login
Create account
or
Continue with Facebook
Continue with Google
Prev
Previous Chapter
Chapter 4: Virtual bus structure-based network-on-chip topologies
Next
Next Chapter
Introduction
Part III
Routing and flow control
Add Highlight
No Comment
..................Content has been hidden....................
You can't read the all page of ebook, please click
here
login for view all page.
Day Mode
Cloud Mode
Night Mode
Reset