,

11

Bias Generator Circuits

Neuromorphic chips often require a wide range of biasing currents which are independent of process and supply voltage, and which change with temperature appropriately to result in constant transconductance. These currents can span many decades, down to less than the transistor ‘off-current’. This chapter describes how to design wide-dynamic range configurable bias current references. The output of each current reference is a gate voltage which produces a desired current. Bias currents are generated by a bootstrapped-mirror ‘master bias’ current reference that generates a master current, which is successively divided by a digitally-controlled current splitter to generate the desired reference currents. Nonidealities such as power supply sensitivity, matching, stability, and headroom are also discussed. Open source design kits simplify the job of including these circuits on new designs.

11.1   Introduction

Analog and mixed-signal neuromorphic and bio-inspired chips such as the sensors described in Chapters 3 and 4 and some of the multichip systems described in Chapter 13 require a number of adjustable voltage and current references. Reference voltages are used, for example, as inputs to differential amplifiers used in feedback transimpedance configuration, as thresholds for voltage comparators, and as inputs to tilted resistor ladders. Reference voltages typically do not need be precise and on many designs it does not matter much if they vary somewhat with process, although they should not be sensitive to power supply noise. Current references are used everywhere, for example, for biasing amplifiers, for setting time constants of various circuits, and for powering loads for static logic.

Chips will often have large numbers of identical circuits (e.g., pixels, column amplifiers, or cells) that require identical biases. The required currents can extend over many decades. For instance, consider a chip with circuits that span timescales from nanoseconds to milliseconds which uses subthreshold g_m − C filters with 1pF capacitors. The rise time T of simple g_m − C circuits scales as C/g_m. The transconductance g_m of a transistor in subthreshold operation scales as I/U_T, where I is the bias current and U_T is the thermal voltage. Such a chip would require bias currents I = CU_T/T from 10 μA to 10 pA − a range of six decades. Actually the current range would be larger than this because the fast circuits would run super-threshold and require even higher currents. This huge range of bias current creates special requirements that are quite different than conventional industrial mixed-signal chips, which typically derive all bias currents from a few references spanning only a couple of decades in current.

Bias current references are often left out in experimental chips because designers assume that these ‘standard’ circuits can easily be added in later revisions when the chip’s design can be productized. But this is a poor strategy to achieve process, voltage and temperature (PVT) manufacturing tolerance. As a result, these chips need to be tuned individually for correct operation. These biases are often specified by directly setting bias transistor gate voltages using off-chip components. However, the required voltages depend on chip-to-chip variation in threshold voltage. If these voltages are generated by potentiometers or supply-referenced digital-to-analog converters (DACs), they are sensitive to power supply ripple. Also, the subthreshold currents depend in an exponential way on temperature, doubling every 6–8^°C around room temperature. Potentiometers and voltage DACs consume significant static power. Each chip requires individual adjustment, which can be difficult and time consuming, especially if the parameter space has many dimensions. These adjusted parameters must be carried along with the chip throughout its assembly into a final system and the distribution of this system to end-users.

Some early designers generated scaled versions of the desired currents using off-chip resistors that supply current to on-chip scaling current mirrors (Gray et al. 2001). Although this scheme is straightforward, it requires a pin for each independent bias, it requires a regulated power supply, and it necessitates bulky on-chip current mirrors when a small on-chip current is required. For example, a feasible off-chip resistance of 1 MΩ requires an impractical current mirror with a ratio of 1 million.

Industry-standard current references are poorly suited to the biasing of most neuromorphic chips. The reason is that the references used in industry stem from a long tradition of analog circuits that run above threshold, and that only require a limited span of biasing currents. When these references are used on neuromorphic chips, they provide a small range of potential bias currents, which has the consequence that sometimes refabrication of the chip is required to adjust the current to the required value.

Several groups have developed circuits that replace these off-chip components with digitally configurable on-chip circuits. Some of the designs are open-sourced with layout and schematics (jAER 2007), and have been incorporated into chips from several groups, much as the shared AER transceiver circuits from the Boahen group at Stanford. These ICs include vision and auditory sensors and multineuron chips.

This chapter starts with an extensive discussion of the core circuits, each followed by typical measurements of operating characteristics. The chapter concludes with a brief description of available design kits.

11.2   Bias Generator Circuits

The block diagram in Figure 11.1 shows three main components: the ‘master bias’ that generates the master current I_m, a ‘current splitter’ that subdivides the master current into scaled copies to form a set of smaller references, and a configurable buffer that copies the bias current to the places it is used. Each bias uses a copy of the master current and a current splitter. A selected fraction of the master current is copied from the splitter to form the individual bias current. This current is copied by a highly-configurable active mirror, resulting in a voltage that is connected to gates of transistors in the biased circuits. These circuits are described in the following sections, starting with the master bias.

11.2.1   Bootstrapped Current Mirror Master Bias Current Reference

The master current I_m in Figure 11.1 is generated by the familiar bootstrapped current reference in Figure 11.2 which is attributed to Widlar (1965, 1969) and is first reported in CMOS by Vittoz and Fellrath (1977) (see also textbooks such as Baker et al. 1998; Gray et al. 2001; Lee 2004; Razavi 2001). Transistors M_n1 and M_n2 have a gain ratio (W_n1/L_n1)/(W_n2/L_n2) = M. Since the currents in the two branches are forced to be the same by the mirror M_p1 – M_p2, the ratio in current density in the M_n transistors sets up a difference in their gate-source voltage, which is expressed across the load resistance R. The key feature of this circuit is that the current is determined only by the resistance R and ratio M and the temperature, such that the resulting transconductance is independent of temperature, as we will now discuss.

The master current I_m that flows in the loop is computed by equating the currents in the two branches. In subthreshold, this equality is expressed by

Figure 11.1 Bias generator architecture showing core circuits

Figure 11.2 The master bias current reference, together with startup and disable circuit. I_m is the master current, and R is an external resistance that sets I_m. C_k1 and C_k2 are MOS capacitors of a few hundred fF. The squares represent bonding pads and recommended external connections for prototyping. Adapted from Delbrück and van Schaik (2005). With kind permission from Springer Science and Business Media

where I₀ is the transistor off-current and κ is the back-gate or body-effect coefficient (also known as 1/n). Eliminating I_o and V_n from Eq. (11.1) results in the remarkably simple yet accurate formula Eq. (11.2):

where U_T = kT/q is the thermal voltage. The voltage V_Racross the load resistor R does not depend on the resistance R in subthreshold and provides a direct measurement of temperature:

An above-threshold analysis yields Eq. (11.4) that is not very accurate but still useful for estimating the required resistance:

Here μ_n is the electron-effective mobility, and C_ox is the unit gate oxide capacitance. In strong inversion the current decreases with R², while in weak inversion it decreases as R.

The actual I_m is approximately the sum of Eqs. (11.2) and (11.4). With ideal transistors I_m does not depend on supply voltage or threshold voltage, but is closely proportional to absolute temperature (PTAT) in subthreshold. In reality it is slightly affected by the supply voltage through drain conductance and also by mismatch of the threshold voltage between the transistors in the current mirrors. This master bias circuit is often called the constant g_m circuit because the g_mof a transistor biased with current I_m is independent of temperature for both weak and strong inversion operation of the master bias. The transconductance of a transistor with W/L the same as M_n2biased with current I_m is given by

These g_m depend only on R, M, and κ (Nicolson and Phang 2004). Thus, g_m depends on temperature in either weak or strong inversion only on the temperature-dependence of R and κ. This dependence causes g_m to vary much less than would the exponential dependence of a voltage-biased transistor. This temperature independence holds only if the transistor is of the same type as M_n1 and running in the same operating regime. Circuits that are biased from the smaller currents from the splitter outputs will have a slightly temperature-dependent g_m.

The ratio M is not critical as long as it is substantially larger than 1. Commonly used values range from 8 to 64. The main effect of M is to change the loop gain, which affects power supply rejection, startup, and stability.

11.2.2   Master Bias Power Supply Rejection Ratio (PSRR)

It is important that this master current not be affected by inevitable supply voltage variation or noise. To increase the power supply rejection ratio (PSRR) of the master bias current, the drain resistances of the transistors are increased by using long M_p’s and cascoding M_n1 with M_c1 and M_c2. The pFETs are not cascoded to preserve headroom. Razavi computes the power supply sensitivity of the master bias current as an exercise (Example 11.1 in Razavi (2001)). The result of this small-signal analysis is interesting and a bit surprising in that the sensitivity to power supply voltage vanishes if the M_p2 mirror output transistor in Figure 11.2 has infinite drain resistance. In other words, if the p-mirror copies the current perfectly, the output resistance of the M_n1 (or M_c1) transistor is irrelevant. Why is this plausible? If the p-mirror copies perfectly, it is impossible for the n-mirror to have unequal output current. Therefore, the original assumption that the current is equal in the two branches is satisfied and power supply variation has no effect. One might still think that finite drain conductance in M_n1 increases the gain of the M_n1–M_n2 mirror, but this is not the case, because increased drain conductance does not increase incremental mirror gain; it only increases output current, and incremental current gain is what determines the master bias current. Simulations of the master bias circuit that increase the length of the M_n1–M_n2 mirror (which decreases the mirror’s output conductance) slightly increase the master bias current.

For low voltage operation, where the cascode occupies too much headroom, making transistors M_p1 and M_p2 long and excluding the M_c1–M_c2 cascode are good choices.

11.2.3   Stability of the Master Bias

There is a subtle potential instability in the master bias but it is easily avoided with proper understanding. Excessive C_R can cause large-signal limit-cycle oscillations. Since this node is often connected to an external resistor, it is easy to unintentionally create a large capacitance. A large M ratio can also create a large parasitic capacitance C_R. The circuit can be stabilized by making the compensation capacitor C_n several times C_R. In practice, V_n is brought to a bonding pad, where an external capacitance ensures that the master bias can be stabilized. In the most recent design kits (jAER 2007), a large capacitor is included in the layout and it is not necessary to bring V_n to a pad. For more details of this possible instability, see Delbrück and van Schaik (2005).

11.2.4   Master Bias Startup and Power Control

A startup circuit is necessary for the master bias. Very small current (sometimes incorrectly called ‘zero current’) in both branches of the bootstrapped current mirror circuit can form a metastable operating point (Lee 2004), which can even be stable depending on parasitic currents; see Delbrück and van Schaik (2005) for an extensive discussion.

Whatever the cause of the metastable low current state, the startup simulation in Figure 11.3 shows that escape from an ‘off’ state can be slow, even when it is unstable, so a startup circuit is necessary to escape this parasitic operating point quickly when power is applied.

A number of startup mechanisms are currently in use (Ivanov and Filanovsky 2004; Razavi 2001; Rincon-Mora 2001). Here we describe a four-transistor startup circuit that transiently injects current into the current mirror loop on power-up and then shuts itself off. Unlike many other startup circuits, this mechanism is process-independent because it does not depend on threshold or supply voltage and does not require any special devices. It is used on a commercial computer peripheral product that has shipped hundreds of millions of units over more than ten years of commercial production. However, it is still a good idea to simulate startup behavior over the most pessimistic conditions, e.g., slow ramp-up of supply voltage, low threshold voltage and high temperature.

To understand the startup circuit, refer back to Figure 11.2. Transistors M_k1, M_k2, and M_pd, and MOS capacitors C_k1 and C_k2 enable the startup and power-control functionality. The loop is kick-started on power-up by the current flowing from M_k2, which is ‘on’ until V_k is charged to V_dd by M_k1, which then shuts off. C_k2 holds V_k low on power-up (V_pd is at ground), while C_k1 ensures that V_p is initially held near V_dd, holding M_k1‘off’ so that the kick-start can occur. C_k1 and C_k2 must be large enough so that sufficient charge flows into the loop to get it going; a few hundred femtofarads is typical. C_k1 and C_k2 are MOS capacitors to avoid the necessity of a special capacitor layer, such as a second polysilicon layer. The polarity of the MOS capacitors is arranged so that they operate in inversion (C_k2) or accumulation (C_k1) while kick-start is active. (C_k1 has another important role that is discussed later.) While the bias generator is operating, no current flows in this startup circuit. The charge injected by M_k2 is a complex function of circuit parameters, but the essential point is that M_k2 is not shut off until the master bias has current flowing in it.

Figure 11.3 Simulation of slow restart when off state is intentionally produced. Adapted from Delbrück and van Schaik (2005). With kind permission from Springer Science and Business Media

If the master bias circuit ever falls into a metastable low-current state, there is no rapid automatic recovery. It is possible that such a circumstance could arise under, for instance, deep brown-out conditions with slow recovery of the supply voltage. Capacitor C_k1 is important here because it tends to hold the gate-source voltage of M_p1– and hence its current – constant when V_dd changes. If C_k1 is not included, a sudden drop in V_dd can transiently turn off M_p1, possibly leading to an unintended and extended shutdown of the master bias.

In some systems the ability to completely shut off all bias currents and then restart them is desirable, such as for a sensor chip that needs only periodic activation by an external periodic wake-up signal. This control enabled by the ‘power-down’ input V_pd, which is grounded for normal operation. Raising V_pd to V_dd turns off the master bias and the derived biases by pulling V_c to ground through M_pd and shutting off the current in the loop. Yanking V_pd back to ground yanks V_k low, through C_k2 (M_k1 is ‘off’), and the start-up circuit restarts the current as before. While V_pd is high, no current flows in M_pd, because V_k is at V_dd and M_k2 is off. A conductive path to ground from V_n (say, through a leaky C_n) could require pumping V_pd for a few cycles at a sufficient rate to move the current mirror loop to a regime of positive feedback. But if, as usual, there is no DC path other than through M_n2, a single downward transition on V_pd is sufficient for restart. Other circuits such as the bias buffer in Section 11.2.10 are also adapted to the use of this disable signal by tying the bias to the appropriate rail in the disabled state.

11.2.5   Current Splitters: Obtaining a Digitally Controlled Fraction of the Master Current

The master bias described so far generates a reference current I_m. This master current is a single reference current generated in a single circuit block in a specific location of a chip. In order to use this current as a reference bias for the rest of the analog circuits in the chip, it needs to be first scaled to the specific bias currents needed in the chip, and second, distributed throughout the chip. In this section we concentrate on the first aspect: scaling it to needed values. More specifically, we will describe ways to down-scale to desired values in a digitally controlled manner. This is a good option specially for prototype circuits where the designer may want to explore alternative bias values than those used during the initial simulations and design, or where the biases need adjustment during operation. (Why not scale up the master bias current? Practical values of resistance dictate that the master current lies near the upper end of bias currents. Of course it is possible to scale up the master current by a small multiple by using a scaled current mirror, or more compactly, using a variation on the current splitter sometimes called a compound mirror, but we will not discuss these here. For details on the implementation of a compound-mirror splitter that multiplies the master current by factors of 8 and 64 see Yang et al. 2012, Figure 1.)

Figure 11.4 Splitter concept. The input master current I_m (either sourced on the left or sunk on the right) is converted into an output current I_b according to the digital word provided at control bus w. The remaining current is dumped to I_dump

In general, the current splitter circuit can be represented by the block shown in Figure 11.4. In this block an input current I_m is converted into an output current I_b according to the digital word provided at control bus w. The fraction of input current I_m not driven to output I_b is dumped onto line I_dump. Depending on the circuit technique used for down-scaling the input reference current, this dumping output may or may not exist. In the rest of this section we describe several possible ways to provide a digitally-controlled down-scaled value of the reference current.

Current splitting is accomplished most robustly and compactly by using the principle of current division (Bult and Geelen 1992). We will compare passive and active current splitters and introduce the principle of current division in our discussion of passive splitters next.

Passive Current Splitting Ladder

In the passive splitter in Figure 11.5, the master current is copied to the current splitter by transistor M_p3. The splitter successively divides the copy of I_m in a way similar to an R-2R resistor ladder, to form a geometrically spaced series of smaller currents. By configuring the switches using bits of w, the desired current branches of the splitter are connected to form I_b, while the rest of I_m goes to I_dump.

Figure 11.5 Passive current splitter. M_R and M_2R are identically sized unit transistors

This splitter is called passive because we input a current and the same charge that we input is output at various taps. At each branch, half of the current is split off, and the rest continues to later stages. The last stage is sized to terminate the line as though it were infinitely long. By starting at the far end of the splitter, it is easy to see how the parallel and series combinations of the transistors result in an equal split of the currents at each branch. M_R and the two M_2R transistors (which each have the same W/L as the M_R transistor) form the R-2R network; the octave splitter is terminated with a single M_R transistor. The splitter has N stages, and the current flowing transversely out from the splitter at stage k is I_m/2k. The last two currents are the same. The reference voltage V_n for the pFET gates in the splitter should be a low voltage to minimize splitter supply-voltage requirements, but it needs to be high enough to saturate the output circuit that sums up the selected currents. V_n here is the same master bias voltage V_n from Figure 11.2, because it conveniently scales correctly with master bias current.

The current division principle accurately splits currents over all operating ranges, from weak to strong inversion, dependent only on the effective device geometry. In this R-2R splitter, behavioral independence from the operating regime is most easily understood by following each transistor’s operation back from the termination stage and observing that the transverse M_2R and lateral M_R transistors share the same source and gate voltage and that the transverse transistor is in saturation. It can be easily observed that combining series and parallel paths causes half the current to flow into each branch at each stage without any assumption about channel operating conditions. It is also easy to see that, looking from the input terminal, the entire splitter forms a ‘compound transistor’ that has an effective W/L equal to one of its M_R or M_2R unit transistors.

Active Current Splitting Ladder

The current splitting principle illustrated in Figure 11.5 passively divides an input current into branches. It is also possible to exploit the MOS ladder structure to actively generate weighted current sources. This is illustrated in Figure 11.6, where transistor M₀ is used to set the gate voltage of the ladder structure. One can think of M₀ as being the input transistor of a current mirror (of size W/L), while the series-parallel compound of the other transistors behaves as an equivalent M₁ transistor also of size W/L. This M₁ transistor would be the output transistor of the current mirror. Since both M₀ and M₁ have identical size (W/L), they will drive the same current I_range. However, the total current through equivalent output transistor M₁ is physically branched into current components I_j which add up to I_range, where at each stage I_j = 2I_j+1. As in the passive current splitter case, one has to guarantee that the currents flow through each branch. Consequently, the drain terminals of all vertical transistors should be connected to voltage nodes with the same drain voltage V_D. In Figure 11.6 these drain terminals are connected to either node I_b or node I_dump, but both should be biased at the same voltage V_D to avoid differential drain conductance effects. The switches are set according to the digital values b_j. In the same way as for the passive splitter, the output current value available at node I_b can be any combination of unit current sources I_j. Therefore, the current mirror output transistor M₁ effectively operates as a digitally-controlled–size transistor whose size can be digitally set between 0 and W/L in steps of size (W/L)/(2ⁿ) where n is the number of control bits. Drain voltage V_D has to be large enough to guarantee that a W/L size transistor driving a current I_range would remain in saturation. Similarly to the passive current splitting case, this active current source also operates correctly under the weak, moderate, and strong inversion regimes. However, unlike for the passive splitter, if the smallest currents are smaller than the off current, then the source voltage must be shifted as described in Section 11.2.8.

Figure 11.6 Active current splitter that exploits the current splitting principle for the generation of active current sources © 2003 IEEE. Reprinted, with permission, from Linares-Barranco et al. (2003)

Achieving Splitter Ratios other than Factors of Two

Figures 11.5 and 11.6 show R-2R splitters built from unit transistors that split by octaves, but other ratios are also possible by using M_R and M_2R with different aspect ratios. By changing the aspect ratios of the vertical and horizontal transistors, one can control the relative ratio between consecutive current branches. For example, Figure 11.7 illustrates how to ratio horizontal, vertical, and terminating transistors to achieve a ratio factor N among consecutive current branches.

However, we strongly recommend the use of unit transistors. A ratio N = 8, for instance, would require 7 parallel transverse and a series/parallel combination of 8/7 lateral unit transistors, making the layout large. In this case, it would be much simpler to build an octave splitter and select only every third output. Subtle effects related to substrate bias and short/narrow channel effects can act differentially on transistors with differing aspect ratios. These effects cause nonideal splitter behavior, especially in deep subthreshold. These effects are not always modeled properly, so simulations may not show the correct measured behavior. See Yang et al. (2012) for a specific arrangement of a factor-of-eight splitter and measurements from this structure.

Figure 11.7 Generating arbitrary current ratios between consecutive branches. Adapted from Linares-Barranco et al. (2004). With kind permission from Springer Science and Business Media

Comparing Active versus Passive Current Splitters

Active splitters have the advantage of lower headroom requirements, but the cost can be greater overall imprecision and smaller current range at the low end. Because the active splitter mirrors from a single input transistor to a number of copies, precision depends largely on the original copy, which depends on the matching of the input transistor. Since this transistor is sized to match the unit transistors used in the splitter, its area is constrained more strongly than the pFET copy of the master bias used in the passive splitter illustrated in Figure 11.5. This pFET can have arbitrarily large area, so its matching can be made quite precise. On the other hand, the passive splitter requires a headroom of more than one diode drop, compared with the single diode-drop of the active splitter. Both types of splitters have been successfully used in numerous designs.

11.2.6   Achieving Fine Monotonic Resolution of Bias Currents

MOS transistors in current splitter circuits are prone to inter-device mismatch. As a result the down-scaled digitally-controlled currents have random errors (from splitter to splitter) around the nominal desired value. For example, when using the 2W/L-W/L ratios shown in Figure 11.6 for an 8-bit active splitter with maximum nominal current of 500 pA, one would expect to attain 256 possible current bias values equally spaced between 0 and 500 pA. However, one could obtain the actual measured result shown in Figure 11.8a, where each of the 256 values deviates randomly from the desired nominal value. The maximum possible deviation is obtained for the two central values, because the ladder switches from current iI_i to I₁ (see Figure 11.6). In this particular case, the accumulation of random errors in the branches has resulted in a large gap. Note that increasing the number of branches per ladder does not solve this problem. This can be a severe problem if the user is trying to program a critical value within the gap. Or in another case, it could be that the situation is reversed, and the resulting currents are nonmonotonic in code value. The result would be that increasing code would actually decrease the current for some values. This could be a problem if the bias current is controlled as part of a feedback loop, since it might result in positive feedback instability.

Figure 11.8 Motivation for fine splitters. © 2007 IEEE. Reprinted, with permission, from Serrano-Gottaredona et al. (2007)

Figure 11.9 Duplicate ‘stochastic ladder’ circuit for fine biasing. © 2007 IEEE. Reprinted, with permission, from Serrano-Gottaredona et al. (2007)

To avoid this situation, one option is to use the ‘double ladder’ circuit shown in Figure 11.9 (Serrano-Gotarredona et al. 2007), which is also referred to as a ‘stochastic ladder’. This way, a lot of redundancy is introduced because now each ladder branch is replicated, each with its own random error, and any combination of branches is possible because now there are twice as many control bits. Figure 11.8b shows the result of combining two ladders, each like the one used for Figure 11.8a. As can be seen, the output current now goes up to twice the previous maximum and the digital code (x-axis) now reaches now 2¹⁶. On the y-axis we can see that the values go up and down and that values overlap and the coverage is much finer. Figure 11.8c shows the same current output values as in Figure 11.8b, but re-ordered monotonically. This re-ordering is done in practice by first measuring all the values in Figure 11.8b (or at least those of the sixteen branches), and second storing a lookup table to map from original digital word w_val to the ordered one w_ord. The drawback of this technique is that each fabricated double ladder in each chip needs to be experimentally characterized and a lookup table of 2ⁿ n-bit entries, where n is 16 in Figure 11.8, needs to be computed and stored, either in firmware or software. This calibration time could increase testing cost and the cost of the lookup memory could be prohibitive for production. Another implementation of range selection (Yang et al. 2012), open-sourced in the jAER project (jAER 2007), overlaps the coarse ranges and includes built-in current measurement circuits, potentially allowing filling in of overly-large steps and calibration during normal operation.

11.2.7   Using Coarse–Fine Range Selection

A generic digitally controlled bias cell should be designed in such a way that it can be used for providing a range of possible bias currents as wide as possible. The options described so far build a single ladder per bias cell with as many ladder branches as needed. For example, if our master bias provides a maximum current of 100 μA, and we would need smallest bias currents around 1 pA, we would need an M-2M ladder with at least 27 bits. However, in this case, the smallest programmable current steps are in the order of the smallest current, thus making the tuning in the lower range extremely coarse and providing far too much unnecessary resolution at the highest biases. A solution for this is using coarse–fine range selection, which can also reduce the total number of required control bits (Bult and Geelen 1992; Serrano-Gotarredona et al. 2007); this is also the strategy employed in the latest open-source design kit (jAER 2007; Yang et al. 2012).

Figure 11.10 shows a possible realization of this concept. The reference current is first copied by a ladder structure with a ratio scheme of N = 10. This way, consecutive ladder branches currents are scaled by a factor of 10. A digital selection circuit chooses only one of the branches and provides current Irange. This current is then fed to a ladder with octave ratios. For example, we can have the range selection ladder cover from 100 μA down to 1 pA, which would require 8 output branches for the N = 10 ladder. To select one out of the 8 branches we only need four range selection bits. Then, for the N = 2 ladder we could use 8 bits to have 256 selection values for each range.

The diagram in Figure 11.10 also includes an additional current mirror for output sign inversion, which can be switched into the current path using bit w_sign. Also, the output current can be directed to its destination bias or to an external test pad for measuring the selected current, by configuring bit w_test. In this particular figure, the N = 2 ladder uses the stochastic ladder replication for fine current sweeping (Serrano-Gotarredona et al. 2007). The open-source implementation, aimed at ease of implementation and high degree of integration, is described in Yang et al. (2012). This design kit includes the configurable buffer described in Section 11.2.10.

Figure 11.10 Example bias cell including range selection capability and output current sign selection. © 2007 IEEE. Reprinted, with permission, from Serrano-Gottaredona et al. (2007)

11.2.8 Shifted-Source Biasing for Small Currents

As technology shrinks, so does the power supply voltage and the transistor threshold voltage. All else being equal, subthreshold leakage ‘off current’ I₀ grows exponentially with smaller threshold voltage. (We use the term ‘off-current’ to mean the drain-source current of a transistor that is off. Specifically we distinguish this current from the reverse-biased junction leakage current of sources and drains to the local substrate. The off current is the saturation current of a transistor with V_gs = V_sb = 0, i.e., the pre-exponential I₀ in the saturated subthreshold transistor drain current: I_ds = I₀ exp(κ/U_T), where κ is the back-gate coefficient and U_T is the thermal voltage. I₀ is typically several orders of magnitude larger than the substrate leakage current; e.g., 1 pA vs. 1 fA in a 180 nm process technology.) On the 2 μm technologies of the late 1980s, off currents were around 1 fA. In the mainstream 180 nm analog technologies of today, they hover around 10 pA. In the future many logic technologies will have even larger off currents of up to perhaps 1 nA. In analog designs a conventional current mirror can only copy currents down to a few times I₀ .

Linares-Barranco et al. (2003, 2004) presented the principle of shifted source (SS) biasing (Figure 11.11). The shifted source voltage V_sn of the current mirror is a few hundred millivolts from the power rail to allow the current mirror to operate with its gate voltage below its common source voltage. A level-shifting source follower (biased with current I_bb) tied from the current mirror drain input to the common gate voltage V_g holds the drain-source voltage of the input transistor in saturation even for I₁ that are as small as I₀ or even less. The common sources of both M₁ and M₂ are held at V_sn, which is typically 200 mV to 400 mV above ground. This arrangement allows V_g to drop below V_sn for small (sub-off) input currents. The current mirror is then capable of copying currents several decades smaller than I₀ as illustrated in the right part of Figure 11.11. To build a complete system, complementary pairs of such mirrors are required with supplies V_sn and V_sp.

The shifted source voltages V_sn and V_sp are quite close to the power rails and must be actively regulated there, particularly since they will also be used by any circuits biased by these small currents. The V_sn regulated voltage can be be supplied from the low-dropout regulator circuit in Figure 11.12, with the complementary circuit for V_sp (Delbrück et al. 2010). The reference voltage V_nref is generated by the split-gate diode-connected pair M_r1 and M_r2. M_r1 is wide and short and M_r2 is long and narrow. M_r2 runs in triode mode, acting as a load resistance and thus allowing generation of a reference voltage of 200–400 mV. The buffer amplifier then is used to create a negative feedback loop that regulates the shifted source voltage to the reference voltage. It is important to use a wide-output-range amplifier for the buffer, because the output voltage, which is the gate voltage of the load transistor, may need to swing all the way from low to high voltages, depending on the I_s source current.

Figure 11.11 Principle of shifted-source (SS) current mirror. © 2010 IEEE. Reprinted, with permission, from Delbrück et al. (2010)

Figure 11.12 Shifted-source reference and regulator circuit. © 2010 IEEE. Reprinted, with permission, from Delbrück et al. (2010)

The programmable buffer bias current sources I_bb, which is typically about 1 μA, sets V_nref and biases the p-type error amplifier. The wide pass transistor M_s sinks the current I_s supplied by the N external nFET sources M_L. The OTA drives V_g (when the regulator is enabled) in negative feedback to regulate V_sn to V_nref. If V_sn is too low then V_g is decreased, and vice versa. The I_bb current source onto V_sn holds V_sn up when I_s sourced externally vanishes. It also sets the minimum transconductance of M_s. Switches M₁ and M₂ allow disabling the SS regulator and tying V_sn to ground by disconnecting the OTA and tying V_g to V_dd. Parasitic capacitances C_p (especially across the drain-gate capacitance of M_s) can lead to instability since they provide a positive feedback path from V_o to V_sn. A large C_s /C_p capacitive divider ratio reduces the feedback gain to stabilize the regulator.

11.2.9 Buffering and Bypass Decoupling of Individual Biases

Once the current splitter provides its output current I_b, the next step is to distribute it to its destination point or points within the chip. The situation changes dramatically depending on whether it is a single destination bias point, or there are a large number of them (for example, a bias within the pixels of a million pixel array). In the general case where the bias is a small current or could be used to bias many cells, it is a good idea to actively buffer the bias voltage to de-couple it from external disturbance and enable special states such as being connected to the power rail. Recent design kits have included a general purpose bias buffer cell that provides these functionalities, as well as allowing post-layout choice of bias voltage polarity. This way, designers can simply include the biasing layout and choose the voltage type and other options by setting configuration bits. Here we will first discuss some general decoupling and buffering considerations, illustrated in Figure 11.13, and then describe an implementation of a general purpose bias buffer (BB), shown in Figure 11.14.

Figure 11.13 Bypassing and buffering. (a) and (b) show how to bypass n- and p-type biases. (c)–(e) compare ways to buffer bias voltages. (f) is the circuit used in the small signal stability analysis. Figures (c) to (f) adapted from Delbrück and van Schaik (2005). With kind permission from Springer Science and Business Media

A diode-connected transistor sinking current I_b and operating in subthreshold has a transconductance or source conductance of g ≈ I_b /U_T (neglecting the difference caused by κ). This means that the bias voltage for a small bias current will have a high impedance (e.g., ≈ 10⁸Ω for I_b = 100 pA) and can easily be disturbed by other signals on the chip that are capacitively coupled to it, e.g., by crossing wires or by drain-gate parasitic capacitance. Figure 11.13a,b shows the simplest remedy which is to bypass the bias with a large capacitance to the appropriate power rail (V_dd for p-type and ground for n-type). Bypassing the bias has the additional benefit of greatly reducing the effect of power-supply ripple on the bias current. It is important to bypass to the appropriate power rail so that the bias voltage is stabilized relative to the appropriate transistor source voltage. The parasitic capacitance to the other rail will then have much less effect on the gate-source voltage.

If the chip will be exposed to light, care must be taken when bringing these generated bias voltages off chip because ESD protection structures in the bonding pads can produce significant currents under illumination (e.g., several nA under 1 klux). When the programmed bias current is small, these parasitic photocurrents in the bonding pads can significantly perturb the bias currents. In addition, parasitic conductance between package pins can significantly affect the generated biases when bias currents are in the sub-nA range, especially under humid conditions. Therefore it is a good idea to actively buffer this gate voltage so that its source impedance is independent of the bias current. Section 11.2.11 discusses how parasitic photocurrents affect current splitters. Here we discuss active buffering as shown in Figure 11.13c–f.

Figure 11.14 Configurable bias buffer circuit. The input to the buffer is the selected splitter output I_b and the output is the voltage V_bias. Configuration bits control whether the bias voltage is intended for n- or p-type transistor biasing, if the bias includes an extra diode-connected transistor for cascode biasing, whether the bias is tied weakly to the power rail, and whether a shifted supply voltage is used in connection with shifted-source low current biasing. Transistors with dashed gates are low threshold devices. © 2012 IEEE. Reprinted, with permission, from Yang et al. (2012)

Active buffering of the gate voltage is simple but there are a few issues to watch out for and the principles should be understood to be used effectively. The total capacitance on the bias voltage is often large when a large number of identical circuits (e.g., pixels) are biased. This immediately helps bypass the bias voltage to reduce capacitive coupling. On the other hand, any disturbance of the voltage can last a long time because the large capacitance must be charged back to the static level. The circuits in Figure 11.13c and d and the bias buffer circuit in Figure 11.14 use an active current mirror with feedback that introduces no first-order mismatch because the gate voltage V_bn settles at the voltage required for the input transistor to sink the bias current I_b. This feedback gives them an advantage over the simple voltage buffer of the diode-connected transistor shown in Figure 11.13e, which introduces the offset voltage of the voltage buffer. However, the resonance frequencies of the active circuit must be considered because the amplifier may be driving a large capacitance, so the time constants at the input and output nodes of the amplifier can be comparable. If the resonance frequencies are comparable to the disturbance frequencies, the buffer can amplify the disturbance rather than suppress it.

The condition that avoids resonance can be calculated (Delbrück and van Schaik 2005) by using the equivalent circuit in Figure 11.13f. The response to a sinusoidal disturbance V_x coupled through capacitance C_x is given by 11.6, where the parameters are shown in the figure:

To achieve critical damping, the poles of Eq. (11.6) must lie on the negative real axis. In other words, the solutions to setting the demoninator of the right hand side of Eq. (11.6) to zero ((τ_i s + 1)(τ_o s + 1) + A_i = 0) must be real and negative. To achieve this, Eq. (11.7) must apply to the buffer amplifier time constant:

Here τ_o is the time constant of the output of the unity gain buffer amplifier, which drives (usually) a large capacitance. τ_i is the time constant of the amplifier input node, which consists of the small input capacitance C_i and the large input resistance r_i ≈ V_E /I_b, where V_E is the Early voltage at the input node. A_i is the gain of the input node looking from the gate of M_i. If τ_o = τ_i, we have the condition of maximum resonance, and , which will typically be about 10. When the circuit is properly biased according to Eq. (11.7), however, the equivalent time constant of the high pass filter shrinks to Eq. (11.8):

Compared with the passive case of just diode-connecting the generated bias current, which has a high-pass time constant of τ = C_o U_T /I_b, the actively buffered bias high-pass time constant is reduced by a factor C_o/C_i, which can be many orders of magnitude. To achieve this state, the error amplifier must be biased to be fast enough to fulfill Eq. (11.7). Because these parameters vary with use of the bias and bias current, the buffer current is also made programmable.

11.2.10 A General Purpose Bias Buffer Circuit

The active mirror in Figure 11.13c is used in the general purpose configurable bias buffer (BB) circuit shown in Figure 11.14 (Yang et al. 2012). The input to the BB is the splitter output current I_b and it generates the bias voltage V_bias. This complicated circuit has many configuration switches that enable various modes, but the principle of operation is simply based on a complementary pair of active mirrors that can be optionally configured to use shifted sources (Section 11.2.8) and whether an additional diode-connected transistor is inserted into the current path to generate a cascode bias. The input to the buffer circuit is the programmed fraction I_b of I_m, and the output is a buffered bias voltage V_bias. Internal buffer currents I_BN and I_BP are generated by a separate bias generator that is shared across all biases. In this buffer bias generator, I_BN and I_BP come from diode-connected transistors rather than the BB circuit. V_rail is the power supply voltage supplied in ‘disabled’ state.

When implementing this buffer, it is important to carefully simulate it to study headroom limitations. Transistors M₂ and M₈ are low threshold devices. These are automatically used for large bias currents to allow sufficient headroom. Switches S₃ are configured by logic (not shown) connected to the coarse bias bits so that the proper branch is used depending on the level of current.

11.2.11 Protecting Bias Splitter Currents from Parasitic Photocurrents

When building optical sensors, it is important to consider the effects of parasitic photocurrent when using small bias currents such as those using the shifted source scheme discussed in Section 11.2.8. Every active region can act like a photodiode, creating current to the local bulk (either substrate or well). These photocurrents can be comparable to bias currents for the smallest biases, which could affect circuit operation by changing bias current depending on the light shining on the chip.

For use on an optical sensor chip, current splitters built from pFETs are better to use, because these pFETs are built in an n-well implanted in a p-substrate. (We typically assume a p-type substrate because this has become by far the most common scenario.) Thus they can be protected from the effects of parasitic photocurrents by covering the n-well with metal. No minority carriers will then be generated in the n-well, so there will not be any parasitic photocurrent created in the pFETs. If nFET devices were used, their sources and drains would act as parasitic photodiodes which would collect diffusing minority carriers from exposed areas of silicon.

11.3   Overall Bias Generator Architecture Including External Controller

All these subcircuits interface to an external controller in a complete bias generator. The example discussed here, evolved from Delbrück et al. (2010), is shown in Figure 11.15. An external controller (typically a microcontroller, but it could be an integrated controller) loads configuration bits into shift registers that control a set of N independent bias currents, one of which is shown in the inset. (For an integrated controller, these bits could come directly from a register bank rather than from a shift register.) The master current I_m which is generated by a single bootstrapped mirror is shared over all N biases. In this implementation, the 32-bit configuration word for a bias is shifted into shift register stages (SR) and then latched (L). (The latches are necessary since otherwise the biases would change in an unpredictable manner as the bits were loaded.) The 32 bits are partitioned into 22 bits for the bias current I_b, 6 bits for the bias buffer current I_bb, and 4 bits of buffer configuration. Biases are daisy-chained (15 in the case of this implementation). Bits are loaded on the IN0 bit while clocking CLOCK; after all bits have been loaded, LATCH is toggled to activate new settings. In the original circuits like this one, designs were simplified by using an architecture where bits were serially loaded into a single global shift register. The most recent implementations use a coarse-fine range-selection strategy with addressable biases (Yang et al. 2012).

Figure 11.16 shows a partial layout of the bias generator layout in a 180 nm 4-metal 2-poly process. Each bias occupies an area of about 80% of a 200 × 200 μm² pad. To prevent parasitic photodiode action at low currents, the entire circuit is covered with image sensor black shield and low current parts of the circuit are covered with metal; n-well guard rings around nFETs provide additional shielding from minority carriers that could diffuse laterally through the substrate.

Figure 11.15 Example of overall bias generator architecture. © 2010 IEEE. Reprinted, with permission, from Delbrück et al. (2010)

11.4   Typical Characteristics

Discussion about measured characteristics from one of the fabricated bias generators will conclude this chapter. The intention is to show typical behavior and to bring out some of the observed nonidealities; one example was already shown in Figure 11.8 for current splitter variability. The second example shown in Figure 11.17 is from data taken from the coarse-fine design kit reported in Yang et al. (2012).

Figure 11.16 Part of the layout of the bias generator in Figure 11.15 in 180 nm technology. A single bias occupies an area comparable to a 100 μm-pitch pad

Figure 11.17 (a) Measured bias currents vs. fine bias code value over all coarse ranges. Shifted-source biasing was used for the lowest three coarse ranges. © 2012 IEEE. Reprinted, with permission, from Yang et al. (2012). (b) Measured coefficient of variation (σI)/I) for the fine code value 127 across 12 biases on one chip

Figure 11.17a shows a measured bias current over all 8 coarse ranges. Currents can be generated over a range of more than 180 dB, extending from 25 μA down to more than a factor of 100 smaller than the off current level. The overlapping ranges allow flexibility in choosing a desired bias current. Figure 11.17b shows matching of a mid-level bias current across 12 biases on one chip. The constant relative variability of about 10% (in the smaller current region) at any node of the current splitter is a consequence of the fact that series and parallel resistors combine to have the same total variability as any single element (Scandurra and Ciofi 2003). Variability is reduced for bias currents above threshold.

11.5   Design Kits

Several generations of bias generator design kits are open-sourced (jAER 2007). Open-sourced design kits allow developers to more easily add bias generators to their designs. In the latest generation kit, which targets a 180 nm process (Yang et al. 2012) and Cadence design tools, biases are generated by coarse-fine strategy, can be individually addressed, can be measured with a built in calibration circuit, and are digitally configured with a variety of output options. The custom layout that is necessary for each bias is to tie the reset value of each bias to one of the two power rails. These kits include necessary firmware and host PC software necessary to build expert and user-friendly bias controls such as the ones illustrated in Figure 11.18.

Figure 11.18 GUI control of biases. (a) Expert mode, showing selection of bias type, coarse range and fine code. (b) User friendly mode, where functional control of sensor characteristics is exposed and changes around the nominal value in (a) changes selected biases appropriately

11.6   Discussion

This chapter discussed the circuits and architectures for integrated bias current generators. These circuits can be thought of mostly as specialized current DACs. The next few years should bring still more evolution that adapts and improves these circuits and their system-level implementations towards still smaller process technologies with lower supply voltages and increased flexibility and functionalities. It is likely that calibration will become more important as the cost of digital circuits continues to decrease while transistor matching tends to worsen.

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