| 1D |
one dimensional |
| 2D |
two dimensional |
| 3D |
three dimensional |
| ACA |
analog computing arrays |
| ACK |
acknowledge |
| A/D |
analog–digital (converter) |
| ADC |
analog–digital converter |
| AdEx |
Adaptive exponential integrate-and-fire model |
| AE |
address event |
| AEB |
address-event bus |
| AER |
address-event representation |
| AEX |
AER extension board |
| AFGA |
autozeroing floating-gate amplifier |
| AGC |
automatic gain control |
| ALOHA |
Not actually an abbreviation, ALOHA refers to a network media access protocol originally developed at the University of Hawaii |
| ANN |
artificial neural network |
| ANNCORE |
analog neural network core |
| API |
Application Programming Interface |
| APS |
active pixel sensor |
| AQC |
automatic Q (quality factor) control |
| ARM |
Acorn RISC Machine |
| ASIC |
application-specific integrated circuit |
| ASIMO |
Advanced Step in Innovative MObility (robot) |
| ASP |
analog signal processor/processing |
| ATA |
AT Attachment (also PATA: Parallel ATA); an interface standard for connecting mass storage devices (e.g., hard disks) in computers |
| ATIS |
asynchronous time-based image sensor |
| ATLUM |
Automatic Tape-collecting Lathe Ultra-Microtome |
| aVLSI |
Analog very large scale integration |
| BB |
bias buffer |
| BGA |
ball grid array |
| BJT |
bipolar junction transistor |
| BM |
basilar membrane |
| BPF |
band-pass filter |
| bps |
bits per second |
| Bps |
bytes per second |
| BSI |
back-side illumination |
| C4 |
capacitively coupled current conveyor |
| CAB |
computational analog block |
| CADSP |
cooperative analog–digital signal processing |
| CAVIAR |
Convolution AER Vision Architecture for Real-time |
| CCD |
charge-coupled device |
| CCN |
cooperative and competitive network |
| CCW |
counter clockwise |
| CDS |
correlated double sampling |
| CIS |
CMOS image sensor |
| CLBT |
compatible lateral bipolar transistor |
| CMI |
current-mirror integrator |
| CMOS |
complementary metal oxide semiconductor |
| CoP |
center of pressure |
| CPG |
central pattern generator |
| CPLD |
complex programmable logic device |
| CPU |
central processing unit |
| CSMA |
carrier sense multiple access |
| CV |
coefficient of variation |
| CW |
clockwise |
| DAC |
digital-to-analog converter |
| DAEB |
domain address -event bus |
| DAVIS |
Dynamic and Active-Pixel Vision Sensor |
| DC |
direct current |
| DCT |
discrete cosine transform |
| DDS |
differential double sampling |
| DFA |
deterministic finite automaton |
| DIY |
do it yourself |
| DMA |
direct memory access |
| DNC |
digital network chip |
| DOF |
degree(s) of freedom |
| DPE |
dynamic parameter estimation |
| DPI |
differential pair integrator |
| DPRAM |
dual-ported RAM |
| DRAM |
dynamic random access memory |
| DSP |
digital signal processor/processing |
| DVS |
dynamic vision sensor |
| EEPROM |
electrically erasable programmable read only memory |
| EPSC |
excitatory post-synaptic current |
| EPSP |
excitatory post-synaptic potential |
| ESD |
electrostatic discharge |
| ETH |
Eidgenössische Technische Hochschule |
| EU |
European Union |
| FACETS |
Fast Analog Computing with Emergent Transient States |
| FE |
frame events |
| FET |
field effect transistor |
| FET |
also Future and Emerging Technologies |
| FG |
floating gate |
| FIFO |
First-In First-Out (memory) |
| fMRI |
functional magnetic resonance imaging |
| FPAA |
field-programmable analog array |
| FPGA |
field-programmable gate array |
| FPN |
fixed pattern noise |
| FPS |
frames per second |
| FSI |
front side illumination |
| FSM |
finite state machine |
| FX2LP |
A highly integrated USB 2.0 microcontroller from Cypress Semiconductor Corporation |
| GALS |
globally asynchronous, locally synchronous |
| GB |
gigabyte, 230 bytes |
| Gbps |
gigabits per second |
| Geps |
giga events per second |
| GPL |
general public license |
| GPS |
global positioning system |
| GPU |
graphics processing unit |
| GUI |
graphical user interface |
| HCO |
half-center oscillator |
| HDL |
Hardware Description Language |
| HEI |
hot electron injection |
| HH |
Hodgkin–Huxley |
| HiAER |
hierarchical AER |
| HICANN |
high input count analog neural network |
| HMAX |
Hierarchical Model and X |
| HMM |
Hidden Markov Model |
| HTML |
Hyper-Text Markup Language |
| HW |
hardware |
| HWR |
half-wave rectifier |
| hWTA |
hard winner-take-all |
| I&F |
integrate-and-fire |
| IC |
integrated circuit |
| IDC |
insulation displacement connector |
| IEEE |
Institute of Electrical and Electronics Engineers |
| IFAT |
integrate-and-fire array transceiver |
| IHC |
inner hair cell |
| IMS |
intramuscular stimulation |
| IMU |
inertial or intensity measurement unit |
| INCF |
International Neuroinformatics Coordinating Facility |
| INE |
Institute of Neuromorphic Engineering |
| I/O |
input/output |
| IP |
intellectual property |
| IPSC |
inhibitory post-synaptic current |
| ISI |
inter-spike interval |
| ISMS |
intraspinal micro stimulation |
| ITD |
interaural time difference |
| JPEG |
Joint Photographic Experts Group |
| KB |
kilobyte, 210 bytes |
| keps |
kilo events per second |
| LAEB |
local address-event bus |
| LFSR |
linear feedback shift register |
| LIF |
leaky integrate-and-fire |
| LLN |
log-domain LPF neuron |
| LMS |
least mean squares |
| LPF |
low-pass filter |
| LSM |
liquid-state machine |
| LTD |
long-term depression |
| LTI |
linear time-invariant |
| LTN |
linear threshold neuron |
| LTP |
long-term potentiation |
| LTU |
linear threshold unit |
| LUT |
look-up table |
| LVDS |
low voltage differential signaling |
| MACs |
multiplyand accumulate operations |
| MB |
megabyte, 220 bytes |
| MEMs |
microelectromechanical systems |
| Meps |
mega events per second |
| MIM |
metal insulator metal (capacitor) |
| MIPS |
microprocessor without interlocked pipeline stages (a microprocessor architecture) |
| MIPS |
also millions of instructions per second |
| MLR |
mesencephalic locomotor region |
| MMAC |
millions of multiply accumulate operations |
| MMC/SD |
Multimedia card/secure digital |
| MNC |
multi-neuron chip |
| MOSFET |
metal oxide semiconductor field effect transistor |
| MUX |
multiplex; multiplexer |
| NE |
neuromorphic engineering |
| NEF |
neural engineering framework |
| nFET |
n-channel FET |
| NMDA |
N-Methyl-D-Aspartate |
| NoC |
Network on Chip |
| NSF |
National Science Foundation |
| OHC |
outer hair cell |
| OR |
Octopus Retina |
| ORISYS |
orientation system |
| OS |
operating system |
| OTA |
operational transconductance amplifier |
| PC |
personal computer |
| PCB |
printed circuit board |
| PCI |
Peripheral Component Interconnect |
| PCIe |
Peripheral Component Interconnect Express |
| PDR |
phase dependent response |
| pFET |
p-channel FET |
| PFM |
pulse frequency modulation |
| PLD |
programmable logic device |
| PRNG |
pseudo-random number generator |
| PSC |
post-synaptic current |
| PSRR |
power supply rejection ratio |
| PSTH |
peri-stimulus time histogram |
| PTAT |
proportional to absolute temperature |
| PVT |
process, voltage, temperature |
| PWM |
pulse width modulation |
| PyNN |
Python for Neural Networks |
| Q |
quality factor of filter |
| QE |
quantum efficiency |
| QIF |
quadratic integrate-and-fire |
| QVGA |
Quarter Video Graphics Array; 320 ×240 pixel array |
| RAM |
random access memory |
| REQ |
request |
| RF |
radio frequency |
| RF |
also receptive field |
| RFC |
Request for Comments(a publication of the Internet Engineering Task Force and the Internet Society |
| RISC |
reduced instruction set computing |
| RMS |
root mean square |
| RNN |
recurrent neural network |
| ROI |
region of interest |
| SAC |
selective attention chip |
| SAER |
serial AER |
| SAM |
spatial acuity modulation |
| SATA |
serial ATA (an interface standard for connecting mass storage devices (e.g., hard disks) to computers, designed to replace ATA) |
| SATD |
sum of absolute timestamp differences |
| SC |
spatial contrast |
| S-C |
switched-capacitor |
| SCX |
Silicon Cortex |
| SDRAM |
synchronous dynamic random access memory |
| SerDes |
serializer/deserializer |
| SFA |
spike-frequency adaptation |
| SiCPG |
silicon CPG |
| SIE |
serial interface engine |
| SiN |
silicon neuron |
| SNR |
signal-to-noise ratio |
| SOS |
second-order section |
| SpiNNaker |
spiking neural network architecture |
| SRAM |
static random access memory |
| SS |
shifted source |
| SSI |
stacked silicon interconnect |
| STD |
short-term depression |
| STDP |
spike timing-dependent plasticity |
| STRF |
spatiotemporal receptive field |
| SW |
software |
| sWTA |
soft winner-take-all |
| TC |
temporal contrast |
| TCAM |
ternary content-addressable memory |
| TCDS |
time correlated double sampling |
| TCP |
Transport Control Protocol |
| TN |
TrueNorth |
| TTFS |
time to first spike |
| UCSD |
University of California at San Diego |
| UDP |
User Datagram Protocol |
| USB |
universal serial bus |
| USO |
unit segmental oscillators |
| V1 |
primary visual cortex |
| VGA |
Video Graphics Array; 640×480 pixel array |
| VHDL |
Verilog Hardware Description Language |
| VISe |
VIsion Sensor |
| VLSI |
very large scale integration |
| VME |
VERSAbus Eurocard bus standard |
| VMM |
vector-matrix multiplication/multiplier |
| WABIAN-2R |
WAseda BIpedal humANoid No. 2 Refined (robot) |
| WKB |
Wentzel–Kramers–Brillouin |
| WR_OTA |
wide-linear range OTA |
| WTA |
winner-take-all |
| XML |
Extensible Markup Language |
| ZMP |
zero moment point |
