- Cover
- ESD Series
- Title page
- Copyright page
- Dedication
- About the Author
- Preface
- Acknowledgments
- 1 Analog, ESD, and EOS
- 1.1 ESD in Analog Design
- 1.2 Analog Design Discipline and ESD Circuit Techniques
- 1.3 Design Symmetry and ESD
- 1.4 ESD Design Synthesis and Architecture Flow
- 1.5 ESD Design and Noise
- 1.6 ESD Design Concepts: Adjacency
- 1.7 Electrical Overstress
- 1.8 Reliability Technology Scaling and the Reliability Bathtub Curve
- 1.9 Safe Operating Area
- 1.10 Closing Comments and Summary
- References
- 2 Analog Design Layout
- 2.1 Analog Design Layout Revisited
- 2.2 Common Centroid Design
- 2.3 Interdigitation Design
- 2.4 Common Centroid and Interdigitation Design
- 2.5 Passive Element Design
- 2.6 Resistor Element Design
- 2.7 Capacitor Element Design
- 2.8 Inductor Element Design
- 2.9 Diode Design
- 2.10 MOSFET Design
- 2.11 Bipolar Transistor Design
- 2.12 Closing Comments and Summary
- References
- 3 Analog Design Circuits
- 3.1 Analog Circuits
- 3.2 Single-Ended Receivers
- 3.3 Differential Receivers
- 3.4 Comparators
- 3.5 Current Sources
- 3.6 Current Mirrors
- 3.7 Voltage Regulators
- 3.8 Voltage Reference Circuits
- 3.9 Converters
- 3.10 Oscillators
- 3.11 Phase Lock Loop
- 3.12 Delay Locked Loop
- 3.13 Closing Comments and Summary
- References
- 4 Analog ESD Circuits
- 5 Analog and ESD Design Synthesis
- 5.1 Early ESD Failures in Analog Design
- 5.2 Mixed-Voltage Interface: Voltage Regulator Failures
- 5.3 Separation of Analog Power from Digital Power AVDD to DVDD
- 5.4 ESD Failure in Phase Lock Loop (PLL) and System Clock
- 5.5 ESD Failure in Current Mirrors
- 5.6 ESD Failure in Schmitt Trigger Receivers
- 5.7 Isolated Digital and Analog Domains
- 5.8 ESD Protection Solution: Connectivity of AVDD to VDD
- 5.9 Connectivity of AVSS to DVSS
- 5.10 Digital and Analog Domain with ESD Power Clamps
- 5.11 Digital and Analog Domain with Master/Slave ESD Power Clamps
- 5.12 High-Voltage, Digital, and Analog Domain Floor Plan
- 5.13 Closing Comments and Summary
- References
- 6 Analog-to-Digital ESD Design Synthesis
- 6.1 Digital and Analog
- 6.2 Interdomain Signal Line ESD Failures
- 6.3 Digital-to-Analog Core Spatial Isolation
- 6.4 Digital-to-Analog Core Ground Coupling
- 6.5 Domain-to-Domain Signal Line ESD Networks
- 6.6 Domain-to-Domain Third-Party Coupling Networks
- 6.7 Domain-to-Domain Cross-Domain ESD Power Clamp
- 6.8 Digital-to-Analog Domain Moat
- 6.9 Digital-to-Analog Domain Moat with Through-Silicon Via
- 6.10 Domain-to-Domain ESD Design Rule Check and Verification Methods
- 6.11 Closing Comments and Summary
- References
- 7 Analog-ESD Signal Pin Co-synthesis
- 7.1 Analog Signal Pin
- 7.2 Analog Signal Differential Receiver
- 7.3 Analog CMOS Differential Receiver
- 7.4 Analog Differential Pair ESD Signal Pin Matching with Common Well Layout
- 7.5 Analog Differential Pair Common Centroid Design Layout: Signal Pin-to-Signal Pin and Parasitic ESD Elements
- 7.6 Closing Comments and Summary
- References
- 8 Analog and ESD Circuit Integration
- 8.1 Analog and Power Technology and ESD Circuit Integration
- 8.2 ESD Input Circuits
- 8.3 Analog ESD Output Circuits
- 8.4 Analog ESD Ground-to-Ground Networks
- 8.5 ESD Power Clamps
- 8.6 ESD Power Clamps for Low-Voltage Digital and Analog Domain
- 8.7 ESD Power Clamp Issues
- 8.8 ESD Power Clamp Design
- 8.9 Bipolar ESD Power Clamps
- 8.10 Closing Comments and Summary
- References
- 9 System-Level EOS Issues for Analog Design
- 10 Latchup Issues for Analog Design
- 10.1 Latchup in Analog Applications
- 10.2 I/O-to-I/O Latchup
- 10.3 I/O-to-I/O Latchup: N-Well to N-Well
- 10.4 I/O-to-I/O Latchup: N-Well to NFET
- 10.5 I/O-to-I/O Latchup: NFET to NFET
- 10.6 I/O-to-I/O Latchup: N-Well Guard Ring between Adjacent Cells
- 10.7 Latchup of Analog I/O to Adjacent Structures
- 10.8 Analog I/O to Core
- 10.9 Core-to-Core Analog–Digital Floor Planning
- 10.10 High-Voltage Guard Rings
- 10.11 Through-Silicon Via (TSV)
- 10.12 Trench Guard Rings
- 10.13 Active Guard Rings
- 10.14 Closing Comments and Summary
- References
- 11 Analog ESD Library and Documents
- 11.1 Analog Design Library
- 11.2 Analog Device Library: PASSIVE ELEMENTS
- 11.3 Analog Device Library: Active Elements
- 11.4 Analog Design Library: Repository of Analog Circuits and Cores
- 11.5 ESD Device Library
- 11.6 Cadence-Based Parameterized Cells (PCells)
- 11.7 Analog ESD Documents
- 11.8 ESD Cookbook
- 11.9 Electrical Overstress (EOS) Documents
- 11.10 Closing Comments and Summary
- References
- 12 Analog ESD and Latchup Design Rule Checking and Verification
- 12.1 Electronic Design Automation
- 12.2 Electrical Overstress (EOS) and ESD Design Rule Checking
- 12.3 Electrical Overstress (EOS) Electronic Design Automation
- 12.4 Printed Circuit Board (PCB) Design Rule Checking and Verification
- 12.5 Electrical Overstress and Latchup Design Rule Checking (DRC)
- 12.6 Whole-Chip Checking and Verification Methods
- 12.7 Cross-Domain Signal Line Checking and Verification
- 12.8 Closing Comments and Summary
- References
- Appendix: Standards
- Appendix: Glossary of Terms
- Index
- End User License Agreement
To My Family in Buenos Aires, Argentina
Hector Bergier and Rachel
Marta Bergier and David Engels
Raul Bergier
Gabriel and Mabel Bergier
Juliano Bergier
Mariano Bergier
Virginia Bergier and Fabian Scheinnaizen
Martin Schiennaizen
Guido Schienazen
Hernan Bergier and Soldedad Scieri
Mora Bergier
Ivan Bergier
Fabian Bergier and Costy Yabes
Luciano Bergier
Barbara Bergier
Ian Bergier
Luca Bergier
Diego Bergier and Elena Galan Fajardo
Sandra Bergier
Desiree Bergier
Catriel Bergier
Nahuel Bergier
Nehuen Bergier
Andrea Engels
Lorena Engels
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