11.2.1 Resistors

High-precision resistors are needed in analog applications, which contain high degree of matching and wide resistance ranges. Resistors in analog circuits include:

• Polysilicon resistors
• Metal resistors
• Silicon resistors

The resistors have different resistance tolerance values as well as different temperature coefficients of resistance (TCR) which influence analog application results.

For ESD applications, resistors are used as series resistor elements on signal pins. Resistors can also be used between power rails, between ground rails, and as RC-triggered MOSFET ESD power clamps. For these ESD applications, interdigitated layout practices are acceptable.

ESD robustness of resistor elements is a function of the cross-sectional area of the resistor, the material properties, and the layout and design [3–9]. The power-to-failure of resistor elements are a function of the cross-sectional area, thermal conductivity, heat capacity, melting temperature of the material, and the pulse width. For resistor elements, the ordering of the interconnect melting temperature, tungsten metallurgy has the highest melting temperature, copper, and then aluminum has the lowest.

For serpentine design styles, corner design can lead to a lower ESD failure levels. ESD failure due to current crowding on the corners is worse for 90° angles. ESD failure levels in serpentine design can be improved with chamfered corners.

For analog design, corner design issues can be eliminated using strap connections between segments of the resistor. In analog design, using contacts, vias, and metal connections, the accuracy and matching can be improved between the resistors. With the integration of strap connections, resistor elements can be interdigitated for matching within a circuit.

11.2.2 Capacitors

With a wide range of voltage applications, capacitor elements are needed to support the voltage conditions. Capacitor elements can consist of the following [5]:

• MOS capacitors
• Metal–insulator–metal (MIM) capacitors
• Metal–interlevel dielectric (ILD)–metal capacitors
• Vertical natural plate (VNP) or vertical parallel plate (VPP) capacitors

Capacitors are needed for ESD networks [3–5, 7–9]. Capacitor layout can be common centroid layout or interdigitated layout design but not required since matching is not critical for these circuits. For ESD power clamps, capacitors are used for RC-triggered ESD power clamps. ESD power clamps are typically used between the power and ground rails. RC-triggered power clamps can be used on low-dropout (LDO) regulators; buck, boost, and buck–boost regulators; and other voltage regulator outputs.

The capacitor elements have different levels of ESD robustness. The dielectric thickness influences the failure level of the capacitors.

11.2.3 Inductors

On-chip inductor designs are typically planar inductors formed from the metal wiring of the back end of line (BEOL) of a semiconductor chip. Semiconductor technology utilizes copper, aluminum, and tungsten metallurgies [3–5, 7–9]. For inductors, the melting temperatures of the metallurgy play a role in the ESD failure [5]. The on-chip spiral planar inductors have one of the following design styles:

• Square inductor
• Polygon inductor
• Octagonal inductor
• Circular inductor

These spiral inductors typically have an “underpass” at the center. The underpass connection is typically a lower-level metal design level below the spiral inductor coil.

Inductors can also be formed in intertwined pairs using multiple design levels. These can be used for circuits that require matched inductors or balun applications. Multilevel inductors take up less area than single-level spiral inductors.

11.4.1 Analog Design Library: Reuse Library

Analog design libraries can consist of a “reuse” library where circuit design teams place basic analog design functions into a repository for other teams to use. The reuse library may be a library which is not supported by the quality and reliability team. The problem with reuse library is that if they are not qualified, then EOS and ESD problems may be propagated across many designs. This is a concern with reused analog design with unverified ESD sensitivity. As a guideline, a good business practice is as follows:

• Test and quantify analog functional blocks for ESD and EOS sensitivity.
• Introduce a formal qualification and release process for reuse circuitry.
• Information notes and documentation on EOS and ESD test results on reuse functional blocks.

11.6.1 ESD Hierarchical PCell Physical Layout Generation

In ESD design, it is desirable to change the physical layout of the ESD network. Hence, an RF-ESD design methodology is needed that can vary the physical layout of the design in physical size (e.g., area), form factor (e.g., length, width, and ratio), shape (e.g., rectangular, circular), and relative size of elements within a given circuit (e.g., be able to vary the size of the resistor, capacitor, or MOSFET independently within the common circuit topology) [5, 10–13]. For example, in some chip architectures, it is desirable to place multiple power clamps across a design, instead of a single element. It is also desirable to place different size ESD circuits for a common topology in a common chip. Hence, these features will be needed for integration and synthesis into a semiconductor chip architecture. In the formation of the hierarchical ESD p-cell elements, the generation of the ESD physical layout can be formed using the “graphical method” or the “code method” using SKILL code. In the “graphical method,” the p-cells and physical shapes are placed in the design environment manually. The physical sizes of the O[1] p-cells are defined by its parameters. The physical dimensions that are desired to be modified are passed up to the higher-order p-cell design through “inheritance.” The inherited parameters become free variables which allow the physical size changes of the O[1] elements. The parameters that allowed adjustment in each O[1] element are contained in the final O[n] p-cell ESD network. Another methodology allows for the placement to be completed by software instead of manual placement of the physical elements and the electrical connections. SKILL code generates the schematic directly and forms placement of the elements.

In order for this design method to be successful, either the elements must be scalable or quantified. This can be verified through experimental testing of the ESD elements. Additionally, with the placement of a plurality of elements, new failure mechanisms must not occur. In our case, it was found that there is a range where linearity of ESD robustness versus structure size where this is true, and no new failure mechanisms were evident.

11.6.2 ESD Hierarchical PCell Schematic Generation

An analog ESD method that allows full circuit evaluation and the ability to change the physical size of the element through circuit simulation is desirable [10–13]. Additionally, it is desirable to provide changes in the circuit topology itself within the ESD network. The circuit topology can influence the trigger conditions, capacitance loading, linearity, and RF circuit stability. Hence, it is desirable to have ESD networks that can change the physical topology within a circuit design environment. Analog networks also have a wide range of application and power supply voltages; ESD circuits are required which can be modified to address the different application voltages. Hence, an ESD design system that allows for both change of circuit topology and structure size in an automated fashion is desirable. The circuit topology automation allows for the customer to autogenerate new ESD circuits and ESD power clamps without additional design work. In order for this method to be successful, the interconnect and associated wiring outside of the primitive elements must have a design environment that independently extracts the wiring, via, and interconnects. In our design environment, the wiring and via interconnect are autoextracted, which then eliminates the need for evaluation of electrical characteristics for every model element and every ESD structure.

11.6.3 ESD Design with Hierarchical Parameterized Cells

In semiconductor chip design, there are fundamental ESD functional blocks required in the semiconductor chip synthesis and floor planning. For ESD design, the minimum set of classes of hierarchical parameterized cells needed to support an ESD design system involved are as follows [10–13]:

• ESD input networks
• ESD rail-to-rail networks
• ESD power clamps

In a mixed-signal ESD design system, the ESD design system should contain a family of these elements in each category which satisfy signal types (e.g., digital, analog, and power), analog parameters (e.g., noise, linearity, stability), and spatial placement. For analog input circuits, the loading effects of ESD input and impedance influence are critical for performance evaluation.

For ESD rail-to-rail networks, the issue is stability and noise coupling is important in mixed-signal environments. Noise is a concern in digital networks; peripheral and core circuitries are isolated when the peripheral circuit noise is significant and the interior core logic networks are sensitive to noise disruption. Noise is a large concern in semiconductor chips with both digital and analog function on a common substrate. In mixed-signal applications, functional circuit blocks are separated to minimize noise concerns. Digital noise affects both the analog and DC circuitry impacting the noise figure (NF). Designers need the ability to estimate the noise and stability of the circuit in the presence of multiple circuits and ESD networks. To eliminate noise, digital circuit blocks are separated from the analog circuit blocks without a common ground or power bus. The introduction of the ESD elements between the grounds can address the ESD concerns but increases the noise and stability implications. As a result, the cosynthesis of the ESD and noise concerns needs to be flexible to address both issues. And, for ESD power clamps, the ESD networks can influence noise, stability, and leakage.

11.6.4 Hierarchical PCell Graphical Method

For construction of the p-cell, there are different methods of p-cell definition within the Cadence^TM environment. This methodology is referred to as the “graphical” technique [10–13]. The command structure for p-cell definition involves Stretch, Conditional Inclusion, Repetition, Parameterized Shapes, Repeat along Shape, Reference Point, Inherited Parameters, Parameterized Layer, Parameterized Label, Parameterized Property, Parameters, and Compile. The Stretch function allows Stretch in X, Stretch in Y, Qualify, and Modify. The Repetition function allows for Repeat in X, Repeat in Y, and Repeat in X and Y.

Stretch commands require an algorithm to define the design “expression for stretch.” For this p-cell, the “expression for stretch” is defined as {{pitch * num_stripes_up} – pitch} where “pitch” is the width of the upward diode periodicity and the “num_stripes_up” is an inherited parameter contained in the higher-order p-cell passed from the lower p-cell to address the number of fingers of the diode between the input pad and the V_DD power supply. Likewise for the downward diode, a second “expression for stretch” is defined for the second p-cell diode element stretch line. The expression for stretch is defined as “{{pitch*num_stripes_down}  –  pitch}” for the second stretch line in the y-direction. For the first stretch line, the direction of stretch is “up”; for the second stretch line, the direction of stretch is “down.” For the stretch of the diode p-cells, and the busses, a stretch line exists in the x-direction. For the stretch in x, an “expression of stretch” is defined as {{a * num_segments_up} + b} where a and b are constants. The stretch direction is chosen to the right.

For the P-cell parameter summary, a typical output has the form as shown below:

Parameters defined in this parameterized cells

num_segments_up num_segments_down

num_stripes_up num_stripes_down

Stretch

Stretch Type: Vertical

Name of Expression of Stretch: 2.52*num_stripes_down − 2.52

Stretch Direction: down

Stretch

Stretch Type: Vertical

Name of Expression of Stretch: 2.52*num_stripes_up − 2.52

Stretch Direction: up

Stretch

Stretch Type: Horizontal

Name of Expression of Stretch:

7.6*num_segments_up + 4.2

Stretch Direction: up

Inherited Parameters

Number of instances with parameter inheritance: 2

Instance Name: I3

Inherited Parameter: Name: num_X

Inherited Parameter: Value: num_segments_up

Inherited Parameter: Type: integer

Inherited Parameter: Default: 1

Inherited Parameter: Name: num_PD

Inherited Parameter: Value: num_stripes_up

Inherited Parameter: Type: integer

Inherited Parameter: Default: 1

Inherited Parameter: Name: num_X

Inherited Parameter: Value: num_segments_down

Inherited Parameter: Type: integer

Inherited Parameter: Default: 1

Inherited Parameter: Name: num_PD

Inherited Parameter: Value: num_stripes_down

Inherited Parameter: Type: integer

Inherited Parameter: Default: 1

As part of an analog ESD CAD design system, a hierarchical O[3] parameterized cell is designed which forms bidirectional O[2] series diode strings which can vary the number of series diode elements and the physical width of each diode element. For example, a design may use four diodes in one direction and two in the other direction between the ground rails. The automated ESD design system has the ability to adjust the design size and the number of elements. In digital circuits, the design decision is typically decided based on the digital DC voltage separation required between the grounds; in high-speed digital and analog circuits, the design issue is the capacitive coupling at high frequency. As more elements are added, capacitive coupling is reduced. In our ESD design system, the interconnects and wires automatically stretch and scale with the structure size. Algorithms are developed which autogenerate the interconnects based on the number of diodes “up” versus diodes “down.” As elements are added, both the graphical layout and physical schematics introduce the elements maintaining the electrical interconnects and pin connection.

11.6.5 Hierarchical PCell Schematic Method

A powerful feature of an automated ESD design system is the ability to autogenerate ESD networks from both the “graphical method” and the “schematic method.” Typically, ESD designers start from the graphical layout of the physical design, and circuit designers start from the schematic layout to evaluate the performance objectives. To cosynthesize the performance and the ESD objectives, it is important to be able to have different modes of integration and starting points in the design methodology.

To achieve autogeneration of ESD circuits, a design flow has been developed (Figure 11.1). The flow is based on the development of p-cells for both the schematic and layout cells. The p-cells are hierarchical, built from device O[1] primitives which have been characterized with defined models. Without the need for additional RF characterization, the design kit development cycle is compressed. Autogeneration also allows for design rule checking (DRC) correct layouts and layout-versus-schematic (LVS) correct circuits.

In the ESD CAD design system, the schematic p-cell is generated by the input variables to account for the inherited parameters of input values. A problem with schematic autogeneration is the circuit simulation phase. The circuit may be placed as a subcircuit; however, specter simulation will only allow a single definition of a subcircuit. This prevents the reuse of the schematic p-cell in any other configuration. To retain the ESD circuit variability, a design flow has been built around the schematic p-cell.

From the schematic methodology, four different modes of implementation were addressed:

• Creation of the ESD element
• Creation and placement of an ESD element
• Placement of an existing ESD element
• Placement of an ESD schematic

In an automated design environment, Figure 11.3 shows a representation of the different methodologies. As an example of the schematic methodology, from the schematic editing screen, the user invokes AMS utils → ESD. From the ESD pull-down, four functions are defined: ESD → Create an ESD element, ESD → Create and Place an ESD element, ESD → Place an existing ESD element, and ESD → Place an ESD schematic.

In our ESD CAD design system, the schematic PCell is generated by the input variables to account for the inherited parameters of input values. A problem with schematic autogeneration is the circuit simulation phase. The circuit may be placed as a subcircuit; however, simulation will only allow a single definition of a subcircuit. This prevents the reuse of the schematic p-cell in any other configuration. To retain the ESD circuit variability, a design flow has been built around the schematic p-cell.

In one method, the designer is allowed the capability of building an ESD library with the creation of ESD cells. The designer will select the option to “Create an ESD element.” Figure 11.2 shows an example of where the “Create an ESD element” function initiates creation of an ESD schematic for a parameterized cell of a back-to-back diode string known as “AntiparallelDiodeString.” To generate the electrical schematic, the ESD design system requests the “number of diodes up” and the “number of diodes down”; this determines the number of diodes in the string that are used between digital V_SS and analog V_SS (or RF V_SS) for grounds. For power supply rails, the “AntiparallelDiodeString” is used between digital V_DD and analog V_DD (or RF V_DD). The design system also requests the number of cathode fingers in the diode structures for the “up” string and “down” string. The input parameters are passed into a procedure which will build an ESD cell with the schematic p-cell built according to the input parameters and placed in the designated ESD cell. An instance of the ESD layout p-cell will also be placed in the designated ESD cell. This allows for the automated building of an ESD library, creating a schematic, layout, and symbol of the circuit based on the input parameters. This symbol may be placed in the circuit by selecting the “Place an ESD circuit” option.

The second method allows for the autogeneration of the schematic ESD circuit to be placed directly into the design. This procedure available with the “Place an ESD schematic” option will allow the designer to autogenerate the circuit and place it in the schematic. Since these cells are hierarchical, the primitive devices and autowiring are placed by creating an instance of the schematic p-cell and then flattening the element. The instance must be flattened to avoid redefinition of subcircuits. Figure 11.3 shows the generation of the back-to-back antiparallel diode string.

The problem arises during the layout phase of the design. In the schematic due to the flattening, the hierarchy has been removed, and only primitive elements remain. During design implementation, the primitives will be placed, and the hierarchy will be lost. To maintain the hierarchy, an instance box is placed in the schematic retaining the input parameters and device names and characteristics as properties and the elements are recognized and the primitives are replaced with the hierarchical p-cell.

To produce multiple implementations using different inherited parameter variable input, different embodiments of the same circuit type can be created in our methodology. In this process, the schematic is renamed to be able to produce multiple implementations in a common chip or design; the renaming process allows for the design system to distinguish multiple cell views to be present in a common design.

When the inherited parameters are defined, the circuit schematic is generated according to the selected variables. Substrate, ground, and pin connections are established for the system to identify the connectivity of the circuit. The design system can also autogenerate the layout from the electrical schematic which will appear as equivalent to the previously discussed graphical implementation.

The physical layout of the ESD circuits is implemented with p-cells using existing primitives in the reference library. The circuit topology is formed within the p-cell including wiring such that all parasitics may be accounted for in preproduction test site construction.

In a Bipolar, BiCMOS, and BCD technology, ESD networks can be constructed from these primitive p-cell elements of CMOS, bipolar, and LDMOS elements. Hierarchical parameterized cells can be formed from bipolar-only primitive p-cells, CMOS-only primitive p-cells, LDMOS p-cells, or primitive elements. Additionally, new primitive elements using hybrid levels can be used for the primitive cell design. From the lowest-order O[1] primitive parameterized cells, hierarchical parameterized cells can be constructed to form a library of ESD networks. In the list of primitive p-cell elements, the hybrid primitive elements can provide advantages in ideality, capacitance, substrate injection, noise isolation, latchup robustness, and ESD robustness.

In this mixed-signal ESD design system methodology, there are significant advantages and limitations. This methodology developed has been adopted in a foundry environment and has demonstrated significant unanticipated advantages in an analog and mixed-signal design team environment:

• A significant improvement in design and release productivity is evident from implementation of the hierarchical parameterized cell ESD library.
• The designs are completed at the test site phase; this allows for direct implementation into the design kit release/verification process at the test site phase of the development cycle.
• The hierarchical parameterized ESD designs do not need unique DC and AC characterization since the designs contain all AC characterized elements; this provides no additional characterization workload and will be updated with all design releases.
• The customers do not continue to request alternate size structures of different form factors after the initial release.
• As the design system matures, the number of inherited parameters can be increased to allow increased customer flexibility to address area, form factor, or other issues.
• The modular nature of the hierarchical ESD designs allows reuse and flexibility. The introduction of new ESD networks is possible utilizing the existing implementation and modifying the hierarchy for the modification.

11.7.1 ESD Technology Design Manual Section

ESD technology design manual sections are important for defining the usage of ESD elements and the supported networks. ESD technology design manuals are typically contained within the technology design manual. Technology design manuals contain all the design rules for the specific technology.

Historically, in early ESD development, the ESD technology design manual section was small and not comprehensive. In the 1980s, the ESD design manual section contained one or two ESD elements, a few recommendations, and no ESD DRC rules. The analog ESD design guidelines utilized the same solution as the digital ESD guidelines. Today, ESD technology design manual sections have been significantly expanded.

ESD technology design manual sections can include the following:

• ESD required specifications
• ESD supported standards
• ESD supported designs
• ESD design rules
• ESD design recommendations
• ESD guard ring rules
• ESD layout design practices
• Do’s and Don’ts

11.9.1 EOS Design Release Process

An EOS design release process should contain some of the following items:

• Package EOS requirement
• Bond wire EOS requirement
• On-chip EOS protection
• On-chip ESD protection
• On-chip power rail requirements for EOS and ESD
• On-chip interconnect width requirements for EOS and ESD
• EOS robustness of technology elements
• Product—application EOS and ESD compatibility
• Product—technology EOS and ESD compatibility
• EOS DRC results
• EOS LVS results
• EOS electrical rule check (ERC) results

By establishing a good semiconductor chip release process, the risks for EOS can be reduced for semiconductor manufacturing release. Figure 11.6 shows an example of an EOS control program that can be applied to an analog technology.

11.9.2 Electrical Overstress (EOS) Cookbook

In the product definition, design integration, and planning stage, many corporations have developed “cookbook” documents for circuit and printed circuit board (PCB) design teams [8, 9]. An EOS cookbook can be used by the entire team to avoid design implementation errors and insure product success.

By establishing a good product release process, the risks for EOS can be reduced for semiconductor manufacturing release and EOS robustness in the field. Whereas an EOS or ESD design manual may refer to the different EOS and ESD design, an “EOS cookbook” will provide information of correspondence between circuit type and the protection elements. An EOS cookbook should contain some of the following items:

• Guideline on how to use the document
• EOS specification requirements for qualification
• EOS and ESD models
• EOS and ESD specification references
• Off-chip EOS protection solutions library
• Advantages and disadvantages of different EOS protection solutions
• Off-chip EOS protection layout
• Off-chip EOS guidelines
• PCB EOS protection solutions
• Package EOS requirement
• Bond wire EOS requirement
• On-chip EOS protection
• On-chip ESD protection
• On-chip ESD layout
• On-chip power rail requirements for EOS and ESD
• On-chip interconnect width requirements for EOS and ESD
• Guard ring placement and definition
• On-chip ESD power clamp placement
• EOS robustness of technology elements
• Product—application EOS and ESD compatibility
• Product—technology EOS and ESD compatibility
• Table of pin types

One of the most critical issues in an EOS and ESD cookbook is the interrelationship and compatibility of the EOS and ESD solutions used for specific pin types. Hence, the table of pin types is the key core of the EOS and ESD cookbooks.

11.9.2.1 Table of Pin Types

The table of pin types is the most critical element of the EOS and ESD cookbooks. This section identifies the type of pin and the power domain of the pin. For the specific pin type, a specific recommendation of what EOS and ESD solution is needed. In this section, the pin type identifies the Cadence library element cell name, circuit schematic, and the connectivity. For example, the pin types would be segmented by power domain (e.g., 2.5, 5.0 V, and HV domain). Additionally, there is segmentation of analog, digital, and HV circuitry. Circuit functions of inputs, outputs, and bidirectional are segmented for the different ESD and EOS solutions. In the end, clear guidelines are set for the circuit design teams so that the correct EOS and ESD circuit is used for the specific circuit to avoid mismatch between the product application voltage tolerance of the elements and proper “turn-on” of the different EOS and ESD elements for the specific circuit (Figure 11.7).

The pin type table for the different voltage domains can include the following [9]:

• V_DD power input
• V_DD power input/output
• Digital input
• Digital output
• Digital open-drain output
• Bidirectional I/O
• Analog input
• Analog output

The pin type table and corresponding ESD network for HV domains can include the following:

• VIN or V_DD power input
• HV digital input
• HV analog output
• HV open-drain output
• HV phase output
• HV phase input
• Analog output

The ESD design networks can include isolated and nonisolated designs. For power technologies, the ESD designs can include the following:

• Nonisolated ESD networks
• Isolated ESD networks (5, 10, 40, 60, 80, and 120 V)

Isolated and nonisolated designs are required for the following:

• Primary stage signal pin ESD
• Secondary CDM signal pin ESD
• Domain-to-domain ground ESD networks
• ESD power clamps

11.9.3 Electrical Overstress Checklist

In the product definition, design integration, and product release, it is very important to establish checklist for providing EOS product robustness [8, 9]. EOS checklists can be used in the product release and sign-off process.

An ESD checklist for a product release is commonly in the development of semiconductor components. Figure 11.8 is an example of an ESD checklist.

In the product sign-off and release process, there are members of the team that are from application engineering, product definition, marketing, device design, circuit design, packaging, reliability engineering, quality engineers, functional test engineers, and management. An EOS checklist must be understood by the entire team to avoid design implementation errors and insure product success.

An EOS checklist for a product release should contain some of the following items (Figure 11.9):

• EOS environment and application requirements
• ESD environment and application requirements
• Product specifications and EOS implications
• Off-chip EOS protection solutions
• PCB EOS protection solutions
• PCB electrical characteristics
• Package EOS requirement
• Bond wire EOS requirement
• On-chip EOS protection
• On-chip ESD protection
• On-chip power rail requirements for EOS and ESD
• On-chip interconnect width requirements for EOS and ESD
• EOS robustness of technology elements
• Product—application EOS and ESD compatibility
• Product—technology EOS and ESD compatibility
• DRC results
• LVS results
• ERC results
• Functional test results
• ESD test results
• EOS test results
• System assembly procedures
• Manufacturing audit results
• Sign-off release of all organizations (e.g., technology, product definition, quality)

By establishing a good product release process, the minimization of EOS losses can be reduced for semiconductor manufacturing release and EOS robustness in the field.

11.9.4 Electrical Overstress Design Reviews

As part of the semiconductor chip release process, an EOS design review should be part of the process [8, 9]. In an EOS design review, the review process should evaluate the following:

• EOS environment and product compatibility
• Package compatibility
• Wire bond current handling capability
• EOS protection device—signal pin compatibility
• EOS protection device and ESD protection device compatibility
• EOS DRC results
• EOS LVS results
• EOS ERC results
• Electromigration maximum current density compatibility

In the EOS design review process, visual inspection of traces on the PCB and interconnect wiring levels to improve the maximum current carrying conditions is valuable to build EOS robust products.