Chapter 3

Transistors

The invention of transistor by scientists William Shockley, John Bardeen and Walter Brattain at AT&T Laboratories at New Jersey in the USA has revolutionised the electronic devices resulting in various applications of electronics and communication engineering fields around the universe.

The family of transistors consists of

1. Bipolar Junction Transistors (BJTs)

   (N-P-N Transistor and P-N-P Transistor)

2. 1. Junction Field Effect Transistors (JFETs)

      (N-Channel JFET and P-Channel JFET)

   2. Metal-oxide Semiconductor Field Effect Transistor (MOSFETs)

      Enhancement MOSFETs; Depletion Enhancement MOSFETs

3. Unijunction Transistor.

3.1 Bipolar Junction Transistor (BJT)

A bipolar junction transistor has emitter (E), base (B) and collector (C) regions made of either P-type or N-type of semiconductor materials with a provision for three connecting terminals to the three semiconductor material regions. The three terminals of the device are emitter, base and collector. There are two types of transistors, one of them N-P-N type and the other P-N-P type, based on the semiconductor materials used in the device.

As shown in the Figures 3.1 and 3.2, transistor consists of three layers, emitter layer, the base layer and the collector layer. Between base and emitter regions, one P-N junction J₁ exists, which is known as the input junction or the emitter junction. A second P-N junction J₂ exists between base and collector regions, which is known as output junction or the collector junction.

The functioning of the active device, the transistor depends on the biasing voltages to the two PN junctions and one of the methods of operation of the transistors as common emitter transistor (CE Transistor) or common base transistor (CB Transistor) or common collector transistor (CC Transistor) depending on the circuit features, their applications are decided.

For a transistor to act as an amplifying device, it requires that the base-emitter junction J₁ is forward biased and the base-collector junction J₂ is reverse biased. The arrow on the emitter terminal of the transistor symbols, shows the direction of forward current when the emitter base junction is forward biased.

Transistor device can be connected in three basic modes or configurations that are known as (1) common emitter transistor configuration (CE Transistor operation), (2) common base transistor configuration (CB transistor operation) and (3) common collector transistor configuration (CC transistor operation). In each mode, one of the three terminals of the transistor is grounded and the other two form input and output terminals. Thus, transistor is operated as a four terminal or a two-port network. For instance, in common emitter configuration the emitter terminal is grounded and the input is applied between base and emitter forming the input port. Output is obtained between collector and emitter terminals, which form the output port. Thus, a transistor is considered as a two-port network as shown in the Figures 3.3, 3.4 and 3.5.

Common Emitter Transistor Configuration

Common Base Transistor Configuration

Common Collector Transistor Configuration

For an N-P-N transistor, emitter region is made up of heavily doped N-material to provide a large enough emitter current I_E. The base region is a very thin P-layer region and least doped and is of smaller area of cross-section. The collector region is again an N-layer that is moderately doped. The collector region is larger in area than the emitter and base regions.

Basic Operation

Basically, the bipolar junction transistor (BJT) is used as a two-port network or as a four terminal network and functions as an amplifying device along with other applications. The name for the transistor device itself is an acronym formed from the two words transfer + resistor = transistor, which will be clear in the course of discussion of the concept of working of the transistor as an amplifying device.

For achieving different levels of resistance, say, low resistance at the input port, the input junction of the transistor is to be forward biased and to achieve larger resistance at the output port of the transistor output junction is to be reverse biased. These different levels of resistances at the input and output ports of the transistor contribute to the amplifying action of the transistor. Thus, for the transistor to act as an amplifying device, there is need for biasing the input (emitter junction) and output (collector junction) junctions of the transistor.

The transistor is known as bipolar junction transistor (BJT), since both electrons and holes participate in the device conduction mechanism to contribute to the flow of various currents through the device, thus is, the operation of the device.

For a transistor to function as an amplifying device the input junction called as the emitter junction J₁ of the transistor is to be forward biased (D.C. source used for this purpose is known as bias voltage) by a voltage and the output junction, the collector junction J₂ is to be reverse biased by a voltage. Consider common emitter operated transistor with forward bias V_BE to the input junction J₁ for the input diode between base and emitter and reverse bias V_CE to the output junction J₂ for the output diode between base and the collector of the NPN transistor as shown in Figs. 3.6–3.9. (Concept of virtual diodes is introduced for clarity of understanding of device operation.)

When the forward bias V_BE is increased, there are two forces that act on the majority carrier electrons in the N-material emitter of the N-P-N transistor. Force F_VBE = e. V_BE due to the forward bias pushes the electrons towards the junction, thereby reducing the depletion region about the input diode junction J₁ (of the input diode) between base and emitter regions of the transistor. The negative immobile ion charge at the junction J₁ in the P-material base region due to the contact voltage (or built-in voltage or barrier potential V_B) V₀ tries to restrain the entry of electrons with a force V_V0 = e V _V0 as long as the barrier potential V₀ is not reduced. Once the forward bias V_BE overcomes the opposing affect of contact potential; that is, when the actual junction potential (V₀ – V_BE) at that instant is less than the barrier potential V₀; electrons are injected from the emitter into the P-material base region of the transistor.

The movement of the injected minority carrier electrons from the emitter into the base region to the other end of the base area is by diffusion, because of the charge gradient among the injected electrons and the small quantity of originally existing minority carrier electrons in the P-type base material. During this course of journey some electrons recombine with the holes in the base material. These recombinations are less in number, because of the small area of cross-section of the base material and light doping; the numbers of available holes for recombinations are less For a good N-P-N transistor, almost all the electrons injected from the emitter into the base will be collected and I_C is preferable to be almost equal to I_E. Hence, the P-type base region should be narrow and the electron lifetime should be long. The lost holes in recombinations are supplemented by positive terminus of V_BE contributing to the very small magnitude of the base current I_B; which is shown as entering into the base of the transistor. Once the injected electrons are at the junction J₂ of the output diode, the electrons enter the collector region because of the reverse bias to the output junction J₂ (of the output diode) and then are pulled onto the positive of the supply voltage V_CE. So, the collector current I_C is into the collector terminal (direction of the conventional collector current I_C is opposite in direction to the movement of electrons out of the collector terminal). Also, it can be seen from the directions of flow of the base current and the collector current through the emitter terminal as the emitter current I_E; which is the sum of the base current and the collector current.

Mathematically,                                |I_E| = |I_B + I_C|

Thus, mathematically I_E is expressed as above, for the N-P-N transistor under discussion.

For understanding the physical operation of the N-P-N transistor, the transistor is considered to be the virtual connection of two semiconductor diodes (i.e. one diode, the input diode between emitter and base and the second diode, the output diode between base and the collector) back to back. For a transistor to be operated as an amplifying device, the input diode (N-P diode) between base and emitter with junction J₁ is to be forward biased and the output P-N diode between base and collector with junction J₂ is to be reverse biased. Voltage V_BE forward biases the input diode and the voltage V_CE reverse biases the output diode as shown in Fig. 3.7 (wherein the concept of virtual base through two diodes back to back for an N-P-N transistor is visualised).

N-P-N Transistor Working

Figs. 3.8 and 3.9 show the N-P-N transistor with biasing voltages for the common emitter mode operation to understand the device operation. The forward bias V_BE (D.C. source V_BB is used to provide the forward bias V_BE) between emitter and base regions for the junction J₁ (of the virtual input diode) reduces the depletion region (transition region or space charge region) width W_EB about the junction J₁. The forward bias causes the movement of majority carrier electrons from the emitter into base region.

Emitter region is heavily doped and so large numbers of electrons are injected from the emitter into the base region. That is how the emitter is considered as the source of electrons. At the same time, holes move from the base into the emitter region. The numbers of holes that move from the base into the emitter are deliberately made less, because of small area of cross-section of the base and its light doping. So, the emitter current I_E is almost contributed by the injected electrons from the emitter into the base region and further proceeding towards the collector region.

There is a concentration gradient between injected electrons from the N-type emitter into the base region and the small number of originally existing minority carrier electrons in the P-material base. As the electrons diffuse through the base material, some electrons recombine with the holes. The number of recombinations are deliberately made less by reducing the area of the base and its light doping concentrations, so that the probability of recombinations is less. The lost holes due to recombination are supplemented by the positive terminal of V_BE and enter through the base lead contributing to the base current I_B due to the holes entering the base region. The remaining electrons enter the collector region and are collected by the collector due to the positive nature of the reverse bias voltage V_CE across the junction J₂ (of the virtual output diode). The collector area is much larger than the emitter area to reduce the junction heating due to the power dissipation at the collector junction.

The Current Components through the Transistor

The current components through the transistor device and external paths and also the depletion region widths to illustrate base width modulation are shown in the Fig. 3.10

The transistor operates in the active region when the base -emitter junction J₁ is forward biased and the base-collector junction J₂ is reverse biased irrespective of the transistor configuration. The emitter current I_E is the sum of majority carrier electron current and the minority carrier hole current in the N-P-N transistor as shown in the Fig. 3.10.

 

All the electrons that cross the emitter -base junction do not reach the collector, since there are some recombinations with holes in the base region and the remainder enters the collector and the collector current component is I_NC. There is a small minority carrier current due to reverse bias of the base-collector junction designated as the current I_C0.

The net collector current will be I_C = (I_C0 – I_NC); if I_E is not equal to zero. When I_E = 0, the collector current I_C = I_C0; since I_NC representing the injected carrier current is zero, since I_E = 0.

Emitter injection efficiency as per definition,

Base width Modulation and Early Effect

The bias voltage V_EB forward biases the input junction J₁ of the N-P-N transistor and the bias voltage V_CB reverse biases the output junction so that the transistor operates as an amplifying device. The reverse biased base to collector junction produces depletion regions into the base and collector regions with widths inversely proportional to the doping levels. Thus, the spread of the transition regions or the space charge regions into the base region is much more into the base region than into the collector region, which becomes relatively negligible. Also, almost all the depletion region width spread is in the base region only. This reduces the effective width of the base region proportional to the applied reverse potential or bias voltage across base-collector junction J₂. These types of changes in the effective base width with variations in the reverse biasing voltages to the output junction of the transistor is known as base width modulation as shown in Fig. 3.10.

The reduction in the effective base width with increase in reverse bias reduces the recombination probabilities of holes and electrons in the base region resulting in the decrease of base current I_B and consequent increase in the collector current I_C. This is called as early effect. The upward slope in the output characteristics of transistors is due to the early effect that will be clear in later discussions. But for the early effect, the collector current should be independent of the reverse bias to the output junction, since the charge carrier reach the collector falling through a potential valley at the output junction which are further explained at the explanation for obtaining the transistor output characteristics.

3.2 Transistor Characteristics

To know the electrical behaviours of the transistor and determine the application or use of the transistor in the practical electronic circuits, the following setup shown in the Fig. 3.11 is used. The curves that represent the variations of currents with respect to voltages at the input and the output ports are known as the static characteristics of the devices. The characteristics between the parameters V_CE and I_B at the input port, maintaining V_CE constant are called the input characteristics. The characteristics between the parameters V_CE and I_C those at the output port, maintaining I_B constant are called the output characteristics.

Input Characteristics

As can be seen from the curves, the input characteristics are nothing but the forward characteristics of the input junction P-N diode. Input characteristics of a common emitter transistor are between V_BE and I_B (the input port parameters of the CE transistor) for constant values of V_CE. To start with a particular value of collector supply voltage V_CE or V_CC is applied at the output port for example 5 volts. The magnitudes of input voltage V_BE and current I_B are measured for various values of V_BE. Now, V_CE is changed to say 10 volts and the magnitudes of V_bE and I_B are measured and tabulated. Using the observed data the input characteristics of the transistor can be drawn that look like the curves in the Fig. 3.12.

Thus, up to and below Vγ (cut in voltage) of the input diode or the emitter junction, the base current I_B is virtually zero. From Vγ onwards, the base-emitter diode is progressively forward biased and the input current starts rising slowly first and rapidly due to the exponential relation between voltage and current. As can be seen from the curves, the input characteristics are nothing but the forward characteristics of the P-N diode.

For the higher V_CE (10 volts) the reverse bias on the output junction, the collector junction increases. The increase in reverse potential increases the depletion region widths in both base and collector regions about the junction. The increase in depletion width is more on the base side than on the collector side, since the base is much less doped than the collector region. To wit, the spread of the depletion width is mostly on the base side and literally negligible on the collector side. Thus, the effective base width decreases and the effective base resistance increase causing a decrease in base current. The field between emitter and base increases, pulling more electrons from the emitter region. Thus, increasing the emitter current as well as collector current. That is the reason why, base current decreases and collector current increases.

 

As is observed in the characteristics, this variation of base current due to variation of reverse bias on the base-collector junction is due to base-width modulation or early effect.

The input characteristics show that for higher V_CE, the curve is pushed to the left or for a given V_BE; I_B1 for V_CE1 is less than I_B2 for V_CE2; where V_CE2 is greater than V_CE1.

Output Characteristics

Using the experimental setup shown in the Fig. 3.11, the transistor output characteristics are obtained. Initially, with I_B = 0 microamperes (Zero V_BE), varying V_CE resulting collector current I_C magnitudes are observed. Now the collector current will be simply equal to I_CO, the saturation current, because the forward bias V_BE to the emitter junction is zero. V_BE is adjusted to choose a convenient value of I_B and is to be kept constant. V_CE is varied in steps and the pairs of values of V_CE and I_C are observed and tabulated. For different sets of constant values of I_B, variations in I_C for varying magnitudes of V_CE are observed and tabulated. Plotting the observed data, a family of curves known as the Transistor output characteristics between V_CE and I_C for constant values of I_B can be obtained as shown in the Fig. 3.13

Interpretation of Output Characteristics

The output characteristics show that there are three distinct regions:

(1) Active region, (2) Cut off region, and (3) Saturation region.

In the cut-off region, the collector current I_C is almost zero and is equal to I_CEO; the reverse saturation current between emitter and collector with base open circuited. In this region, the transistor acts as a open switch.

In the saturation region, there is a large collector current (I_C) variation for small region in which V_CE changes very much less. V_CE is of the order of a few tenths of a volt and is called as V_CE sat. In this region the transistor acts as a closed switch with virtually zero voltage drop across it. The resistance r_{CE sat} in this saturation region is of the order of a few ohms.

In the active region, with increase in I_B, the output characteristics shift up. For a given I_B with V_CE = 0 volts, I_C = 0 mA. As V_CE increases, I_C increases up to knee points and beyond that knee region, the collector current (I_C) increases with V_CE with a small upward rise. In fact, the current should have been constant but for early effect.

3.3 Small Signal Low Frequency Amplifier, h-Parameters

An amplifier can be considered as a two-port (four-terminal) network, with conveniently defined parameters, which find practical use. For instance, for a transistor circuit design, the hybrid parameters are useful. Transistor is basically a current amplifier but natural sources are voltage type in nature. So, the following expressions are used to represent the input and output relations.

Considering the transistor as shown in the Fig. 3.13 A

 

 

Putting the above equations in matrix form

As can be seen later, the parameters h₁₁, h₁₂, h₂₁ and h₂₂ do not have the same dimensions; h-parameters are known as hybrid parameters.

From the above equation, by applying some boundary conditions, h-parameters can be obtained.

If in equation (3.1) and (3.2), V₂ is made zero, that is, output port is short-circuited

h₁₁ has the dimensions of a resistance and pertains to the input port and it can be termed input resistance h_i represented by h_i = The unit of input resistance h_i is ohms.

In the same way,

h₂₁ is a dimensionless quantity representing the ratio of output current to input current or current gain. This is represented by h_f = and is called forward current gain h_f. It is a dimensionless quantity.

Now by making I₁ = 0 or open circuiting the input port, two more parameters are obtained as following:

h₁₂ is a reverse voltage transfer ratio and is named h_r. It is a dimensionless quantity and gives an idea as to the voltage that appears across the input port. This in fact, represents the unwanted voltage transfer from the output to the input, since amplifiers should be preferably unilateral in transfer of energy from input into the output ports, but not the other way round.

h₂₂ represents the admittance of the output port and is designated as output conductance, h_o. h_o is measured in mhos or siemens.

Thus, as the h-parameters possess a mixture of units, they are known as hybrid parameters.

When applied to analysis of amplifiers with alternating signals V₂ = 0 and I₁ = 0 represent constant D.C. values of voltage at the output port and current at the input port. Since the transistor characteristics are not entirely linear, the values of the h-parameters change from point to point and are defined over small linearised regions and hence are called small signal parameters.

In this context, input resistance

Forward current gain

Reverse voltage transfer ratio

Output conductance

Transistor amplifiers can have three configurations with any one of the terminals grounded. The other two terminals forming the input and output terminals subject to the original definition.

So, three sets of h-parameters are obtained with the second subscript to the h-parameters, designating the grounded terminal.

So, for CE configuration of transistor the h-parameters become h_ie; hf_e; h_re and h_oe.

For common base configuration these parameters are h_ib; hf_b; h_rb and h_ob.

For common collector configuration, the h-parameters are h_ic; hf_c; h_rc and h_oc.

All these parameters can be determined from the static characteristics of the transistor.

The different sets of parameters are interrelated and inter convertible. For instance,

where

and using →

or

Similarly,

or

For CC parameters

h_íc and h_oc are equal to h_ie and h_oe, respectively.

Between CE, CC and CB as per chosen directions of positive and negative polarities, CE configuration is considered to be an inverting voltage amplifier, whereas for the same chosen polarities, CB and CC configurations form non-inverting amplifiers.

Common emitter configuration has input impedance h_ie of the order of 1 K Ohm and output impedance of the order of 40 K ohms.

For common base configuration the input impedance h_ib will be of the order of a few ohms 10 to 20 ohms and has output impedance of the order of 2 M Ohms.

CB configuration has a reasonable voltage gain but current gain h_fb or α is less than unity (I_c (output current) < I_e (input current)).

CC configuration has a current gain of hf_c = (1 + hf_e) but the voltage gain is less than unity (as will be explained later it forms the voltage series negative feedback amplifier with feedback factor

Determination of Reverse Voltage Transfer Ratio h_re, and R_IN or h_ie

Input characteristics to find out (R_in or h_ie) are shown in the Fig. 3.14.

Input resistance R_in or h_ie of the common emitter transistor is defined from the forward resistance of the input diode as and can be determined from the input characteristics as shown in the Fig. 3.14.

For V_BE1, there is a corresponding I_B1, and for another base-emitter voltage V_BE2; I_B2 is the base current.

Therefore                    V_{B E2} − V_{B E1} = ΔV_{B E}

And corresponding increment in base current ∆I_B = I_B2 – I_B1.

This is the slope of the input characteristic for a specific value of V_CE.

Determination of (R_in or h_ie)

Determination of the Reverse Voltage Transfer Ratio h_re

A constant I_B line is drawn on the input characteristics of CE transistor of Fig. 3.14A; to determine the reverse voltage transfer ratio h_re defined as following. h_re is the ratio of change in base voltage V_BE to change in collector voltage V_CE for a constant I_B.

Determination of Current Gain h_fe and R_out = 1/h_oe and g_m from Output Characteristics:

Determination of the Current Gain β or h_fe of the Common Emitter Transistor

β, the incremental current gain is also called h_fe and is obtained in the following way.

For a common emitter operated transistor, for a given V_CE; the ratio of incremental collector current ∆I_C and incremental base current ∆I_B is defined as the small signal forward current gain β or h_fe.

Forward current gain β of a common emitter (CE) operated transistor is defined as following

Forward current gain β of a common Emitter (CE) transistor can be determined from the

Data from the Common emitter transistor output characteristics of Fig. 3.15 to determine β is as follows.

            I_B2 = 200 μA; I_C2 = 20 mA  I_B1 = 100 μA; I_C1 = 10 mA

            ΔI_C = (20 − 10) 10⁻³ = 10 mA

            ΔI_B = (200−100) 10⁻⁶ = 100 μA

Current gain of common emitter transistor

Determination of the Output Resistance R_out = 1/h_oe of the Transistor

R_out is defined as the slope of V_CE versus I_C characteristic for a constant I_B.

Thus,

So,

Assuming the following data from common emitter transistor output characteristics, output conductance and output resistance are calculated as given below.

g_m is by definition

As

3.3 Common Base Mode Transistor

In common base transistor configuration, base terminal is grounded and forms the common terminal for both input and output ports. Thus, when the base terminal of the transistor (BJT) is common to both the input and output ports, the mode of operation of the transistor is called the common base mode of operation as shown in Fig. 3.16.

For the transistor to be in the active region of its output characteristics, it requires that the emitter junction, the input junction, that is, the emitter-base junction is to be forward biased by V_EB and the output or collector-base junction is reverse biased by V_CB as shown in the Fig. 3.16.

As seen from the Fig. 3.16 the input current is the emitter current I_E and the output current is the collector current I_C. The current through the base lead is I_B and |I_B| = |I_E – I_C |. The current gain α of the common base operated transistor is defined as the ratio of the change in collector current ∆I_C to the change in emitter current ∆I_E with constant collector to base voltage V_CB.

Current gain

Current gain

Since the emitter current is greater than the collector current, the current gain of common base operated transistor is always less than unity and as the difference in magnitude between the emitter and collector current (I_E – I_C = I_B) is very small, the current gain α (alpha) of the common base transistor is less than one and always close to unity.

Input Characteristics of CB Transistor

For any transistor configuration, whether it is common emitter (CE) configuration or common collector (CC) configuration or common base (CB) configuration; the input and the output characteristics are drawn between voltage and currents. For the input characteristics, the output voltage is kept constant. For the output characteristics the input current is kept constant.

The input characteristics of common base (CB) transistor are thus between V_EB and I_E; the input voltage and current variations maintaining constant V_CB, the reverse bias to the collector junction. The experimental setup to obtain the data for input and output characteristics is shown in the Fig. 3.16 and the input and output characteristics are shown in Figures 3.17 and 3.18, respectively.

The input characteristic of any transistor configuration is similar to a forward biased diode. The input characteristic of this common base transistor is nothing but that of the forward biased emitter-base diode. For a given V_CB, as V_EB increases, beyond the cut-in voltage V_γ the emitter current I_E increases just like in a forward biased diode as shown in the Fig. 3.17. After passing the cut-in voltage, V_γ, for small changes of V_EB, large changes of I_E occurs.

For a constant V_EB, the increasing reverse bias voltage, V_CB can increase the emitter current I_E.; when the early effect comes into play. So, the knee voltage or the cut-in voltage or the threshold voltage for conduction of the emitter diode, lowers and large changes in I_E can be obtained at lower V_EB. This can be seen on the input characteristics that for a higher value of V_CB2; the characteristic moves to the left of V_CB1 characteristic. Due to base width modulation or early effect, when V_CB is more I_E increases due to increased field at the collector junction and it requires less V_EB to draw the same emitter current I_E and thus the curve for V_CB2 moves to the left of that for V_CB1.

The slope of V_EB versus I_E characteristic (input characteristic) is the input resistance represented by h_ib of the common base operated transistor. The input resistance of the common base transistor is defined as following:

The input resistance h_ib will be of the order of a few ohms, that is, about 10 to 20 ohms. This is very low when compared to the input resistance h_ie of CE transistor, which is typically 1 KΩ. The reason for this difference in magnitudes of the input resistances is clear from the following equation:

Since I_B, the base current is a few orders less than the emitter current I_E; the input resistance h_ib of common base transistor is so many orders less than h_ie. Also, the magnitudes of I_E and I_B in the expressions for the input resistances of the common emitter and common base configurations of the transistor confirm the same.

Output Characteristics of Common Base Transistor

For a given magnitude of emitter current I_E the graph between the output parameters, the collector current I_C and V_CB is called the output characteristic and a family of output characteristics are obtained for different values of I_E as shown in the following Fig. 3.18.

It is already familiar that for a given emitter current I_E; the forward biased input junction, a small current I_B goes to the base and the remaining current goes to the collector as the collector current I_C; according to the equation I_E = – (I_B + I_C).

The region between the output characteristic for I_E1 = 0 mA and V_CB axis on the CB transistor output characteristics is the cut-off region. The magnitude of collector current is I_CB0 which is negligibly small, that is, of the order of a few nanoamperes for silicon device and is of the order of a few microamperes for a germanium device under the situation of reverse bias to collector junction. The output characteristics resemble the reverse biased diode characteristic with reorientation of the quadrant of appearance and the parameters.

When the collector terminal is open, the entire emitter current I_E goes to the base and the collector current I_C = 0. When V_CB is zero, the electrons (for N-P-N Transistor) that cross the base region face a field at collector-to-base junction J₂ that neither opposes nor aids the electrons will allow all the electrons to continue their journey into the collector circuit and the collector current I_C for a given emitter current I_E becomes maximum even at the starting point of the characteristic, that is, for V_CB = 0 volts.

Now, if V_CB increases, the base width modulation occurs and a very slight increase in the collector current I_C is observed. The reason for this virtually constant I_C with variations in V_CB is that the electrons with reverse bias at the collector face an accelerating potential and they move with constant velocities or experience acceleration but the quantum of collector current I_C changes by a very little magnitude.

The relation between the collector current and the emitter current is defined according to the following equation

 

where I_C0 is the reverse saturation current which is ≅ 0 with I_E = 0 mA

α is called as the forward current gain of common base transistor.

As compared to the CE transistor configuration, the phenomenon of early effect is less prominent in CB transistor operation, since the forward current gain alpha α is less than unity and change in collector current I_C is negligibly small.

The slope of the collector current I_C versus V_CB characteristic (output characteristic) is almost zero and hence the output impedance of the CB transistor runs into megaohms.

Grounding of the base terminal produces perfect isolation between the input and the output ports, since it acts as a shield between emitter and collector and there is no common path between the two ports. In other words, the emitter to collector inter electrode capacitance virtually becomes zero.

The very low input impedance of the transistor CB configuration makes it unsuitable to be driven by non-ideal voltage sources (whose source impedance is not negligible). All practical voltage sources are non-ideal. But this common base mode transistor can be used with current sources, but natural current sources are rare and so the common base configuration finds less practical application.

The use of common base transistor in high frequency applications is appreciable because of its ability to provide perfect isolation between the input and output ports of the transistor.

3.4 High Frequency Linear Models

As the common emitter circuit is the most important practical configuration, common emitter transistor model valid at high frequencies is discussed. The circuit is very accurate and is called hybrid-π or Giacoletto model as shown in the Fig. 3.19. The circuit is applicable for both low and high frequencies.

Hybrid- π or Giacoletto Model

Analysis of circuits using this hybrid-π model is not too difficult and gives results, which are in excellent agreement with experiment at all frequencies for which the transistor gives reasonable amplification. All parameters (resistances and capacitances) in this model are assumed to be independent of frequency.

Elements of the Model

 

rbb′:	The internal point (B′) is the effective base point. rbb′ is the base spreading resistance between the external base terminal B and B′. The magnitude of rbb′ is of the order of 100 ohms.
rb′e:	The resistance rb′e represents the resistance of the forward biased base to emitter junction, the emitter junction of the transistor.
Cb′e:	The capacitance Ce or Cb′e is placed in parallel with rb′e to account for the input junction, that is, the emitter junction diffusion capacitance accounting for the excess minority carrier storage in the base. This is the capacitance of the emitter to base forward biased junction.
rb′c:	It represents the resistance of the reverse biased collector to base junction.
Cb′c or Cc:	It represents the capacitance of the reverse biased collector to base junction. (Also known as the output junction or the collector junction capacitance.)
gm Vb′e:	Small changes in the voltage Vb′e across the emitter junction finally results in small signal collector current gmVb′e. This effect is accounted as current generator gmVb′e (when collector is shorted to emitter) as shown in Fig. 3.19.
rce, = 1 /gce:	The conductance between C and E is gce.

Some typical hybrid-π parameter values of common emitter transistor at high frequencies:

 

gm	=	50 ma/v or 50,000 µΩ
rbb′	=	100 Ω
rb′e	=	1000 Ω
Cb′e	=	100 pf
rb′c	=	3 × 106 Ω
Cb′c	=	2 pf
rce	=	100,000 Ω

Determination of Hybrid- π Parameters

Manufacturers supply data that characterise the transistors. Usually, not all of the hybrid-π parameters are given. The determinations of hybrid-π parameters from the commonly published data or from quantities that can be easily determined are considered.

1. Determination of transconductance (g_m)

In the linear region for small signals, g_m is given by,

At temperature

Transconductance g_m can be easily found from the D.C. or Quiescent operating current I_CQ decided with the class of operation of amplifiers and the operating temperature T.

2. Determination of input conductance (g_b′e)   The hybrid-π model valid at low frequencies is shown in Fig. 3.19A, where all capacitances are negligible.

FIGURE 3.19A Hybrid-π equivalent circuit of transistor considered at low frequency

From the typical values of the circuit components of common emitter transistor at high frequencies, r_b′c >> r_b′e. Hence, I_b flows into r_b′e and hence V_b′e = r_b′e.I_b.

The short circuit collector current I_C is g_mV_b′_e.

Therefore,                    I_C = g_m.V_b′e = g_m.I_b.r_b′e

The short circuit current gain h_fe is defined by

Manufacturers usually specify ß_o = hf_e

3. Determination of r_bb′ From Fig. 3.19A, the input resistance with output shorted is h_ie.

Under these conditions r_b′e is in parallel with r_b′_c

∴                    r_b′e || r_b′C ≅ r_b′e since, r_b′C 〉〉 r_b′e

From Fig. 3.19A with output shorted

4. Determination of feedback conductance (g_b′c)   With the input open-circuited, h_re is defined as the reverse voltage gain with I_b = 0.

∴                        h_re.(r_b′c + r_b′e) = r_b′e

∴                                   h_re.r_b′c = rb′e(1 − h_re)

Since                        h_re ≅ 10⁻⁴ that is, h_re 〈〈 1, Then, (1 − h_re) ≅ 1

Therefore,              h_re.r_b′c = r_b′e

When which means that r_b′c 〉〉 r_b′e that is, r_b′c will have a magnitude of the order of megaohms.

5. Determination of output conductance (g_ce)   With the input open-circuited, the conductance is defined as h_oe for I_b = 0

With I_b = 0; V_b′e = h_reV_ce. Substituting this in the above equation

As r_b′c 〉〉 r_b′e  ∴ (r_b′c + r_b′E) ≅ r_b′c

using g_m = g_b′e .h_re from equation (3.25) in the above equation,

 

using in the above equation,

∴	hoe = gce + gb′c + hfe.gb′c
∴	hoe = gce + gb′c (1 + hfe) ≡ gce + gb′c.hfe
∴	gce = hoe − hfe.gb′c
Also,	hoe = gce + gb−c + gm.hre
and as
i.e.	goe = hoe − gm.hre                                    (3.28)

6. Determination of C_b′c   The value of the capacitance of the reverse biased collector-to-base function C_ob is often specified in the manufacture’s transistor’s data. C_b’_c = C_ob is the capacitance measured between the collector and base leads with the emitter lead open circuited (for signal frequencies) C_b’_c = C_ob.

7. Determination of C_b′e or C_e   Experimentally C_b′e is determined from a measurement of F_T, the frequency at which the common emitter short circuit current gain drops to unity.

Validity of Hybrid-π Model

The hybrid-π model is valid under dynamic conditions, when the rate of change of V_be is small enough so that the base incremental current ∆I_b is also small. It was also proved that the hybrid-π model is valid for frequencies up to approximately where f_T is the frequency at which current gain of an amplifier is unity. f_T is also known as unity gain frequency. f_T incidentally is the gain-bandwidth product of an amplifier, that will be explained more later.

Example A junction transistor is to operate at the following operating point I_CQ = 2 mA, V_CEQ = 20v and I_BQ = 20μA. The following values for this operating point are the specifications of the transistor. ß_O = 100; f_T = 50 MHz; C_0b = 3 pf; h_ie = 1.4 KΩ; h_re = 2.5 × 10⁻⁴; h_0e = 25 μ mhos. Determine the hybrid-π model parameters of the transistor. Assume that the operating temperature is 300 K.

Solution

1.  

   
2. 
3. r_bb′ = h_ie − r_b′e = 1400 − 1300 = 100 ohms
4. 

5.  

   
6. C_b′c = C_ob = 3.pf
7. 

3.5 Field Effect Transistor

While a transistor (BJT-bipolar junction transistor) is a bipolar device and basically a current-operated device, a junction field effect transistor (JFET or simply FET) as the name itself suggests is a voltage-operated device. These terms are derived from the device operations. These terms indicate the basic difference between BJTs and FETs.

The control electrode current is high with the forward biased input junction of BJT, whereas, the input electrode current of FET devices is negligibly small. The transistor has another disadvantage that its input impedance is low and requires ideal voltage sources for driving it. The other alternative is to use a buffer amplifier in the form of emitter follower as an impedance matching network.

The JFET is basically reverse biased at the input port and has theoretically infinite input impedance. Thus, it acts as an ideal front end connecting circuit in practical applications. The currents through the field effect transistor are due to the movement of majority carriers. Hence, the FET is a unipolar device and a voltage variable resistance made to operate as an amplifier.

When, very high input resistance amplifier stage is to be designed, FET amplifier stage is preferred over bipolar transistor amplifier stage.

Transistors are nonlinear devices as evident from the device characteristics. Transistor operation is considered as linear for small signal operations of amplifiers.

There are two types of FETs. The JFETs also called Junction gate FET and the MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are also called Insulated Gate FET (IGFET) from the structure and functioning of MOSFET devices as seen further.

As mentioned earlier, the field effect transistor (FET) is unipolar and has only one type of current carriers, the majority carriers for electrical conduction of the device. If the current carriers are electrons FET is called an N-Channel JFET. The complement of this is P-Channel JFET having holes as current carriers. The schematic symbols of N-Channel FET and P-Channel FET are shown in Fig. 3.20. The arrow head on gate electrode indicates the direction of current when the gate-source junction is forward biased.)

Just like a transistor, FET device also has three terminals the source, the gate and the drain (similar to emitter, base and collector electrodes of a transistor). But in a FET, the source and drain are interchangeable as opposed to the transistor device, where, the emitter and collector cannot be interchanged.

In FET devices, there are no separate input and output junctions as in the case of transistors. N-channel FET has N-type semiconductor bar. Drain terminal is at the upper end and source terminal is at lower end of the N-type bar. Here, between drain and source, an N-channel exists, which is called a channel. As is shown in Fig. 3.21, on the other two sides of the N-type of semiconductor slab, P-materials are formed and these two P-material sides are joined together to form the gate electrode.

Thus, on two sides of the slab, there are P-N junctions, though the two P-regions are joined together to form one electrode, the gate. Voltage V_GS or V_GG is connected between gate and source of N-Channel field effect transistor with negative of the voltage source connected to the gate electrode and positive to the source terminal. The two P-N Junctions between the gate and the source are thus reverse biased by the D.C. voltage V_GS or V_GG. The gate of the N-Channel FET device draws negligible current, that is I_G = 0. So, FET is a voltage-controlled device.

D.C. voltage V_DS or V_DD is connected between the drain and the source terminals of the FET device. The majority carriers in the N-channel JFET device are electrons and the active output terminal is the drain. The positive of the D.C. voltage source V_DS or V_DD is connected to the drain terminal and the negative of the D.C. source is connected to the source terminal as shown in the Fig. 3.21. Electrons flow from drain to source in the output circuit between drain and the source for various values of V_DS. The conventional drain current I_D flows from the positive terminal of V_DS or V_DD through the device from the drain to the source and then completes the path to the negative terminal of V_DS as shown in the Fig. 3.21.

Initially, when V_GS = 0 volts and V_DS = 0 volts, the depletion region widths (of unbiased junctions) about the junctions are uniform. With the increases in voltages, V_DS for different constant values of V_GS, the situation is that the reverse bias is more towards drain end than the source end at the two P-N junctions in the device (the varying magnitudes of the reverse biases is due to the flow of the drain current I_D through the device channel across increased areas of cross-sections of the channel from the source to the drain, thus producing different voltage drops across the channel). These varying reverse biases cause varying magnitudes of depletion region widths about the two junctions. Increased reverse bias magnitudes from source to drain cause increased depletion region widths towards the drain as shown in the Fig. 3.21.

With the drain shorted to the source and a negative voltage applied between gate and source two reverse biased junctions appear on both sides of the gate and depletion regions spread into the slab. As the reverse voltage increases, the conducting area of the channel is reduced. The drain current decreases with increasing reverse bias and when it is high enough the channel virtually closes and small reverse current flows. This is the condition when I_D is almost zero and the channel is pinched off (cut off with V_DS = 0 volts).

3.6 FET Characteristics

Using the experimental setup of Fig. 3.21A; the basic properties of a typical FET are illustrated by the device characteristics as shown in the Fig. 3.22.

Output characteristics of the FET device are between the drain to source voltage V_DS and drain current I_D for a set of constant gate to source voltages V_GS. Initially, voltage V_GS is kept at zero volts. It is kept constant. Then varying the voltage V_DS in increments, the corresponding incremental values of I_D are tabulated. A family of output characteristics is obtained for a set of gate to source voltages V_GS as shown in the Fig. 3.22. The drain resistance r_d can be calculated from the output characteristics in the pinch-off region.

Transfer characteristics of the FET device are between the gate to source voltage V_GS and the drain current I_D for a set of constant drain to source voltages V_DS. Initially, V_DS is kept constant, say, at 10 volts. Varying gate to source voltages V_GS from 0 to the pinch-off voltage V_P (V_GS off) of the device in increments (V_P is gate voltage when the drain current I_D becomes zero), corresponding increments of drain current I_D are tabulated. This procedure may be repeated for another constant voltage V_DS to obtain another transfer characteristic. The transfer characteristic is drawn as shown in the Fig. 3.26. The Transconductance g_m can be calculated from the transfer characteristics.

The amplification factor μ also can be determined from the output characteristics or as the product of g_m and r_d (μ = g_m·r_d). These device parameters are defined later. The maximum gain of FET amplifiers is decided by the maximum value of the amplification factor of the device.

Discussion on the Output Characteristics of FET

V_GS is maintained constant at certain values (for example V_GS = 0 volts) as shown in the Fig. 3.22. At each constant value of V_GS, as V_DS is increased up to a few volts drain current I_D linearly increases from the origin 0 to A the majority carrier electrons flow from source to drain through the N- type channel and then complete their path through the drain circuit. The channel resistance is uniform and acts as a semiconductor resistor. The channel resistance limits the current. The resistance increases with V_DS as shown on the output characteristics of the FET device in the Fig. 3.22. This region from 0 to A on the output characteristics is known as Ohmic region.

For each , where r_d is the drain resistance. In this region of operation, the FET device behaves like a voltage variable resistor (VVR) or voltage dependent resistor (VDR).

For higher values of V_DS, the channel resistance becomes non-uniform, during the region A to B on the output characteristic, since the depletion region width changes along the length of the channel from source to drain as shown in the Fig. 3.21. This region is known as Nonlinear region.

At the source end, the depletion region width is minimum and at the drain end it is maximum, because of varying reverse bias voltages (due to varying voltage drops between the source and the drain along the channel region due to the flow of the drain current I_D) at the gate-source and gate-drain junctions, respectively that can be seen from the Fig. 3.21. Thus, for each V_GS on the drain characteristics, with increasing values of V_DS, the magnitudes of the drain current I_D increases up to a drain to source voltage V_DSP simply known as the pinch-off voltage V_P. The drain current starts raising slowly and finally reaches a constant value or I_D reaches a saturation value, (where the depletion region widths come closer, but never overlap for the prevention of disappearance of reverse bias to maintain the device operation) above the knee portion from the pinch-off voltage V_P as shown in the Fig. 3.22. The region B to C on the output characteristic is the Pinch-off region, the active region for amplifier operation.

When V_GS = 0 v, I_D will be maximum ever that is reached and it is called drain saturation current I_DSS. This is also clear from the following equation.

The relation between I_D, I_DSS, V_GS and V_P is given by Shockley’s equation:

For a given V_GS, V_DS versus I_D characteristics (output characteristics) have four regions.

1. Linear region from 0 to A on the output characteristic of the JFET device is known as (voltage dependent resistor, VDR) VDR region or simply Ohmic region.

2. The knee portion from A to B on the JFET output characteristic, in which the device resistance suddenly changes from a low value to a high value exhibits a nonlinear behaviour. This is called as the Nonlinear region.

3. From B to C portion of the JFET output characteristic, the curve is almost parallel to the X-axis (indicating the saturated or constant values of drain current I_D) and is known as the Pinch-Off region and the characteristic in this region exhibits a high resistance of the order of a few hundred kilo ohms and it is called as (one of the FET device parameters or constants) drain resistance r_d. This device internal resistance is used in the representation of the small signal A.C. equivalent circuit for the analysis of the FET amplifier operation. The pinch-off region also suggests the voltage controlled current source (V C C S) behaviour of the device in practical circuit applications.

4. Beyond the point C, when the voltage V_DS becomes large enough to breakdown the junction causing a sudden high rise of drain current, I_D. This Breakdown region is never used in practice and so it is not shown on the output characteristics of JFET device.

Determination of the Drain Resistance r_d and the Amplification Factor μ   The three FET device constants are transconductance g_m, drain resistance r_d and the amplification factor μ. The following are the definitions with the relation between them.

Transconductance,

Drain Resistance,

Amplification factor

From these definitions…

The drain resistance r_d can be calculated from the JFET output or drain characteristics. Drain resistance is the inverse of the slope of the output characteristic. Drain resistance is the ratio of the increment in drain to source voltage ∆V_DS between V_DS2 and V_DS1 and the corresponding increment in the drain current ∆I_D between I_D2 and I_D1 that are obtained from the graphs. From the characteristics in the Fig. 3.26, it is clear that large change in the drain to source voltage produces a small change in the drain current.

The drain resistance r_d is calculated as the ratio of ∆V_DS = [(V_DS2 – V_DS1)] = 20 – 4 = 16 volts to ∆I_D = [I_D2 – I_D1] = 10 – 9.5 = 0.5 mA. So, the drain resistance r_d is equal to 32 kilo-ohms.

Transfer Characteristics of the Field Effect Transistor (JFET) (Determination of Transconductance g_m)   With the voltage V_DS across drain and source electrodes of the JFET device kept constant, if V_GS is varied from zero to higher negative values, the drain current I_D drops from the drain saturation current I_DSS to reach almost zero, when V_GS is large enough to close the channel at a voltage V_P known as V_{GS off} (pinch-off voltage). The device parameters I_D, I_DSS, V_GS and the pinch-off voltage V_P are related by Shockley’s expression,

Differentiating the above equation with respect to V_GS; expression for g_m can be obtained as following,

using the relation

When V_GS = V_p, that is V_as off, I_D becomes zero (however, some authors indiscriminately use this V_{GS off} as pinch-off), according to the mathematical expression 3.34. This variation of drain current with variations in V_GS for constant value of V_DS is shown on the following transfer or mutual characteristics of Fig. 3.26. This characteristic is a nonlinear characteristic as evident from Shockley’s equation 3.34.

The mutual or transfer conductance g_m can be calculated from the transfer characteristic or output characteristic of the JFET device.

From the transfer characteristics in Fig. 3.26, the transconductance g_m can be determined as the ratio of the increment ∆I_D, that is the change in drain current from I_D1 to I_{D 2} which is 5 mA from the graph and the increment in gate voltage ∆V_GS that is change in gate voltage from V_GS1 to V_GS2 which is 2 volts. So, g_m is equal to 2.5 milli mhos or milli Siemens. Transconductance is the slope of the transfer characteristic of the FET device.

The amplification factor μ is the product of g_m and r_d from the definitions of the device constants, as shown previously. In these calculations r_d = 32 × 10³ ohms and g_m = 2.5 milli mhos. Therefore, the amplification factor μ = g_m.r_d = 32 × 10³ × 2.5 × 10⁻³ = 80. These values for the device constants are only for the sake of illustration of the method of calculations. It can be seen later that maximum gain of a JFET amplifier is limited to the value of amplification factor, μ of the device.

The square law nature of the device transfer characteristic suggests its use in mixer circuits of radio receivers circuits. Once, we know the FET structure, device working and the device parameters, the device application as an amplifier is considered for simple illustration of application of the FET device.

3.7 N-channel FET as an Amplifier

Like a bipolar junction transistor (BJT), a junction field effect transistor JFET is used in amplifier circuits. Amplifier circuits are broadly (1) voltage amplifiers that are small signal amplifiers and (2) power amplifiers that are large signal amplifiers. Consider basic operation of the JFET device as a voltage amplifier using the following circuit in the Fig. 3.27.

Consider the public address system microphone converts the speech or music, that is, the sound energy into electrical signal. Microphone is a transducer that converts the sound energy into electrical signal. Voltage and power amplifiers amplify the electrical signal from the microphone, before the signal is fed to a loud speaker. The speaker converts the amplified electrical signal back into sound energy. The speaker is a transducer that converts electrical signal into sound energy. This amplified sound from the speaker is used practically. This process is discussed in the chapter for amplifier with circuits.

So, amplifiers consider the input and output A.C. signals for amplification. Now, consider the JFET amplifier a small signal amplifier as in Fig. 3.27.

In the basic amplifier circuit shown in the Fig. 3.27, both the D.C. voltages are (1) gate supply voltage or gate to source bias voltage V_GG used to set the D.C. voltage V_GS (based on the type of the amplifier and its class of operation) and (2) drain supply voltage V_DD so as to set the drain current (output current) I_D flowing through the FET device to a value such that the voltage across the load resistance R_L = I_D.R_L = V_RL is about half the supply voltage V_DD to satisfy the Class A operation of the amplifier.

The bias (D.C. voltage) V_GG is arranged such that the gate of the N-Channel FET is made negative relative to the source, because the requirement is that gate-channel junction of the N-Channel FET is to be reverse biased so that the input resistance R_in of the FET device is very large, which is an advantage over the BJT devices and facilitates non-ideal driving voltage amplifiers.

The gate-source voltage V_GS is established by the bias voltage V_GG as shown in the basic amplifier circuit of Fig. 3.27. Because there may be a gate current of only of the order of a few nanoamperes, the voltage across the gate resistor R_G (1 × 10⁻⁹ × 1 × 10⁶ =10⁻³ volt) negligibly small and the gate-source voltage V_GS is virtually the same as −2 volts. For class A operation of the amplifier. V_GS = (1/2). V_p.

Assume the following output characteristics (static characteristics) for the JFET device as shown in Fig. 3.28.

The output characteristics of the device can be obtained experimentally or by a curve tracer using a cathode ray oscilloscope. When the JFET device is biased with voltages for the required class of operation of the amplifier, steady state values of the drain current I_D and the voltage V_DS are related by D.C. load line equation for the amplifier analysis.

Obtaining the D.C. equivalent circuit of the amplifier circuit in Fig. 3.27, the D.C. load line equation can be written as the following (discussed in detail in the amplifier chapter).

 

The coordinates of the point (X) of the D.C. load line are V_DS = 0 volts and I_D = (V_DD / R_L) and the coordinates of the point (Y) of the line are V_DS = V_DD volts and I_D = 0 mA. The D.C. load line can be drawn by joining the two points (X) and (Y).

The drain current I_DQ and the voltage V_DSQ are obtained by superimposing the D.C. load line on the output characteristics for the required quiescent point operation of the amplifier. If an input signal voltage source, V_in = V_m. sin wt is applied at the input port of the amplifier large variations in I_D flowing through the load resistance R_L develop the output voltage V_out at the output port. It can be observed that the output voltage will be much greater than the input signal voltage and signal amplification takes place. Gain A of the amplifier is the ratio of the output voltage V_out to the input voltage V_in, provided the voltage gain A is greater than unity.

Comparison between Field Effect Transistor (FET) and Transistor (BJT)

Junction Field Effect Transistor	Bipolar Junction Transistor
Device currents are due to the movement of only one type of majority charge carriers. Electrons in N- Channel FET device or holes in P-Channel FET devices.	Transistor currents are due to the movements of both the majority and minority charge carriers in both N-P-N and P-N-P transistors.
The input junction between the gate and the source is reverse biased and hence the input resistance of the FET device is very large. This high input resistance of the FET device is an advantage over transistor devices.	The emitter or the input junction of the transistor is forward biased and hence the input resistance is very low.
The input signals voltage magnitudes between gate and source control the current through the device. So, it is a voltage controlled current source.	The input current base current controls the collector current for device operation. It is a current controlled current source.
Voltage gain is limited to the amplification factor μ of the device, which has low values. So, the amplifier circuits using FET devices have low orders of gain and hence the band width of FET amplifiers are large.	The amplifier circuits using transistors have large values of current and voltage gains. So, the bandwidth of transistor amplifiers are low.
Low noise level.	Noise level is very high.

3.8 Metal Oxide Semiconductor FET (MOSFET)

Two types of MOSFET are available

1. Enchancent mode MOSFET or E-MOSFET

   (MOSFET with induced channel)

    

2. Depletion Enhancement modes MOSFET.

   (DE MOSFET or MOSFET with built-in channel)

Integrated circuit (IC) technology has revolutionised the semiconductor devices and RLC components fabrication or manufacture in batch processing with small size, and at low cost and phenomenal reduction in size and increase in packaging densities is achieved. Reliability of working is increased, resulting in improved performance.

A silicon wafer of 1 sq. inch size can accommodate up to 400 IC chips of surface area 50 mil by 50 mil. Each chip again can contain 50 separate components to make up 20,000 components in a single wafer. If 10 wafers are used in a single batch processing 2,00,000 components can be manufactured.

Like the JFET, the MOSFET is a lower-power semiconductor device that has high input impedance as first generation electron devices or vacuum tubes and low power requirements of transistors. Both MOSFETs and JFETs have drain, source and gate electrodes in common. Both devices have conduction channel with its resistance controlled by gate to source voltages. There are also P and N-type channel MOSFETs; complementary MOSFETs known as CMOs. FET devices use both. The gate-source path in a JFET is a reverse biased junction by V_GS. In a MOSFET, a thin layer of insulating material such as SiO₂ is placed over the channel region before the fabrication of the gate electrode. The insulating layer is very thin, which is of the order less than 1 μm. the field produced by gate voltage still penetrates through insulating layer and modulates the conduction of the channel. The input resistance of MOSFET is much higher than that for JFET because of the SiO₂ insulation layer between gate and the channel. Input resistance of MOSFET is of the order of 10¹⁴ ohms. Since there is an insulator in the input circuit of a MOSFET, the gate potential is not restricted in polarity. There are therefore, two possible modes of operation for MOSFETs. As mentioned earlier, the non-restriction on polarities of gate voltage, enhancement mode and depletion mode of operations are possible.

Manufacturing Process of MOSFET

Considering the fabrication details of the enhancement MOSFET (MOSFET with induced N-type channel) the following steps are involved. The basic MOSFET with N-type channel is formed on a P-type silicon wafer substrate. The source and drain of the MOSFET device with N-type induced channel are N-type islands that are formed or diffused into a lightly doped P-type substrate. Aluminum metal on SiO₂ layer (on the substrate) functions as the gate electrode. Thus, the insulating SiO₂ layer separates the gate and the conducting (induced) N-type channel. With these basic construction features of the MOSFET device, the device is also known as insulated gate field effect transistor (IGFET).

Step-1   The starting material is a P-type substance or wafer upon which an insulating layer of silicon dioxide SiO₂ is grown in the following second step.

Step-2   Upon P-type substrate, SiO₂ layer is grown as shown in the following Fig. 3.30

SiO₂ layer is experimentally grown over the P-type substrate. SiO₂ (silicon dioxide) material that has the fundamental property of preventing the diffusion of impurities through it. SiO₂ layer thickness is of 0.5 μm (5000Å).

Step-3   Kodak Photo Resist material (KPR) is coated on the SiO₂ layer as shown in Fig. 3.31.

To perform photolithography-etching process over SiO₂ layer to provide two windows for the formation of two islands of N-type material, Kodak Photo Resist material (KPR) is coated over SiO₂ layer (KPR is also known as photosensitive material.)

Step-4   A high-resolution photo mask with painted regions at locations 1 and 2 is placed on SiO₂ layer as shown in Fig. 3.32.

A very high-resolution photo mask with two painted regions at 1 and 2 locations over it is placed on the silicon wafers as shown in Fig. 3.32. The painted regions will not allow ultra violet light (UVL) to pass through them (the number of painted areas corresponds to the number of windows and islands to be formed for the device or the circuit component). In this MOSFET device two windows are needed for source and drain island regions, so there are two painted areas on the photo -mask.

Step-5   The photo mask is exposed to ultra violet light radiation as shown in Fig. 3.33.

The photo mask is exposed to ultra violet light (UVL) as shown in Fig. 3.33.

UVL does not pass through the painted regions 1 and 2. UVL passes through the mask over the unpainted areas on 3,4 and 5. KPR over SiO₂ layer gets polymerised over the exposed areas for UVL. The KPR over SiO₂ in regions 1 and 2 remains as in original situation and are dissolved by using etching solutions easily.

Step-6   Etching process for the formation of two windows at regions 1 and 2 in Fig. 3.34.

Regions 3,4 and 5 on SiO₂ layer get polymerised and cannot be dissolved by etching solution. Regions 1 and 2 on SiO₂ layer are not polymerised. So, using etching solution, regions 1 and 2 of SiO₂ are etched away and two windows are formed and P-type substrate regions are exposed at the two windows areas to facilitate pentavalent material diffusion through them for the formation of N-Type of islands.

Step-7   N-type diffusions through the two windows to form source and drain.

Through the two windows Pentavalent impurity atoms of phosphorus material are diffused into the dotted window areas and two N- type islands are formed.

Step-8   Formations of N- type source and drain islands.

N-type island-1 is used to function as source. N-type Island-2 is used to function as drain.

Aluminum metallisations are formed to form gate, source and drain electrodes of MOSFET device. There are frequently other processing steps that involve re-oxidation and further etching to fabricate the total device. Thus, the silicon dioxide (SiO₂) layer between the induced channel connecting the drain and the source and the gate functions as an insulator. That is the reason why the MOSFET device is also called as Insulated Gate Field Effect Transistor.

Step-9   Structural details of the MOSFET(IGFET) device are shown in Fig. 3.37.

The source, drain and gate electrode materials are formed to function as enhancement MOSFET (IGFET) by applying suitable voltages V_DD or V_DS and V_GS as shown in Fig. 3.38.

Step-10   MOSFET with the biasing voltages shown in the Fig. 3.38.

Basically, the voltages V_DD or V_DS and V_GS are the D.C. voltages for the operation of the enhancement MOSFET device with both biasing voltages positive with respect to the source.

(The enhancement-mode MOSFET device is also known as normally off MOSFET). The positive charges (+ V_GS) on the metallic gate induce corresponding negative charges in the channel in the P-type material between the source and the drain on the other side of the SiO₂ layer, just as in a capacitor (aluminum metal of gate and P-type substrate with SiO₂ insulating layer as dielectric contribute to capacitor action to induce negative charges in the channel between source and the drain in the P-type substrate material). As the control of the drain current due to mobile electrons through the N-type channel is at the surface of the P-type semiconductor, the device is also known as Surface Field Effect Transistor.

Step-11   Induced channel formation for the mosfet device working.

With enough positive bias voltage, V_GS, the electron enhancement will be sufficient to convert the P-region under the gate to an N-type channel. So, the formation of the induced channel connects the source and the drain islands, so that a conduction channel operates the device. Drain to source voltage V_DS causes current flow I_D due to the flow of induced electrons along the channel from the drain to source. (Induced channel exists only during device operation).

From the transfer characteristic between the parameters V_GS and I_D of the MOSFET shown in Fig. 3.40, it can be observed that a minimum gate to source voltage V_GST or V_TH is required to induce mobile electrons and form a channel between the source and the drain to establish current flow between the two N-Type of islands. This minimum voltage V_TH is known as the threshold voltage for the MOSFET. The current I_DSS is very small and is of the order of a few microamperes that can be known from the device specifications at the specified threshold voltage V_TH or V_GST. Varying gate to source voltages V_GS control the induced mobile electrons into the channel and thus vary the conductance of the induced channel.

The increasing positive voltages on the gate electrode enhance the conduction electrons in the N-type channel and in turn enhance the magnitudes of the drain current I_D. So, the device is called as enhancement mode MOSFET or simply E-MOSFET.

For this enhancement MOSFET, as long as the gate-to-source voltage is less than the specified threshold voltage V_TH; the MOSFET is normally in the off condition or OFF-state. Once the positive voltage sufficiently exceeds the threshold voltage V_TH, N-type channel is induced and the device switches into the conduction or the ON-state. These binary states of switching of the normally off MOSFET device have good number of applications in digital electronic circuits. The additional feature of isolation or insulation of gate from the source and the drain regions provides infinite input impedance for the device, as the gate current is negligibly small.

The device parameters, the drain current I_D, V_GS and V_TH are connected by the following mathematical expression,

 

where, the value of the constant K depends on the device geometry details. K has the units of mA /(volt)² and typical value of 0.3 is common.

From this equation for the drain current relating the threshold voltage, it is also clear that the device geometry parameter K has a control on the threshold voltage. In practical digital circuits, the magnitudes of ON voltages depend upon the applications. So, the ON-state voltage of the MOSFET device that is dependent upon the threshold voltage V_TH is in turn decided by the design constraints on the MOSFET device to provide a suitable threshold voltage for the desired practical applications.

Output Characteristics for an N-Channel Enhancement Mode MOSFET   Output characteristics of MOSFET device are graphs of the drain current I_D that will flow as V_DS is varied for a number of values of V_GS.

For an enhancement mode MOSFET, I_D = 0 for V_GS = 0 volts and hence it almost touches the V_DS - axis. The device characteristics are similar to JFET device output characteristics.

As V_DS is increased, initially I_D increases till knee points on the output characteristics and beyond knee points drain current I_D remains almost constant, even if V_DS is increased. So, in the constant current regions, the output impedance of the MOSFET device is very high.

Depletion Enhancement MOSFET (DE MOSFET) (MOSFET with Built- in channel)   A channel with charges corresponding to majority carriers of source and drain semiconductor materials is diffused between source and drain to form the built-in channel.

DE MOSFET or depletion-mode MOSFET is also known as a normally ON MOSFET, because with zero gate to source voltage V_GS, the two N-type islands, the drain and the source are connected by N-channel.

Negative charges or voltage –V_GS on the metallised gate induce corresponding positive charges in the N-channel on the other side of SiO₂ layer. The induced positive charges may also be thought of as repelling negative charges in the N-channel, with a consequent reduction in the conductivity of N-channel for depletion mode of operation of the device.

In addition to being operated as depletion-mode device, DE MOSFET can also be operated as an enhancement device. Positive gate voltages V_GS induce negative charges into the already built-in N-type channel. This enhances the channel conductivity, resulting in more drain current, I_D by applying V_DS.

The enhancement mode and the depletion mode characteristics of the DE MOSFET are shown in the Fig. 3.43.

3.9 Unijunction transistor

UJT was first introduced in 1948 and is commercially available since 1952.

The unijunction transistor (UJT) or P-N transistor is a two-layer P-N device with three terminals known as emitter, base-1 (B₁) and base-2 (B₂). Similar to the bipolar junction transistor, the UJT is fabricated on a lightly doped N-type silicon bar with ohmic contacts for the two base terminals B₁ and B₂ at the top and lower ends of the bar. The emitter section is a heavily doped P-type material that is deposited between the base B₁ and base B₂ regions, possessing only one P-N junction of small area as shown in the Fig. 3.46. As the device has only a single junction, it is known as a unijunction transistor.

The UJT device exhibits negative resistance characteristics as shown in Fig. 3.49. This means that an increase in emitter current results in a decrease of voltage between the emitter E and base B₁ terminals.

This negative resistance property of the device is made use of in relaxation oscillator circuits used as a time base voltage in cathode ray oscilloscope. It is also used to provide triggering voltages to SCR device control applications and timing circuits.

Emitter arrow shown on the circuit symbol is inclined towards base B₁. Pointing in the direction of conventional current (hole) flow when the emitter to base B₁ junction of the device is forward biased by the emitter voltage V_E.

The main operational difference between FET and UJT is that the gate surface of FET is much larger than the emitter junction of UJT. FET is normally operated with gate junction reverse biased, where useful behaviour of UJT occurs when the emitter is forward biased.

The structural details of UJT are shown in the Fig. 3.46. High resistively N-type silicon (lightly doped / increased resistance characteristic) of 8 × 10 × 35 mils called base B that has attached to its opposite (top and lower) ends two ohmic contacts base B₁ and base B₂. A 3-mil aluminium wire, called emitter E is alloyed to the base between base B₁ and base B₂ to form small area of a P-N rectifying junction. Unijunction transistor (UJT) was originally known as doublebase diode. Aluminium rod is alloyed to silicon semiconductor slab closer to base B₁ contact as shown in the Fig. 3.46.

UJT Circuit with Biasing Voltages

To obtain the UJT device characteristics and understand the working of the device, voltage, V_BB is applied between base B₁ and base B₂. Voltage V_EE is used to provide a voltage V_E that is applied between the Emitter E and the Base B₁ as shown in the Fig. 3.47. Maintaining a constant supply voltage of say 0 volts; varying the emitter voltages in increments, the corresponding value of emitter current I_E are noted down. The observations are tabulated. Observations are made for different constant values of V_BB = 5 volts, 10 volts, 15 volts and 20 volts. UJT characteristics can be drawn from the tabulated data. During the observations, the salient features such as peak voltage V_P, peak current I_P, valley voltage V_V, valley currents I_V, saturation voltage, and so on are noted down, keeping in view of the expected characteristic of the UJT device.

UJT Equivalent Circuit

Equivalent circuit of the UJT device in the Fig. 3.48 has two resistors R_B1 (variable resistance) and R_B2 (fixed resistance) that form a voltage divider during the operation of UJT and a single diode representing the P-N junction between the emitter and the base B₁. That is the reason why the device is called a unijunction transistor. R_B1 may vary from 5 KΩ to 50 Ω for a corresponding change of I_E from 0 to 50 milliamperes during the device operation.

The resistance R_B2 is a fixed internal resistance between the emitter and base-B₂. The resistance R_B1 is the internal variable resistance of the silicon bar between the emitter and base B₁ that depends on the operation or ON–OFF states of the UJT device. Inter electrode base resistance R_BB = R_B1 + R_B2 (I_E = 0), that is when V_E = 0 V. R_BB is typically in the range of 5 KΩ to 10 KΩ. The position of aluminium rod functioning as the emitter electrode will determine the relative values of R_B1 and R_B2 with I_E = 0.

Knowing η the intrinsic standoff ratio of the UJT device and the applied voltage V_BB across base terminals we can calculate voltage across R_B1.

where, η is called intrinsic standoff ratio, the main parameter of the UJT device.

Typical values of η have a range from about 0.5 to 0.8 for most UJTs.

Power dissipation = 300 mw; RMS I_E = 50 mA; Peak I_E = 2μA

Emitter reverse voltage = 30 V. Inter-base voltage= 35 V.

Principle of Working of the UJT Device

Initially, when V_BB is switched on, and the emitter voltage V_E = 0 volts; voltage across R_B1 will be of such a polarity that will reverse bias the P-N junction between the emitter and base B₁. Only reverse current I_E0 of the order of a few microamperes will be present through the device in the emitter circuit and the UJT device is in the off-state. The device is in the cut-off region of the characteristic shown in Fig. 3.49

For applied potential, V_EE; with increased voltages, when V_E is greater than V_RB1 = ηV_BB by the forward voltage drop across the diode V_D, (V_D = 0.35 to 0.7 volts, as UJT has silicon semiconductor bar); as shown in the Fig. 3.47 and 3.48; the diode (P-N junction between the emitter and base B1) is forward biased and the UJT will fire. Emitter current I_E will begin to flow through R_B1 in the emitter circuit due to the heavy injection of majority carrier holes from the emitter into base B1. The emitter firing potential V_P is given by V_P = ηV_BB + V_D

UJT characteristics for different values of V_BB are shown in the Fig. 3.50.

The UJT characteristics are shown in the Fig. 3.50 for V_BB = 5 V; 10 V; 20 V and 30 volts.

For emitter potential to the left of the peak point, the magnitude of I_E is never greater than I_Eo (μA). The current I_E0 corresponds very closely to the reverse leakage current I_C0 of the conventional bipolar transistor. UJT will be in the off-state during this operation and this region is called the cut-off region as shown in the Fig. 3.49.

Once the voltage V_E is greater than or equal to the peak voltage V_P; the emitter potential V_E will drop with increase in I_E. At this stage, the P-N junction between the emitter and base B₁ is forward biased. So, the emitter current I_E increases. This increase in the emitter current is due to the injection of a good number of majority carrier holes from the P-type emitter region into the semiconductor bar towards base B₁. This increase in conduction reduces the resistance R_B1 to a very small value, resulting in reduction of V_RB1. This forward biases the diode more and the process becomes cumulative resulting in regenerative action. The result is that for increased I_E, V_EB falls to ultimately reach V_V. From the peak voltage V_P to V_V, the UJT device exhibits negative resistance (after the peak point V_P up to the valley point, V_V the emitter current I_E increases but the emitter voltage V_E decreases causing the negative resistance region on the UJT characteristic), which is stable enough to be used in practical circuits such as relaxation oscillator.

Eventually, the valley point V_V will be reached and any further increase in I_E with increase in V_E will place the device in saturation region. In this region the characteristics approach that of semiconductor diode with forward bias.

The decrease in resistance in the active region is due to the holes injected into the N-type slab from the aluminium P-type rod when conduction is established. The increased hole current in the N-type material will result in an increase in the number of free electrons in the slab producing an increase in conductivity G and a corresponding drop in resistance (R ↓ = 1/G ↑).

The three other important parameters of the UJT are I_P, V_V and I_V.

 

Example—UJT relaxation oscillator

η = 0.55, R_BB = 10 KΩ, V_V = 2.0 V, V_P = 6 Volts, V_BB = 10 Volts, I_V = 5 mA, I_P = 50 μA and R_B1 = 200 Ω. During discharge phase resistor R₁ should be so chosen as to ensure that load line determined by R₁ passes through the characteristics in the negative resistance region to the right of peak and left of valley point.

The voltage across the capacitor C due to charging through R_E to the supply voltage V_BB while the UJT is in the off-state and discharging through the conducting UJT through R_B1 and R₁ is according to the following equation and the voltage wave form is as shown in the Fig. 3.52.

The behaviour of the UJT oscillator circuit as one of the applications of UJT device can be explained as follows. The R_EC combination across which V_BB is connected allows the voltage across the capacitor V_C to build up from 0 to the peak voltage V_P (V_P is as explained on the UJT characteristic) exponentially. When once V_P is reached the UJT is triggered to the ON state. This allows the capacitor, which is charged with voltage V_P that is V_C, has gone up to V_P to discharge through R_B1 almost instantly since R_B1 becomes very low. The device turns off and the process repeats generating a near sawtooth voltage wave form across the capacitor.

The output voltages of UJT can be used as trigger voltages to SCR and its other family of devices. In this UJT relaxation oscillator circuit of Fig. 3.51, the resistor R, the capacitor C and the resistances R_B1 and R_B2 predicted by the intrinsic stand-off ratio η of the device determine the frequency of oscillations of UJT and the output signal frequency according to the following equation.

Calculation of range of values of R₁ to ensure working of UJT as an oscillator of Fig. 3.51

Value of R₁ lines between 1.6 KΩ to 80 KΩ R₁ is chosen as 68 KΩ in this range.

3.10 Silicon Controlled Rectifier (Thyristor)

SCR devices are used in industrial power control applications, such as powers delivered to electric motors or induction heating elements or relay controls where the power delivered has to be controlled. In high power circuits, variable resistance control elements involve in power dissipations in controlling elements and result in power wastage. Controlled rectifier devices (similar to thyratron devices of vacuum tubes) such as Silicon Controlled Rectifiers (Thyristors) are developed to control large amounts of power using small amount of powers in the gate circuit.

Silicon controlled rectifier is obtained by adding a third P-N junction to the normal transistor structure. The silicon controlled rectifier or SCR (Thyristor) is a silicon P-N-P-N or four-layer diode or four-layer device with three P-N junctions J₁; J₂ and J₃ with three leads attached to the semiconductor materials called anode (A), gate (G) and cathode (K) with its circuit symbol as shown in Fig. 3.55. The gate terminal is added to the cathode of the familiar diode symbol. The diode arrow points in the possible easy-flow direction for current through the SCR. Gate voltages control the conduction of the SCR. The term anode implies that the terminal so named is normally connected to a voltage source in such a manner as to make it positive relative to the cathode for the device functioning.

Silicon controlled rectifier with four P-N-P-N layers of semiconductors is a four-layer diode with three diodes D₁; D₂ and D₃ (virtual connection) as shown in Fig. 3.56. These diodes with junctions J₁; J₂ and J₃ are considered with the biasing voltages that forward or reverse bias the junctions for understanding the SCR device working depending the anode voltage V_AA and gate voltages V_GG. The conduction or non-conducting states of SCR are predicted from the applied operating voltages.

Fig. 3.57 shows the basic circuit diagram to obtain the SCR characteristics.

For negative anode-to-cathode voltage V_AK, central junction J₂ in the Fig. 3.55 is prone to be forward biased, but the outside junctions J₁ and J₃ are reverse biased. As a result, this is a reverse blocking diode and the characteristic for negative voltage V_AK appears as shown in the third quadrant of the Fig. 3.58. The OFF-state resembles that of a reverse biased diode. No reverse current flows unless the avalanche breakdown voltage is exceeded.

For positive V_AK, the two junctions J₁ and J₃ are forward biased and the central junction J₂ is reverse biased. For positive V_AK, the current at low voltages is limited by the reverse bias behaviour of junction J₂ (central junction J₂ acts as a dam). Only a small forward leakage current I_FX flows through the SCR until the anode is made very much positive relative to the cathode.

As the applied voltage increases, the current increases slowly until the breakover voltage V_BO (for the central junction) is reached. At this point, it is interesting that once the dam is broken, so to speak, current floods easily through the device (the current rises abruptly) with only a small voltage drop of one volt (the voltage across SCR drops sharply) across the SCR (from anode to cathode), and the diode has switched to the ON-state. That is, the SCR has changed from an open-switch mode to a mode much like forward biased diode or a closed switch. Before forward breakover the central junction J₂ is in the blocking state (due to reverse bias to junction J₂) and at the V_F(BO)O the central junction J₂ breaks under reverse breakdown.

However, when a gate current is supplied to the SCR, the forward breakover voltage (but not the reverse breakdown voltage) is reduced in proportion to the gate current. If a gate current greater than some gate-trigger current I_GT is supplied to the gate, the device goes into the break over or conduction state for a small positive anode-cathode voltage of the order of 1 to 2 V. The gate must be positive by only about one volt relative to cathode to cause the gate make trigger current I_GT to flow. This voltage forward biases the bottom P-N junction. For low power SCRs I_GT < 0.1 mA and for high power SCRs I_GT > 15 mA, although some minimum is required in some cases.

The voltage for reverse breakdown is about the same as the SCR’s forward breakover voltage (for I_G = 0). As was true for normal diodes, the reverse breakdown situation can ruin by overheating the diode, if the current is allowed to become large. The SCR is not ruined in the forward direction breakover case since V_AK, the anode-cathode voltage quickly drops to about one volt and the device is designed to carry that current, (the V.I product is then very small) as shown in the SCR characteristics in the Fig. 3.59. Typical SCRs can pass a current of 1 to 15 amperes in the forward direction without harm, depending on the SCR rating and with proper heat sinking.

SCR Concept as Two Back-to-Back Connected Transistors

The switching operation of the four-layer device, the SCR can be understood as two interconnected transistors. In Fig. 3.60, SCR device is considered as a back-to-back combination of P-N-P and N-P-N transistors that are shown physically displaced but electrically connected. The two transistors have a common collector junction.

From the Fig. 3.61, observing the flow of currents through the two transistors T₁ and T₂, it can be seen that I_A = I_E1 = I_E2 and I_A = (I_C1 + I_C2), where I_C1 and I_C2 are as following.

 

From Fig. 3.61, the collector currents will be obtained by summing the currents into the Transistor T₁. Substituting the values of I_C1 and I_C2 in the equation I_A – I_C1 – I_C2 = 0.

          I_A − α₁I_A − I_C01 − α₂.I_A − I_C02 = 0 using I_A = I_C1 + I_C2

∴                      I_A [1 − (α₁ + α₂)] = I_C0 where I_C0 = I_C01 + I_C02                    (3.38)

 

Current gain of a transistor varies with collector current. So, at low currents α is small. As, I_A increases with an increase in V_AK, α₁ and α₂ increase. As the quantity (α₁ + α₂) approaches unity, current tends to increase without limit and breakover occurs. After switching ON the voltage across SCR is smaller than one volt and only the resistance in the external circuit limits the current.

Once in the conduction state, the SCR remains so even after the gate current/voltage is removed. The SCR remains in the ON-state until the anode voltage is reduced so that the anode current falls below a small holding current I_H (typically a few mA). The SCR will be certainly turned off if the anode is actually made negative relative to the cathode. However, a negative voltage to the SCR gate will not turn off the SCR. The turn-on time for a SCR is of the order of 1 μ sec, while the turn-off time after reverse bias is about 20 microseconds.

The introduction of gate current of the order of a few microamperes switches the SCR (Thyristor) to the ON-state at voltages lower than V_BO for the corresponding diode. Such a silicon controlled rectifier provides flexible switching and since the gate current is required only momentarily very efficient control of large currents in the anode circuit can be achieved with virtually a few microamperes of gate current that too momentarily. Therefore, the firing voltage is a function of gate current I_G. In comparison to power transistors, SCRs (Thyristors) are designed with thick base layers for high voltage capability and necessary low α characteristic. Currents may be larger because the total junction areas are available for conduction.

The characteristics of SCR are shown in the Fig. 3.62.

As can be observed from the forward characteristic of Fig. 3.62 of the SCR device, during the positive voltages of V_AK from zero to the forward breakover voltage V_BO, the device functions as an open switch because of the central P-N junction J₂ being under reverse bias and not allowing the current flow as a dam, even if the outer junctions J₁ and J₂ are under forward biased situation. During this region the anode current is of the order of a few microamperes and hence SCR behaves as an open switch with a very high resistance of the order of megaohms, the SCR being in the off-state or no conduction state. Once the anode voltage reaches the forward breakover voltage V_B0; the dam effect of central junction J₂ is broken resulting in flooding of anode current through the device. Now, the device is in the ON-state or conducting state and acts as a closed switch and at the same time, the voltage across SCR drops down to the saturation voltage of about one volt, with a consequent decrease of power dissipation across the device, as the product of the anode current and the saturation voltage across SCR is of the order of few watts. This does not cause any damage to the device. That is one of the main reasons for controlling large amounts of power.

Firing Voltage   It is defined as the minimum voltage, which is required between anode and cathode of a Thyristor (SCR) to trigger into conduction. Firing voltage is slightly more than ON-state voltage. (Firing voltage is a function of gate current I_G as shown in Fig. 3.63).

Latching Current (I_L)   It is the minimum current required to latch the device from OFF state to ON state. It can also be said to be the minimum current required to trigger the device. Typical values of latching current may range from 8 mA to 10 mA.

Holding Current (I_H)   It is defined as the minimum current required for holding the device in conduction. Below this value of current the device cannot conduct and the device returns to the OFF-state. The typical values of holding current of a device may range from 3 mA to 5 mA.

Gate Current (I_G)   It is the current, which flows into the gate terminal to control the stage of device conduction.

Turn-on Time   Though the Thyristor is a very fast switching device, it does not switch instantly, rather it takes finite time to reach its full conduction from the time the trigger signal is applied. In other words, it is called response time, also. The typical values of T_ON range from 150 nanoseconds to 200 nanoseconds.

Turn-off Time   A reverse voltage has to be applied across the device to turn-off from conduction state of the device. It takes a finite time after application of reverse voltage to switch the device OFF (commuted). This time is called the turn-OFF time of the device. The typical values of turn-off time are 200 nanoseconds.

Ratings   Peak inverse voltage (V_PIV): It is defined as the maximum voltage, which the device can safely withstand in the OFF-condition. V_PIV depends on temperature and ON-state voltage. The voltage drop across the Thyristor when conducting is very low. This voltage is called the ON-state voltage of Thyristor. The typical value of this voltage lies between 1volt to 4 volts.

Questions for Practice

1. Indicate the different current components of a collector current I_C of a bipolar junction transistor (BJT) and substantiate the name BJT given to a transistor.
2. Draw a circuit diagram to illustrate the methods of biasing a BJT for the transistor to act as an amplifying device.
3. For a transistor biased to operate in the active region of the device characteristics, in spite of the fact that the collector junction is reverse biased, collector current I_C is large. Predict the reason.
4. A transistor connected in CE configuration is biased to operate in active region of the device characteristics when V_ce = 12 volts, I_C = 10 mA and I_b = 50 μA. Calculate the value of beta (β) of the transistor.
5. Mention the influence of early effect on output characteristics of a common emitter operated transistor.
6. Discuss the significance of maximum allowed power dissipation at the collector junction of the transistor.
7. Show the various operating regions on the output characteristics.of a CE transistor.
8. Predict the region of operation on the output characteristics of a common emitter operated transistor so that the transistor is to be used as a linear amplifier.
9. Illustrate the influence of early effect on the output characteristics of a common base operated transistor.
10. For a transistor operated in CB configuration; I_C = 5.2 mA and I_e = 5.5 mA. Calculate the value of alpha (α) of CB transistor. Also, calculate I_b.
11. Mention the reason why the output resistance of CE transistor biased to act, as an amplifying device is low.
12. Draw the small signal low frequency equivalent circuit of a transistor.
13. Define the h-parameters of the transistor in CE Configuration.
14. What is the reason for calling the transistor h-parameters as hybrid parameters?
15. For a T-network having in each arm of a resistance of value 100 ohms, calculate h₁₁.
16. From the definition of β of a transistor derive the relation between β and α of a transistor.
17. From the definition of α of a transistor derive the relation between β and α of a transistor.
18. For the transistor to act as a switch mention the nature of biasing voltages for input and output junctions of a transistor.
19. Mention the relation between the components I_C, I_Co and a of a transistor.
20. Change of Ic with V_CB in active region is due to _____ and I_E components of a transistor.
21. Justify the reasons for the transistor to behave as a current controlled current source.
22. Mention the relation between I_D; I_DD; V_GS and V_p of a Field Effect Transistor.
23. Mention the main advantages of JFET over BJT.
24. Mention the reason for high input resistance of JFET.
25. Justify the reasons for JFET to function as voltage controlled voltage source.
26. Draw the equivalent circuit of JFET device.
27. Indicate pinch-off voltage on the JFET output characteristics.
28. Mention the various operating regions on output characteristics of JFET device.
29. Define drain saturation current I_DSS.
30. The disadvantage of a JFET is its _____ voltage gain.
31. Find the value of V_GS to make I_D = 12 mA, given I_DSS = 15 mA and V_p = 5 volts.
32. CC transistor with a load resistance R_L in the emitter has a _____ input resistance.
33. For a JFET device, I_DSS = 8 mA and pinch-off voltage V_p = −4 volts. Predict the value of V_GS for class A operation of the device and calculate the value of drain current I_D.
34. Define the JFET device parameters and establish the relation between them.
35. Mention the maximum voltage gain that can be realised from a JFET device.
36. JFET device has a main advantage over BJT device (a) high input impedance (b) higher gain-bandwidth (c) low noise (d) large gain.
37. Mention the reason for calling the MOSFET with induced channel as normally off MOSFET.
38. Explain the concept of how a enhancement MOSFET device functions as a switch.
39. Mention whether E-MOSFET or DE MOSFET has built-in channel in the device.
40. Mention the main advantage of DE MOSFET over E-MOSFET.
41. Explain the two types of concepts of pinch-off voltage for a JFET device.
42. Explain the reasons for varying depletion region widths in a JFET device during the operation of the device.
43. Explain the concept of threshold voltage for the working of a E-MOSFET device.
44. Mention the expression relating the threshold voltage V_TH and the other parameters of the device E-MOSFET.
45. Substantiate the reasons for the use of JFET at the input stages of electronic instruments.
46. Draw the structure diagram of N-channel JFET device.
47. Draw the structure diagram of P-channel JFET device.
48. Mention the biasing voltages on a circuit diagram to obtain the JFET characteristics.
49. Draw a typical transfer characteristic of JFET device with I_DSS = 10 mA and V_P = −4 volts.
50. Determine the transconductance g_m of a JFET device with the drain saturation current I_DSS = 10 mA and V_P = −4 volts at constant drain to source voltage V_DS = 10 volts.
51. Define the pinch voltage V_P with reference to the transfer characteristic of JFET device.
52. Define drain saturation current I_DSS from the JFET characteristics.
53. Define drain resistance r_d and of a JFET and determine the value of r_d if ∆V_DS = 10 volts and ∆I_D = 0.2 mA when V_GS = −2 volts (constant).
54. Define amplification factor μ of a JFET device and derive the relation between the three device constants μ, g_m and r_d.
55. If the amplification factor μ of a JFET device is 25, mention the maximum value of voltage gain that can be realised from an ideal JFET amplifier.
56. Define breakover voltage of a silicon controlled rectifier.
57. Define holding current of a silicon controlled rectifier.
58. What is the minimum voltage required to keep the UJT device in the ON-state?
59. In which region a bipolar junction transistor can act as a switch?
60. Explain about basewidth modulation phenomenon in a transistor.
61. Explain the functions of junction capacitances in a transistor.
62. Derive the relation between α and β parameters of CB and CE operated transistors.
63. Explain thermal run away phenomenon in transistors and how they are taken care of in the device operations.
64. Discuss the differences and common features of N-P-N and P-N-P transistors.
65. Define the transistor h-parameters in cB Configuration.
66. Define stability factor and explain its significance in transistor biasing circuit design.
67. Mention the method of finding whether a transistor is in its active region or not.
68. Discuss the conditions and the reasons for using heat sinks with transistor devices.
69. Can we call the stability factor as instability factor based on the real time situations of transistor to be operated in stable conditions Substantiate the answer.
70. Write a condition to avoid thermal runaway in transistors during their practical operation.
71. Discuss the method of determination of g_m for a transistor.
72. A certain JFET has I_DSS = 36 mA at V_GS = 0 volts. V_GS is equal to half the pinch-off voltage V_P, calculate the magnitude of drain current I_D.
73. Calculate the magnitude of input resistance of the JFET, when the gate current I_GS = 10 μA for an applied voltage V_GS = 2 volts.
74. For a FET device g_mo = 2500 × 10⁻⁶ Siemens, calculate the value of transconductance g_m when the device operating voltage between the gate and the source V_GS has a design value of half the pinch-off voltage, when the FET device is used in an amplifier circuit.

Points to Remember

1. For a JFET device, the drain current I_D = I_DSS when V_GS = 0 volts from Shockley’s equation. This maximum drain current when V_GS = 0 volts is known as drain saturation current I_DSS. This can be observed on both the output and Transfer characteristics of the FET device.
2. The value of drain to source voltage at which the channel is pinched-off is known as pinch-off voltage V_P.
3. A JFET device is a unipolar device because the device current, the drain current is due to the flow of majority carriers only.
4. A FET device has small gain-bandwidth product.
5. A JFET device is a voltage controlled voltage source.
6. For small voltages of V_DS, the drain to source voltage, the FET behaves as a simple and linear resistor.
7. JFET has three device parameters μ, g_m and r_d and are related by μ = g_m.r_d.
8. The Shockley equation for JFET device is
   
9. A JFET behaves like a variable resistor in the ohmic region of output characteristics and as a constant current source in the pinch-off region.
10. A JFET has high input impedance and low output impedance and as such, used at the input stages of electronic instruments.
11. A MOSFET is used in digital electronic circuits, because it can be operated as a binary switch.
12. DE MOSFET can be operated with both types of polarity voltages to gate voltages.
13. MOSFET device is also known as insulated gate FET (IGFET).
14. A JFET is a square law device and hence can be useful as a tuner in radio and TV circuits.
15. The conducting region in FET devices is called as a channel.
16. The main disadvantage of a JFET device is its low voltage and is limited theoretically to a maximum value μ, the amplification factor of the device.
17. Since, JFET has no off set voltage, the device has an application in chopper circuits.
18. The input resistance of a JFET device is very high, since the gate junction of the device is reverse biased and the input gate current is almost negligible or zero.
19. JFET operated in the ohmic region of the output characteristics can be used as a Voltage Variable Resistor (VVR).
20. Silicon transistors operate at high temperatures because of the silicon semiconductor has a wide forbidden band-gap energy.
21. The collector area is larger in transistor devices to allow for much heat dissipation.
22. The N-P-N transistors are preferred over P-N-P transistors, because of the high mobility μ of the electrons during conduction with resulting good frequency response of N-P-N transistor amplifiers.
23. BJT is a bipolar device because, the currents in the device are due to the movement of both electrons and holes in the transistor device.
24. For a good transistor it is necessary that all the injected electrons from the emitter to the base region (for N-P-N transistor) have to reach the collector so that the two currents I_E and I_C are almost equal. To achieve this, the base region of the transistor is made of small area of cross-section for the electrons to spend less time during their journey to the collector and further, the base region is lightly doped to minimize the numbers of recombination of holes in the P-material with electrons in the transit
25. A transistor has two P-N junctions, one between the emitter and base regions known as the emitter junction or the input junction and a second P-N junction between the base and collector regions known as the output junction or the collector junction.
26. Bipolar junction transistor can be treated as two diodes connected back to back for understanding the operation of the device as concept of P-N junctions is mostly useful for the working of semiconductor devices.
27. The transistor is a current controlled current source.
28. The main difference between JFET and BJT is that the input junction of the gate of FET device is reverse biased and has very large input resistance, whereas the input junction of the BJT is forward biased and hence the input resistance of transistor is very low.
29. The transistor is operated as a linear amplifier when the D.C. operating conditions of the transistor are fixed in the active region of the output characteristics of the device.
30. The transistor operating voltages are fixed in the saturation and the cut-off regions for the transistor to operate as an electronic switch.
31. The type of semiconductor material can be determined using Hall effect.
32. Effect of basewidth modulation is more pronounced on the output characteristics of a common emitter operated transistor over a common base operated transistor, because of the large value of current gain β of CE transistor when compared to a very low value of current gain α of a common base transistor.
33. The emitter junction of the transistor is forward biased and its collector junction is reverse biased for the transistor to act as an amplifying device.
34. The reason for the very low input resistance of a transistor is the forward bias to the input junction of the transistor and its consequent low resistance.
35. The negative resistance region lies between the peak and valley points of emitter voltages on the UJT characteristics.
36. There are two positive regions on the UJT characteristics before the peak point and after the valley points of emitter voltages on the UJT characteristics.
37. The intrinsic stand-off ratio of a UJT device lies between 0.5 to 0.8.
38. UJT device can be used in negative resistance oscillator circuits when its operation is in the negative resistance region of the device characteristics.
39. UJT output across the capacitor finds its use as a sweep voltage in CROs.
40. The UJT output voltage can be used as a triggering voltage in SCR circuits.
41. A UJT device comes into conduction state when the emitter voltage V_E is equal to the peak voltage V_P on the UJT characteristics.
42. A common emitter operated transistor configuration is more popular because of its large values of voltage and current gains.
43. In a transistor the emitter region is more doped than the collector and the base regions.
44. The E-MOSFET operates with enhance mode only for the induction of the channel between the drain and source islands in the device for the device to come into the conduction or ON-state, otherwise E-MOSFET is initially in the normally OFF-state.
45. There is no thermal run away phenomenon in the FET devices as the input signal voltages to the FET device are of the order of volts and the voltage equivalent of temperature V_T is of the order of 26 mv at 300°K, which tries to perturb the input signal operations has negligible contribution.
46. The JFET device operates only in depletion mode.
47. The electron mobility is larger when compared to hole mobility in the solid semiconductor medium, because of the small mass for the electrons. So, the N-channel MOSFET devices work faster than P-channel MOSFET devices.
48. The input impedance of the MOSFET (IGFET) device is high because of the insulating layer SiO₂, between the gate and the conducting channel of the device.
49. The N-channel MOSFET device is normally off when V_GS = 0 volts.
50. The gate-to-source voltage that turns on the E-MOSFET device is called as threshold voltage and it also depend upon the geometry of the device as the constant K connecting the drain current is I_D = K. (V_GS − V_TH)².
51. The DE MOSFET works either in enhancement mode or depletion mode depending upon the practical applications.
52. I_D = K(V_GS − V_TH)² for enhancement-MOSFET device transfer characteristic.
53. In a DE MOSFET device, the method of reducing the conductivity of the channel between drain and source of the device by applying suitable polarity voltage at the gate terminal for removing or depleting of the free charges in the channel is known as depletion operation.
54. The enhancement MOSFET has no physical or built-in channel. The device works on the induction of channel between the drain and the source on applying suitable polarity voltage at the gate electrode.
55. Reverse biasing voltages at the P-N junctions of the FET device produce depletion region widths in the channel, thereby increasing the channel resistance.
56. Enhancement MOSFET requires a minimum gate-source voltage V_GS for induction of channel between the drain and the source for device conduction. So, E-MOSFET will not work for zero voltage of V_GS. So, E-MOSFET has no I_DSS parameter.
57. DE MOSFET has a physical or built-in channel for the device working.
58. The difference between JFET and MOSFET is that JFET has a PN-junction.
59. The constant current area on the drain characteristics of FET device occurs in the pinch-off region or the region between the pinch-off voltages V_p to the point of just nearing the breakdown point.
60. The gate-source voltage on the N-channel JFET device should either be zero or negative so as to maintain the very high input resistance of the device by maintaining the reverse biasing voltages at the gate-source junctions.
61. The depletion region widths close the channel completely (but never overlap) when the drain current is zero at the pinch-off voltage or V_{GS (off)} for the FET device.
62. The channel of a JFET is between the drain and the source.
63. MOSFET has insulated gate electrode from the drain and the source.
64. 
65. 
66. The negative resistance region of UJT characteristic is used in the design of relaxation oscillators using UJT devices.
67. For a transistor to be operated as an electronic switch, the D.C. operating conditions are fixed in the cut-off and saturation regions.
68. The values current gain β of CE transistor change from one transistor to another transistor of the same type and so the stability of operation gets effected whenever a transistor is replaced with another unit of the same make and device number.
69. Transistors are classified generally as low or medium power transistors, power transistors, switching transistors, low frequency transistors and high frequency transistors depending on their applications in the practical circuits.
70. Making use of the property of a P-N junction with reverse bias voltage has large value of reverse resistance R_r and the P-N junction with forward bias will have a very low value of forward resistance R_f, a bipolar junction transistor can be tested with a multimeter for its failure or not keeping in view of the behaviour of the transistor device having two P-N junctions one at the emitter-to-base junction and the second PN-junction at base and collector areas of the transistor.
71. Explanation of why the current gain α for CB transistor is less than 1. The current gain alpha α of the transistor is defined for common base operated transistor.
    

    From the definition of the current gain alpha, the output current, the collector current I_C is less than the input current, the emitter current I_E. Hence, the current gain α < 1. Further, the emitter current (I_E) and the collector current (I_C) are approximately equal. So, alpha is approximately unity.

     

72. Explanation of why the current gain β for CE transistor is >> 1. The current gain beta β of the transistor is defined for common emitter operated transistor.
    

    From the definition of the current gain beta, the output current; the collector current I_C is very much greater than the input current, the base current I_B. Hence, the current gain β >> 1.

     

73. Explanation of how the transistor is considered as current controlled device.

    The transistor operates in the active region when the base-emitter junction J₁ is forward biased and the base-collector junction J₂ is reverse biased irrespective of the transistor configuration. Emitter region is heavily doped and so large numbers of electrons are injected from the emitter into the base region. That is how the emitter is considered as the source of electrons. The emitter current I_E is the sum of majority carrier electron current and the minority carrier hole current in the N-P-N transistor.

    All the electrons that cross the emitter-base junction do not reach the collector, since there are some recombinations with holes in the base region contributing to very small magnitude of the base current I_B and the remainder enters the collector and the collector current component is I_NC. There is a small minority carrier current due to reverse bias of the base-collector junction designated as the current I_C0.

    The net collector current will be I_C = (I_C0 – I_NC); if I_E is not equal to zero. When I_E = 0, the collector current I_C = I_C0; since I_NC representing the injected carrier current is zero since I_E = 0.

    

    The above discussions indicate that the transistor is a current controlled device.

     

74. Diagram showing the biasing circuit for PNP transistor in common emitter configuration. PNP transistor in common emitter configuration with biasing voltages, the forward bias V_BE to forward bias the emitter junction and the reverse bias V_CE to reverse bias the collector junction (necessary biasing voltages for the transistor to act as an amplifying device) are shown in the Fig. 1.
    

    FIGURE 1 Common emitter (P-N-P) transistor with biasing voltages to obtain input and output characteristics

75. Explanation of operation of CE mode P-N-P transistor using its input and output characteristics.

    When the input junction is forward biased by V_BE, the majority carrier holes are injected from the P-material emitter into the N-material base, overcoming the cut-in voltage of the input junction, (cut-in voltage is seen on the transistor input characteristics in Fig. 2) as majority carriers contribute to the current through the emitter junction. The injected minority carrier holes move by diffusion from the emitter junction to the collector junction. During this journey some electrons of thin and lightly doped N-material base recombine with the diffusing holes contributing to the base current, I_B. As most of the emitter current has to reach to the collector to function as a good transistor as the output collector current I_C, the recombinations in the base are made deliberately less by light doping and of smaller area of cross-section of the base.

    

    FIGURE 2 Input characteristic of CE Transistor

    As the collector junction is reverse biased by V_CE the holes, the minority carriers in the base move into the collector region contributing to the collector current. Thus, the emitter current is equal to the sum of the base current and the collector currents. On the output characteristics shown in the Fig. 3, a slight upward slope of the collector current is seen which is due to the early effect due to the reverse bias to the output junction. The output characteristics are drawn for different constant values of the base currents as shown on the output characteristics. Further, the output characteristics find three region of operations, 1) saturation region 2) cut-off region and 3) active region. For the transistor to be operated as an amplifier, the biasing voltages known as the D.C. operating conditions are fixed in the active region of the characteristics for the amplifier to function as a linear amplifier.

    

    FIGURE 3 P-N-P transistor common emitter characteristics

76. The three FET device constants are transconductance g_m, drain resistance r_d and the amplification factor μ. The following are the definitions with the relation between them:

    Transconductance,

    

    Drain resistance,

    

    Amplification factor

    

    From these definitions

    

77. Explanation of the operation of the transistor when the emitter junction is forward biased and the collector junction is reverse biased.
    

    FIGURE 1 Common emitter transistor circuit to explain the operation of the transistor as an amplifying device

    For a transistor to function as an amplifying device the input junction called as the emitter junction J₁ of the transistor is to be forward biased (D.C. source used for this purpose is known as bias voltage) by a voltage and the output junction, the collector junction J₂ is to be reverse biased by a voltage. Consider common emitter operated transistor with forward bias V_BE to the input junction J₁ for the input diode between base and emitter and reverse bias V_CE to the output junction J₂ for the output diode between base and the collector of the N-P-N transistor as shown in the Figures 1 and 2.

    When the forward bias V_BE is increased, there are two forces that act on the majority carrier electrons in the N-material emitter of the N-P-N transistor. Force F_VBE = e.V_BE due to the forward bias pushes the electrons towards the junction, thereby reducing the depletion region about the input diode junction J₁ (of the input diode) between base and emitter regions of the transistor. The negative immobile ion charge at the junction J₁ in the P-material base region due to the contact voltage (or built-in voltage or barrier potential V_B) V₀ tries to restrain the entry of electrons with a force F_V = eV_V0 as long as the barrier potential V₀ is not reduced. Once the forward bias V_BE overcomes the opposing affect of contact potential, that is, when the actual junction potential (V₀ − V_BE) at that instant is less than the barrier potential V₀; electrons are injected from the emitter into the P-material base region of the transistor.

    The movement of the injected minority carrier electrons from the emitter into the base region to the other end of the base area is by diffusion, because of the charge gradient among the injected electrons and the small quantity of originally existing minority carrier electrons in the P-type base material. During this course of journey some electrons recombine with the holes in the base material. These recombinations are less in number, because of the small area of cross-section of the base material and light doping; the numbers of available holes for recombinations are less (for a good N-P-N transistor, almost all the electrons injected from the emitter into the base will be collected and I_C is preferable to be almost equal to I_E. Hence, the P-type base region should be narrow and the electron lifetime should be long). The lost holes in recombinations are supplemented by positive of V_BE contributing to the very small magnitude of the base current I_B; which is shown as entering into the base of the transistor. Once the injected electrons are at the junction J₂ of the output diode, the electrons enter the collector region because of the reverse bias to the output junction J₂ (of the output diode) and then are pulled onto the positive of the supply voltage V_CE. So, the collector current I_C is into the collector terminal (direction of the conventional collector current I_C is opposite in direction to the movement of electrons out of the collector terminal). Also, it can be seen from the directions of flow of the base current and the collector current through the emitter terminal as the emitter current I_E; which is the sum of the base current and the collector current.

    Mathematically,                    |I_E| = |I_B + I_C|

    Thus, mathematically, I_E is expressed as above, for the N-P-N transistor under discussion.

    

    FIGURE 2 CE Transistor with biasing voltages to explain the operation of the transistor

78. Explanation of the need for biasing of transistor devices.

    Basically, the bipolar junction transistor (BJT) is used as a two-port network or as a four terminal network and functions as an amplifying device along with other applications. The name for the device itself is an acronym formed from the two words transfer and resistor. For achieving different levels of resistance, say, low resistance at the input port, the input junction of the transistor is to be forward biased and to achieve larger resistance at the output port of the transistor output junction is to be reverse biased. These different levels of resistances at the input and output ports of the transistor contribute to the amplifying action of the transistor. Thus, for the transistor to act as an amplifying device, there is need for biasing the input (emitter junction) and output (collector junction) junctions of the transistor.

    Further, the quiescent operating point or the D.C. operating point Q of the transistor is located on the D.C. load line drawn on the output characteristics of the transistor, depending upon the class of operation of the amplifier. For linear operation of the amplifier, the quiescent operating point is located at the middle of the D.C. load line for the device operation to be in the active region of the output characteristics and symmetrical input and output voltages. Fixation of the quiescent operating point Q; that is, the quiescent collector current I_CQ and the voltage between the collector and the emitter V_CE.Q of the transistor are fixed by the biasing voltages for the emitter junction and the collector junctions of the transistor.

     

79. UJT Symbol and reason for the device name as, unijunction transistor

    The unijunction transistor (UJT) or P-N transistor is a two-layer P-N device with three terminals known as emitter, base-1 (B₁) and base-2 (B₂). Similar to the bipolar junction transistor, the UJT is fabricated on a lightly doped N-type silicon bar with ohmic contacts for the two base terminals B₁ and B₂ at the top and lower ends of the bar. The emitter section is a heavily doped P-type material that is deposited between the base B₁ and base B2 regions, possessing only one P-N junction of small area. As the device has only a single junction, it is known as a unijunction transistor.

    

    FIGURE 1 Unijunction transistor (UJT)

80. Equivalent circuit of the UJT device in the Fig. 2.

    The equivalent circuit of UJT has two resistors R_B1 (variable resistance) and R_B2 (fixed resistance) that form a voltage divider during the operation of UJT and a single diode representing the P-N junction between the emitter and the base B₁. That is the reason why the device is called a unijunction transistor. R_B1 may vary from 5 KΩ to 50 KΩ for a corresponding change of I_E from 0 to 50 milliamperes during the device operation.

    The resistance R_B2 is a fixed internal resistance between the emitter and base-B₂. The resistance R_B1 is the internal variable resistance of the silicon bar between the emitter and base B₁ that depends on the operation or ON−OFF states of the UJT device. Inter electrode base resistance R_BB = R_B1 + R_B2 (I_E = 0), that is when V_E = 0 V. R_BB is typically in the range of 5 KΩ to 10 KΩ. The position of Al rod functioning as the emitter electrode will determine the relative values of R_B1 and R_B2 with I_E = 0.

    Simplified equivalent circuit for UJT

    

    FIGURE 2 UJT equivalent circuit for device working

81. UJT emitter characteristics and various regions marked on the Fig. 1
    

    FIGURE 1 UJT characteristic

82. Working of UJT device when the emitter voltage V_E < V_Peak

    Initially, when V_BB is switched on, and the emitter voltage V_E = 0 volts; voltage across R_B1 will be of such a polarity that will reverse bias the P-N junction between the emitter and base B₁ as can be understood from the equivalent circuit of UJT in Fig. 2. Only reverse current I_E0 of the order of a few microamperes will be present through the device in the emitter circuit and the UJT device is in the off-state. The device is in the cut-off region of the characteristic as shown in the Fig. 3 showing the emitter characteristic and the operating regions of UJT device.

    Working of UJT device when the emitter voltage V_E > V_Peak

    For applied potential, V_BB; with increased voltages, when V_E is greater than V_RB1 = ηV_BB by the forward voltage drop across the diode V_D, (V_D = 0.35 to 0.7 volts, as UJT has silicon semiconductor bar); the diode (P-N junction between the emitter and base B₁) is forward biased and the UJT will fire. Emitter current I_E will begin to flow through R_B1 in the emitter circuit due to the heavy injection of majority carrier holes from the emitter into base B₁. The emitter firing potential V_P is given by V_P = ηV_BB + V_D.

     

83. Calculation of the peak voltage V_p

     

    Data η = 0.8 V_BB = 15 volts and V_D = 0.7 volts

     

    Peak voltage = V_P = η.V_BB + V_D = 0.8 × 15 + 0.7 = 12.7 volts.

     

84. Discussion of the method of determination the quiescent drain current I_DQ and the voltage between the drain and the source for JFET from its static characteristics.

    Basic JFET amplifier circuit Fig. 1.

    Amplifiers consider the input and output A.C. signals for amplification.

    Now, consider the JFET amplifier a small signal amplifier as in Fig. 1.

    

    FIGURE 1 Basic JFET amplifier circuit

    In the basic amplifier circuit shown in the Fig. 1, both the D.C. voltages are 1) gate supply voltage or gate to source bias voltage V_GG used to set the D.C. voltage V_GS (based on the type of the amplifier and its class of operation) and 2) drain supply voltage V_DD so as to set the drain current (output current) I_D flowing through the FET device to a value such that the voltage across the load resistance R_L = I_D.R_L = V_RL is about half the supply voltage V_DD to satisfy the class A operation of the amplifier.

    The bias (D.C. voltage) V_GG is arranged such that the gate of the N-channel FET is made negative relative to the source, because the requirement is that gate-channel diode junction of the N-channel FET is to be reverse biased so that the input resistance R_in of the FET device is very large, which is an advantage over the BJT devices and facilitates non-ideal driving voltage amplifiers.

    The gate-source voltage V_GS is established by the bias voltage V_GG as shown in the basic amplifier circuit of Fig. 2. Because there may be a gate current of only of the order of a few nanoamperes, the voltage across the gate resistor R_G (10 × 10⁻⁹ × 1 × 10 ⁻⁶ = 10⁻³ volt) negligibly small and the gate -source voltage V_GS is virtually the same as −2 volts. for class A operation of the amplifier. V_GS = (1/2). V_P.

    The swings of the input signal voltage V_IN and the output voltage V_OUT of the JFET amplifier depend on the location of the quiescent operating point and in turn, on the class of operation of the amplifier depending on the practical applications.

    Assume the following output characteristics (static characteristics) for the JFET device as shown in the Fig. 2.

    

    FIGURE 2 Static characteristics of JFET device with DC load line to obtain quiescent voltage and current at quiescent operating point ‘Q’

    The output characteristics of the device can be obtained experimentally or by a curve tracer using a cathode ray oscilloscope. When the JFET device is biased with voltages for the required class of operation of the amplifier, steady state values of the drain current I_D and the voltage V_DS are related by D.C. load line equation for the amplifier analysis.

    Obtaining the D.C. equivalent circuit of the amplifier circuit in Fig. 2, the D.C. load line equation can be written as the following:

     

    V_DD = V_DS + I_D.R_L……D.C. load line equation.

    At the point X of the D.C. load line in the Fig. 2; V_DS = 0 volts; and the other coordinate is obtained by substituting V_DS = 0 in the above D.C. load line equation. Therefore, I_D = (V_DD/R_L). Similarly, for the coordinates of the point Y of the D.C. load line in the Fig. 2, I_D = 0 mA, and the other coordinate is obtained by substituting I_D = 0 in the D.C. load line equation. Therefore, the other coordinate of point Y is V_DS = V_DD.

    The coordinates of the point (X) of the D.C. load line are V_DS = 0 volts and I_D = (V_DD/R_L) and the coordinates of the point (Y) of the line are V_DS =V_DD volts and I_D = 0 mA. Joing the two points, the D.C. load line can be drawn on the static characteristics of the JFET device. The drain current I_D.Q and the voltage V_DS.Q between the drain and the source of the JFET device corresponding to the selected quiescent operating point are obtained by superimposing the D.C. load line on the static or output characteristics for the required quiescent point operation of the amplifier.

     

85. Explanation of the JFET device as a switch.

    As shown in the Fig. 1 the FET device can be used as a switch. The drain supply voltage V_DD is applied between the upper end of the drain circuit resistance R_D and the ground terminal, with the polarities of the supply voltage suitably oriented depending on whether the FET device is an N-channel FET or a P-channel FET device. The voltage V_GS between the gate and source is used to apply suitable voltage to the FET device for turning the device to the ON-OFF states.

    

    FIGURE 1 FET operation as a switch

    Apply drain supply voltage V_DD, for example, 10 volts. Apply V_GS = 0 volts. The drain current I_D will be equal to the drain saturation current I_DSS. Then, the voltage between the drain and source V_DS is designed to be approximately zero by suitable design value of the drain circuit resistance using the following equation and selecting the FET device that is specially designed to function as a switch with very low value of the ON resistance r_dS.

     

    V_DS = V_DD − I_D.R_D                    (1)

    Now, the effective drain-to-source resistance r_DS may be an effective short circuit or a few tens of ohms of the order of 50 ohms.

    

    From the transfer characteristic of the FET device, the drain current I_D will be zero at the pinch-off voltage V_P. So, as to bring the FET device into the non-conduction state with zero drain current the voltage V_GS of magnitude greater than the specified pinch-off voltage for the selected FET device is applied. Then, the voltage across the drain and source V_DS of the FET device will be almost equal to the supply voltage V_DD, as the resistance between the drain and the source r_DS will be so high of the order of mega ohms, that FET can be considered as an open circuit.

    

    The resistances of the FET devices under these two operating situations are known as ON resistance and OFF resistance of the FET device. The ON and OFF states of operation of the FET device suggest the practical use of the device as a switch.

     

86. Verify that collector current of a common emitter mode transistor operated in the active region of its output characteristics is given by the following equation.

    When a transistor in common emitter configuration has the emitter junction forward biased and the collector junction reverse biased, the transistor operates in the active region of its output characteristics. Then, the collector current I_C is expressed as in the following equation:

                                              I_C = β.I_B + (1 + β).IC0

                                              I_C = −α.I_E + I_C0                    (1)

    But the base current                I_B = −(I_c + I_E)                    (2)

    ∴                                         −I_E = (I_B + I_C)                    (3)

    Substituting equation (3) in the equation (1)

                                         I_C = α(I_B + I_C) + I_C0                    (4)

    rearranging the terms in the above equation

                                      I_C (1 − α) = α.I_B + I_C0                    (5)

    

    Also,

    

    

    

    using equations (7), (8), and (9) into equation (6)

     

            β = β.I_B + (1 + β).I_C.0                        (10)

     

87. Compare JFET and MOSFET with respect to various features.

    Features of N-channel JFET.

    Consider N-channel JFET device. N-material semiconductor bar of cross-sectional area A and length L has the drain terminal at the upper end and source terminal at the lower end. The N-type semiconductor bar is a sandwich between the two small areas of P-materials at left and right sides of the bar to have combined function as gate electrode. The N-type semiconductor bar has conductance G_C of magnitude given by the following equation and functions as a channel for device currents.

    

    where, n = electron concentration in the channel of the semiconductor

             μ_n = mobility of the electrons e = charge of the electrons.

             A = Area of the cross-section of the N-type bar = w.2a = w.b

    where, w is width of the channel and 2a or b is the breadth of the channel.

    The applied voltages or the fields at the two P-N junctions of the device effect by varying the depletion region widths into the channel and in turn, variation of the conductance G of the channel is a function of the applied fields for the junction field effect transistors. Thus, the two reverse biased junctions vary the cross-sectional area A of the conducting channel of the JFET.

    Hence, the resistance R_C of the channel is the reciprocal to the conductance G_C.

    As long as the applied voltage V_DS is small compared to the barrier potential of the two junctions, the depletion region widths about the two junctions are constant and hence, the channel acts as linear resistor with linear increase in the drain current for small values of V_DS.

    The applied fields according to following equation govern the drain current magnitudes.

    

    With increasing V_DS the reverse bias towards the drain end increases, with increasing depletion region widths near the drain end. Ultimately, at some V_DS the two depletion regions merge and drain current remains constant. This drain to source voltage beyond which the drain current tries to remain constant is known as the pinch-off voltage V_P.

    

    where, 2a = breadth of the channel towards the depletion regions

               ε_S = Dielectric constant of the semiconductor material

              ε_S = 12 ε₀ where ε₀ = permittivity of free space.

     

88. Features of MOSFET

    MOSFET devices have either built-in channel (DE MOSFET) or induced channel (MOSFET) for the device functioning. Voltages between gate and the source terminals V_GS through capacitor action vary the carrier concentrations (electrons for N-type channel MOSFET or holes for P-type channel MOSFET) in the channel. This turn varies the conductivity of the channel and the device currents or channel currents.

    The gate electrode is isolated or insulated from the other electrode structures. So, the input and the output ports are isolated with MOSFET amplifiers. The device is also known as IGFET. The MOSFET device consists of metal, silicon dioxide layer as insulator; N-type or P-type semiconductor substrate to form the source and the drain islands and a channel containing either electrons or holes as current charge carriers to modulate the conductivity of the channel

     

    I_D = K.[V_GS − V_TH]²

    where, K depends on the device structure

    and V_TH is the threshold voltage for device conduction.

    MOSFET circuits occupy less space on silicon wafer and consume less power than the BJTs. They are suitable for VLSI circuits, such as CPU, RAM and a variety of ICs in practical circuits.