Chapter 4

Amplifiers Using Bipolar Junction Transistors or FET

The most important application of a BJT (bipolar junction transistor), or a FET (field effect transistor) is to act as an amplifier. Each amplifier stage consists of an active device a BJT or a FET, D.C. source, A.C. source and associated circuit components. To understand certain basic amplifier features such as amplification of signals, input and output impedances, frequency response of amplifiers, and so on. Block Box model of an amplifier is discussed initially.

An amplifier can be treated as a two-port network with two terminal pairs; one pair of input terminals and one pair of output terminals. In most of the cases, there is a common terminal between the input and the output ports called the ground node (ground terminal) G as shown in the Fig. 4.1.

As shown in the Fig. 4.1, between 1 and 2 input pair of terminals, a voltage or current source can be connected and the input quantity can be V_in or I_in. Similarly, at the output pair of terminals, an output voltage V_out (output voltage) or output current I_out is developed irrespective of the nature of the source; there will be both V_in and I_in and these are interrelated by Thevenin’s and Norton’s theorems. If the output quantity is more than the input quantity, the two-port network is said to function as an amplifier.

A_V and A_I are both dimensionless quantities.

In addition to A_V and A_I; two more quantities known as output impedance Z_out and input impedance Z_in are also defined.

The reciprocals of Z_in and Z_out also will be useful in active network analysis.

If, V_out < V_in or I_out < I_in the two-port network is known as an attenuator.

4.1 BJT and FET More Often used in Amplifiers

For instance, the public address system is used to make the sound from an individual, audible to a large gathering by first converting the sound energy into electrical signal voltage of the order of a few hundred to a few thousands of microvolts by a microphone. This electrical signal is given as an input to a two-port network acting as an amplifier with gain A_V.

This two-port network will have an active device such as a bipolar junction transistor or a field effect transistor and an associated circuit. The output signal V_out from the amplifier is an enhanced version of the input signal, say, an electrical signal output from a microphone and is used to drive a loudspeaker system. The loudspeaker system converts the amplified electrical signal (V_out = A_V V_in) back into amplified sound.

This public address system can be represented as shown in Fig. 4.2.

    V_Mike = Voltage from the microphone (transducer) called the source voltage.

    Z_Mike = Self-impedance of the microphone.

Z_Speaker = Self-impedance of the speaker (transducer) which acts as a load Z_L to the amplifier.

For instance,

This expression in the equation (4.5) shows that unless Z_Mike is negligible compared to Z_in; V_in will be lower than V_Mike.

When a FET is used as an amplifying device, since its input impedance Z_in is theoretically infinite (Z_in is of the order of hundreds of megaohm) V_in = V_Mike. This discussion suggests that the input impedance of an amplifier should be infinite or very large compared to the source impedance Z_s; (Z _Mike in this specific application) when excited by a voltage source. On the other hand, if the exciting source is a current source,

where I_S is the magnitude of the current of the current source.

It can be inferred from the above expression that to maximize I_in; either Z_in should be zero or Z_s should be theoretically infinite or very large compared to Z_in.

Similarly, to get a maximum voltage at the loud speaker or at Z_L; Z_out > zero (Z_out should tend to zero). The significance of Z_out and Z_in for two-port network acting as an interface is well established. One more important point is that if two-port network acts as a controlled current source, its self-impedance should tend to infinity or the load impedance Z_L should tend to zero. (To get maximum current for a load from a current source, the load impedance should tend to zero. This finds use in the future analysis in maximising the current gain from an amplifier. Similarly, when an amplifier is designed to get maximum voltage output, the load impedance should tend to infinity or several orders high compared to Z_out of the amplifier).

A brief description of the components of a basic amplifier with an active device   It was seen in the characteristics of the BJT and FET devices that (for an active device together with circuit components to act as an amplifier) for an amplifier, it should operate in the active region of the output characteristics. For BJT, this requires that the input junction is forward biased and the output junction is to be reverse biased. (An acronym can make the remembrance easy by saying IFOR active; this can be interpreted as I for input junction, F for forward bias; O for output junction and R for reverse bias. This means that to maintain a transistor in the active region of the output characteristics, the input junction is to be forward biased and the output junction is to be reverse biased immaterial of whether it is N-P-N or P-N-P transistor). Fig. 4.4

A transistor amplifier will have two types of operating conditions, with the D.C. and the A.C. voltages. And so, it has a D.C. equivalent circuit and an A.C. equivalent circuit.

R_L (load resistor) and R_B (base resistor) are so chosen to maintain the transistor in the active region at a convenient base current and collector current as required for the specific class of operation of the amplifier based on the application of the amplifier circuit.

Generally, amplifiers get alternating signals for input signals V_in. The amplifiers are expected to develop proportionate and increased output A.C. signals V_out at the output port of the amplifier.

So, A.C. and D.C. versions of the equivalent circuits differ in that capacitors are used to separate A.C. and D.C. components. In D.C. circuits they are considered as open circuits (X_cin or X_cout = = ∞ for). In this context of blocking D.C. voltages, they are called as blocking capacitors C_B.

In A.C. signal operations the capacitors are expected to function as short circuits and couple the A.C. signals from the signal source to the input port and output port of one stage to the input port of other stage. They are called coupling capacitors C_C in this context. The capacitor that connects the A.C. input signal at the input port of the first stage of amplifiers is known as C_in. The capacitor that connects the A.C. signal from the output port of an amplifier to the load is known as output coupling capacitor C_out.

4.2 Transistor Biasing Methods

The simplest method to maintain a bipolar junction transistor (BJT) in the active region is to use two separate D.C. sources as shown in the Fig. 4.7. One D.C. supply V_BB between the base and emitter with a series resistance R_B is used to maintain the required base current (forward bias V_BE to forward bias the input junction, the emitter junction of the transistor). A second D.C. supply V_CC between collector and the emitter is used to maintain reverse bias to output junction that is the collector junction of the transistor. This method of biasing makes the transistor to behave as an amplifying device.

Instead of using two separate D.C. supplies, one D.C. supply V_CC in combination with a few resistors, three types of biasing circuits were developed, (1) fixed biasing circuit, (2) collector to base biasing circuit, and (3) potential divider biasing or self-biasing circuit.

The type of biasing circuit in use depends upon the class of operation of the amplifier and bias stability requirements of the circuit which are discussed one by one in a logical sequence.

Fixed Bias Circuit

Using a single D.C. source V_CC with a reorientation of R_B of the circuit in the Fig. 4.7 will be sufficient for properly biasing the transistor that is to provide forward bias V_BE to input junction, the emitter junction of the transistor and the reverse bias to the output junction, the collector junction of the transistor (the type of biasing voltages also depends on whether it is an N-P-N or P-N-P transistor and the type of connection of the transistor CE, CB or CC configuration of operation of the transistor). This arrangement is called the fixed bias circuit, or fixed current bias circuit as shown in the Fig. 4.8.

The fixed bias or base bias circuit uses only a single D.C. source or supply voltage V_CC (for example, from a transistor power supply) and two resistors R_L (or R_C) and R_B so as to provide the required magnitudes of forward bias (FB) to the input junction (emitter junction between the base and the emitter areas) of the transistor. Simultaneously, reverse bias (RB) is available to the output junction (collector junction between the base and the collector areas) of the common emitter connected transistor.

Fixed Bias or Base Bias Circuit for Common Emitter (N-P-N) Transistor

The choice of R_L and R_B is not entirely arbitrary, but it is subjected to some design constraints. For instance, V_CC should always be less than V_{CE max}, as prescribed by the specifications given by the manufacturer of the active devices.

In addition to this, the second point to be considered is that the power dissipation V_CE.I_C at the collector junction of the transistor should always be less than the allowed maximum power dissipation specified by the manufacturer. This design constraint is represented by a curve drawn on the output characteristics called as the power dissipation curve. This requires that the D.C. load line XY should always be below the power dissipation curve. These details are shown in the Fig. 4.9. This is assured if V_CEQ1 is less than or equal to for small signal operation of the amplifier.

Under these circumstances, the following KVL equations can be written. At the output circuit loop ACEA

                  V_CC = V_RL + V_CE

                  V_CC = I_CR_L + V_CE

        V_CC − V_CE = I_CR_L ---- D.C. load line equation.        (4.7)

This equation (4.7) represents the equation of a straight line known as D.C. load line equation. This has a negative slope of as shown in Fig. 4.9

In equation (4.7); if I_C = 0 mA, then V_CE = V_CC, and this represents one point, say, Y with the coordinates (V_CE = V_CC; and I_C = 0).

At point X; V_CE = 0 volts then So, the coordinates of X are . Joining the two points X and Y; the D.C. load line is drawn on the transistor output characteristics as shown in the Fig. 4.9.

From Fig. 4.8 using KVL equations for the input side loop ABEA

V_BE active = 0.3 volts for germanium transistor

V_BE active = 0.7 volts for silicon transistor

when V_BE active << V_CC as is the case in most applications.

The current I_B is constant and so this type of biasing network is called as fixed bias circuit.

Under no signal conditions, the D.C. operating point will be the point of intersection of the V_CE versus I_C characteristic for and the D.C. load line. This load line is to be located below the power dissipation characteristic (power dissipation curve can be drawn from the maximum power dissipation rating of the selected transistor) for safe operation. The quiescent operating point Q (bias point) is determined graphically, knowing the class of operation of the amplifier in which the transistor amplifier circuit is to be used. The quiescent or D.C. operating point Q₁ is fixed at the middle of D.C. load line for class A operation of amplifier.

Shift in DC Operating Points Q₁   The D.C. operating point shifts due to temperature variations as well as variations due to device parameters in case of replacement of the active device.

Since                    I_C = − αI_E + I_CO and I_C = βI_B + (β + 1) I_CO

Even if, I_B is constant, I_C can change due to changes in β or I_CO. In a circuit, if a transistor fails and is replaced by a new transistor, for the same I_B; I_C is now β₂I_B and may be more or less than the previous value if β₂ is the β of the new transistor. Similarly, if the collector current I_C, is I_C for temperature T₁, and if the temperature rises to T₂; I_C will be now I_C2 such that I_C2 ≠ I_C.

Even then the operating point Q₁ shifts as shown in Fig. 4.10.

Let Q₁ be the operating point at a particular temperature T₁ and β = β₁. If temperature falls to T₂; Q₁ is pushed down to Q″. On the other hand, if β increases to β₂ due to replacement of the transistor, Q₁ is pulled up to Q′. In the former case with Q″ for the same input signal drive; a portion of the output signal may be cut-off and the signal swing is reduced. If Q₁ is pulled up to Q′, V_CEQ shifts left and the signal swing is restricted due to the transistor entering into the saturation region.

So, to guard against these variations and making the operations stable, following techniques can be adopted. Before analysing the circuits, the stability of operating point Q is defined and criteria for stability are arrived at.

Let stability factor S be defined as

Differentiating this equation with respect to I_C

Now, the stability factor

In the fixed bias circuit I_B and I_C are independent and the stability factor becomes (β + 1). If, I_B and I_C are independent; . Substituting this in the equation 4.12 for stability factor S,

can be justified as follows:

For a fixed bias circuit shown in Fig. 4.8

Collector to Base Bias Circuit

In this circuit of Fig. 4.11, resistor R_B is now connected between collector and base. It can be seen that stability of the quiescent operating point Q is improved as can be observed by reduction in the value of stability factor S.

For the collector to base bias circuit in Fig. 4.11 (loop A-C-B-E-A)

Differentiating the above equation with respect to I_C

i.e.

Substituting – for into the equation (4.15) we obtain the following expression for stability factor S.

Hence, this value of stability factor S is much smaller than (β + 1), which is derived previously for the fixed bias circuit. So, there is an improvement in stability of operation with collector to base bias circuit

If R_B << R_L; (R_L + R_B) ≈ R_L

Thus if this condition is satisfied, then there is a large improvement in stability. But this becomes a practical impossibility, since I_B becomes excessive when R_B is very small and the device may saturate. Actually in all practical circuits R_B will be a few orders greater than R_L. Assuming that R_B = 15 R_L and substituting in the equation (4.17) for S

If β = 50; the equation (4.19) becomes

In this collector to base bias circuit, an additional disadvantage is that there is an unavoidable negative feedback from output port to the input port through R_B; resulting in gain reduction. Also, both the output and input impedances get reduced due to this feed back through R_B. This circuit has become obsolete.

Potential Divider Bias or Self-Bias Circuit

In the potential divider bias circuit of Fig. 4.12, V_CC in association with R₁ and R₂ provide the bias and R_E provides bias stability as is explained.

Thevenin’s equivalent circuit for analysis is given in the Fig. 4.13

Applying Thevinin theorem in the circuit of Fig. 4.12

(i.e. potential division of V_CC between R₁ and R₂ i.e. open circuit voltage)

To get the equivalent Thevinin resistance R_Th; short circuit the voltage source V_CC. Then, the circuit is as shown in the Fig. 4.15.

R_Th then is the parallel combination of R₁ and R₂

In the loop BDGEB,

 

Differentiating above equation with respect to I_C,

Substituting this in the equation for stability S

Rearranging the terms in the above equation (4.22),

Stability factor S can be rewritten as

So, the inference is that S varies between 1 for small values of R_B /R_E and (1 + β) if R_B /R_E is very large.

It is not practically possible to make R_B /R_E small, since decrease in R_E reduces input impedance, thus affecting the performance of the amplifier. By choosing suitable values for R_B and R_E, transistor-biasing circuits can be designed for desired values of stability factor S.

Generally, lower values of S are obtained with potential divider bias circuit. This circuit has more stable Q (self-correction of bias through R_E in the circuit) and so this circuit is more popular than the other biasing circuits.

For instance, if S is to be of a prescribed value say 5 for β = 50 and R_E = 1 KΩ.

By substituting these values in the above expression for S, the value of R_B = 4.5 KΩ, as shown below.

  Cross multiplication results in the following expression

When this type of biasing circuit is used in a common emitter (CE) transistor amplifier circuit, a capacitor C_E is connected in parallel to R_E, so that A.C. signal has a bypass path through C_E (X_CE = 0.1 R_E) at the lowest frequency of the signal to be amplified and used value for C_E > 10 μf) so as to avoid reduction of effective A.C. input signal at the input port because of feedback of A.C. signal through R_E if C_E is not used

Considering loop ABGA (through V_CC)

Neglecting current I_B through base in comparison to current I through R₁ and R₂.

An equivalent circuit with a Thevenin’s equivalent voltage generator V_Th or V_BB together with between base and ground is drawn in the following Fig. 4.17.

From loop ABGA of the circuit of Fig. 4.14

or,

and,

Above value for R₂ in the equation (4.25) is obtained from the following steps,

Thus, knowing R_E and S, the value of R_B can be calculated using the equation 4.23 and then using the equations 4.24 and 4.25, the values of R₁ and R₂ can be calculated.

By selecting V_cc from transistor ratings, R_L and quiescent or D.C. operating point; R_E can be calculated considering the loop ACEGA

 

Neglecting I_B in comparison with I_C, since h_FE (D.C. Beta) is large; I_E ≅ I_C

Then,                    V_CC = I_C (R_L + R_E) + V_CE

                            V_CC − V_CE = I_C (R_L + R_E)                            (4.26)

This equation is known as D.C. load line equation for voltage divider bias circuit or self-bias circuit. So, the coordinates of the point X on the D.C. load line are V_CE = 0 volts and the coordinates of the point Y are V_CE = V_CC and I_C = 0 mA. This D.C. load line equation superimposed on the output characteristics of the CE transistor specify the required D.C. operating conditions corresponding to the quiescent operating point Q for the required class of operation of the amplifier circuit that are discussed in the discussion of amplifier circuit operation.

4.3 Various Bias Compensation Circuits and their Working

For a transistor to operate as an amplifying device emitter junction is forward biased and the collector junction is reverse biased by one of the three biasing methods using a single D.C. source and a few resistors. But only the potential divider biasing circuit or self-bias circuit provides stable quiescent or D.C. operating point Q for better response of electronic circuits. But there is a loss of gain or amplification due to negative feedback through the resistor R_E in the process of stabilisation of the D.C. operating conditions of the amplifier circuit.

In certain applications, this loss of gain may be put to considerable disadvantage in the operation of the circuit. One of the simplest methods of design of electronic circuits is to counteract the effect of changes in V_BE (may be due to temperature variations or replacement of the active device with another value of cut-in voltage) is to make the emitter voltage V_E very much greater than the required magnitude of the forward bias to the emitter junction. But, some compensation methods or techniques are used to improve the stability of quiescent operating point Q and thus resulting in extremely stable operating point meaning stable D.C. biasing voltages to the emitter and collector junctions of the transistor.

A compensating semiconductor diode D_C applied with forward bias V_F.D is included in the emitter path of the transistor biasing circuit shown in the Fig. 4.17A. The diode to be used for compensation of V_BE should be of the same semiconductor material as the transistor so that the voltage–temperature coefficient is same. When V_BE changes by ∆V_BE with changes in temperature, the voltage across the diode D_C changes by ∆V_D since ∆V_D = ∆V_BE the corresponding changes cancel each other and compensation for changes in temperature takes place.

Diode Compensation for Variations in I_C0   In case of germanium transistors, changes in reverse saturation current I_C0 with changes in temperature cause a corresponding significant changes in the collector current I_C that cause instability of biasing voltages of the transistor decided by the quiescent operating point. This instability is reduced by introducing a germanium diode between the base and the emitter path (the germanium diode is reverse biased by the voltage V_BE of the transistor) for nullifying the increases in the reverse saturation currents with temperature changes as shown in Fig. 4.17B.

Assume the current through the reverse biased diode as I_RD

Then the base current I_B = (I – I_RD)

Using this expression for I_B in the equation for collector current I_C

 

The reverse saturation current I_RD of the compensating diode nullify the variations in I_C0 of the transistor maintaining constant collector current I_C and provide stable operation of the device.

4.4 Thermistor Compensation

Circuit in the Fig. 4.17C shows one method of transistor parameter variation compensation using temperature sensitive resistive elements such as thermistors rather than diodes. The resistance of thermistor devices changes with temperature. They use ceramic like semiconductors with high thermal coefficients of resistance having high sensitivity to temperature variations. Thermistor has a negative temperature coefficient; where the resistance R_T of the device decreases exponentially with increase in temperature. Thermistor is connected in the CE potential divider bias circuit between positive V_CC and the emitter point of the transistor.

As the temperature T rises; the resistance, R_T of the thermistor (due to negative temperature coefficient property of the thermistor) decreases and the current fed through R_T into the emitter resistor R_E increases. Since the voltage drop across R_E is in the direction to reverse bias the transistor emitter-base junction and reduces the collector current to the previous designed value. Thus, the temperature sensitivity of the thermistor R_T acts so as to compensate the change in the collector current I_C due to temperature T, variations in I_C0, V_BE. or Beta β of the transistor.

An alternative configuration using the thermistor compensation is to place the thermistor R_T across the resistor R₂ as shown in the circuit of Fig. 4.17D. As the temperature T increases, the voltage drop across the thermistor R_T decreases and hence the forward biasing base voltage reduced. Hence, collector current I_C decreases and so the increase in I_C due to raise in temperature is nullified. This feature tends to offset the increase in the collector current with temperature.

Example   A common emitter transistor amplifier with voltage divider bias circuit is to be designed. The operating point is chosen to be V_CE = 12 volts and I_C = 2 ma for class A operation of amplifier. Load resistance R_L = 4.7 KΩ. Stability factor S should be ≤ 5.

For Class A operation of amplifier, the quiescent or D.C. operating point is fixed at the middle of the D.C. load line. So V_CE = 0.5 V_cc. From the given data V_CE = 12 volts. So, V_CC = 24 volts

 

Determine the value of R_E, R₁ and R₂

Solution   Since stability factor S = 5 and β = 50

Can be calculated using the expression for S from equation 4.22.

R_E can be calculated from the expression

Substituting the value of R_E = 1.3 KΩ, S = 5; β = 50 in the equation (4.27)

From the circuit

Thermal Runaway and Thermal Stability

In a CE transistor        I_C = βI_B + (β + 1) I_CO              (4.29)

I_CO is reverse current through the base-collector junction, which is reverse biased for active region operation (I_C0 doubles for every 10°C rise in temperature). Since I_CO is temperature dependent, I_c increases with increase in temperature. The increase in collector current I_C increases the power dissipation at collector-junction. This increases the junction temperature causing further rise in collector current. This process becomes cumulative and if proper care is not taken; the transistor gets destroyed, if the transistor ratings of maximum power dissipation are exceeded. The maximum average power dissipation P_Cmax specified by the transistor manufacturers should not be exceeded for its specific application.

This cumulative process or the phenomenon due to self-heating, in which rise in temperature and current chase each other resulting in increased power dissipation P_C, is called thermal runaway and can be prevented by proper biasing for low power circuits and by using heat sinks for transistors operating at large powers.

Before proceeding further, some criteria have to be defined. In this context a term called thermal resistance θ is defined below.

The power dissipation P_C in watts at the collector junction is proportional to variations in temperature at the collector junction with reference to ambient temperature i.e. (T_J – T_A). The temperature rise at the collector junction is proportional to the power dissipation at the junction.

 

where, T_J = junction temperature in °C

      T_A = ambient temperature in °C

The proportionality between P_c and (T_J – T_A) can be converted into an equality by introducing a constant θ so that

 

where, θ is called the thermal resistance and has a dimension of temperature in °C per watt of power dissipation. The size of the transistor and the device heat transfer methods to surroundings determine the magnitudes of thermal resistance.

Differentiating with respect to

This gives the relation between the thermal conductivity and power dissipation change dP_C with respect to junction temperature change dT_j.

As long as

This condition must be satisfied to prevent thermal runaway and to safe guard the device.

If thermal conductivity is more than the rate of power dissipation with respect to temperature, thermal runaway is prevented. This can be justified as follows, more thermal conductivity means carrying away the heat from the transistor junction into the surroundings as quickly as is generated. As long as the heat is radiated away, thermal runaway is prevented. If it is not possible to directly radiate away heat by having proper ventilation; special heat sinks, which carry away the heat have to be designed.

In one configuration the device is enclosed (embedded) in the heat sink. Other configurations of heat sink designs are also possible for example in power transistors. The collector is connected to the case of the transistor, and can be fixed on a heat sink insulated from the ground.

In low power devices, thermal runaway can be prevented by careful selection of the quiescent or D.C. operating point. The power generated at the collector junction P_CJ under no excitation signal condition is the product of I_CQ and V_CEQ

where                    V_CEQ = V_CC − I_CQ.(R_L + R_E)

∴                            P_CJ = V_C.EQ × I_CQ                                (4.35)

Also,                        P_CJ = V_ccI_CQ − I²_CQ(R_L + R_E)                (4.36)

where V_CC.I_CQ is the D.C. power supplied by the D.C. source V_CC. A part of this power is consumed as power dissipation P_dC in the resistors R_L and R_E.

 

from equation (4.29), the condition to prevent thermal runaway is

But

And is 7% per °C. This is because I_CO doubles for every 10 °C rise in temperature or in other words, I_CO changes by 7% per °C for both silicon and germanium transistors.

That is,                

Therefore, it can be written that

This condition can be applied to the equation for the power

 

Differentiating P_CJ with respect to I_CQ

[For class A amplifier with R_L, the resistive load V_CEQ = I_CQ (R_L + R_E)]

 

For class A amplifier with resistive load,

∴ V_CEQ = 2.V_CEQ − I_CQ (R_L + R_E) and therefore, V_CEQ = I_CQ (R_L + R_E)}

For this inequality to be satisfied, it requires that V_CC – 2V_CEQ is positive so that . This is the biasing condition requirement to avoid thermal runaway. That is, the operating point is not chosen at ; but such that . This, of course, reduces the possible signal swing and the circuit is under utilised; but this ensures safety against thermal runaway.

However, when high power transistors are involved, this simple manipulation does not work and design of proper heat sinks becomes a must.

4.5 Small Signal Low Frequency Amplifier

An amplifier can be considered as a two-port (four-terminal) network, with conveniently defined parameters, which find practical use. For instance, for a transistor, the hybrid parameters are useful for the design of transistor circuits. Transistor is basically a current amplifier but natural sources are voltage type in nature. So, the following expressions are used to represent the input and output relations.

Considering the transistor as shown in the Fig. 4.19

 

 

Putting the above equations in matrix form

As can be seen later, the parameters h₁₁, h₁₂, h₂₁ and h₂₂ do not contain same units; h-parameters are known as hybrid parameters.

From the above equation, by applying some boundary conditions, h-parameters can be obtained. If in equation (4.40) and (4.41), V₂ is made zero, that is, output port is short-circuited.

h₁₁ has the dimensions of a resistance and pertains to the input port and it can be termed input resistance h_i represented by The unit of input resistance h_i is ohms.

In the same way,                    

h₂₁ is a dimensionless quantity representing the ratio of output current to input current or current gain. This is represented by and is called forward current gain h_f. It is a dimensionless quantity.

Now, by making I ₁ = 0 or open circuiting the input port; two more parameters are obtained as following.

h₁₂ is a reverse voltage transfer ratio and is named h_r. It is a dimensionless quantity and gives an idea as to the voltage that appears across the input port. This in fact, represents the unwanted voltage transfer from the output to the input, since amplifiers should be preferably unilateral in transfer of energy from input into the output ports, but not the other way round.

Finally,                    

h₂₂ represents the admittance of the output port and is designated as output conductance, h_o. h_o is measured in mhos or Siemens.

Thus, as the h-parameters possess a mixture of units, and hence are known as hybrid parameters.

When applied to analysis of amplifiers with alternating signals V₂ = 0 and I₁ = 0 represent constant D.C. values of voltage at the output port and current at the input port. Since the transistor characteristics are not entirely linear, the values of the h-parameters change from point to point and are defined over small linearised regions and hence are called small signal parameters.

In this context, input resistance

Forward current gain

Reverse voltage transfer ratio

Output conductance

Transistor amplifiers can have three configurations with any one of the terminals grounded. The other two terminals forming the input and output terminals subjected to the original definition.

So, three sets of h-parameters are obtained with the second subscript to the h-parameters, designating the grounded terminal.

So for CE configuration of transistor, the h-parameters become h_ie; h_fe; h_re and h_oe.

For common base transistor configuration, these parameters are h_ib; h_fb; h_rb and h_ob.

For common collector transistor configuration, the h-parameters are h_ic; h_fc; h_rc and h_oc.

All these parameters can be determined from the static characteristics of the transistor as described in the device chapter.

The different sets of parameters are inter related and inter convertible.

For instance,

or,

Similarly,

or,

For common collector parameters;

∴                        h_fc = (1 + h_fe) or (1 + β)                            (4.48)

h_ic and h_oc are equal to h_ie and h_oe, respectively.

Comparison of CE, CB, CC Configurations of Transistors   Between CE, CC and CB transistor configurations as per chosen directions of positive and negative polarities, CE transistor configuration is considered to be an inverting voltage amplifier, whereas for the same chosen polarities, CB and CC configurations form non-inverting amplifiers.

Common emitter transistor configuration has input impedance h_ie of the order of 1 K Ohm and output impedance is of the order of 40 K ohms.

For common base configuration the input impedance h_ib will be of the order of a few ohms 10 to 20 ohms and has output impedance of the order of 2 M Ohms.

CB transistor configuration has a reasonable voltage gain but current gain h_fb or α is less than unity. (I_C (output current) < I_E (input current)).

Common collector transistor configuration (CC) has a current gain of h_fc = (1 + h_fe) but the voltage gain is less than unity (as will be explained later it forms the voltage series negative feedback amplifier with feedback factor = 1).

Common emitter (CE) transistor amplifier is neither a true current amplifier nor a voltage amplifier, but a bit of both.

Common base transistor amplifier is an almost ideal current controlled current generator, since its input impedance is low and can be connected to a current source. Since its output impedance is high it can act as a current source, that is, in effect a current controlled current source.

CC configuration due to unity feedback factor has very high input impedance and very low output impedance and can act as a voltage controlled voltage source.

Although the active devices BJTs and FETs have different bases of physical operation, once their circuit models replace these devices, their frequency response and other features can be analysed simultaneously. The following h-parameter model is for bipolar junction transistors.

Analysis of Amplifiers using h-Parameter Models

Just like equations can be framed for circuits, circuits can be formed from equations. Considering the equations

                                V_in = h_i.i_in + h_r.V_out

                                I_out = h_f.i_in + h0.V_out                    (4.49)

The following circuit of Fig. 4.20 can be shown with the h-parameters representing the above equations

When Z_L is connected across the output port, a current I_L flows in Z_L. Therefore.

 

The current gain A_i is by definition

From the circuit of Fig. 4.20; i_out = h_fi_in + h_o(– i_outZ_L)

From the equation (4.49)

But                       V_out = − i_out Z_L            (4.55)

Since

The input impedance,

A_V. the voltage gain by definition is equal to

From the Fig. 4.18; V_out = – I_out Z_L

To find Z_o which is defined as

Dividing throughout by V_out

From Fig. 4.21 with    V_S = O;h_r V_out = − (R_s + h_i) × I_in

The amplifier performance can be completely assessed by the four basic relations for A_I, A_V, Z_I and Z_out obtained previously. The expressions for these relations together with comparison are summarised in the following Table.

Typical values of transistor h-parameters are as follows:

 

Example 1   Find the values of A_I; A_v, A_VS, A_IS; Z_i; & Z_o for the following circuit.

 

                h_fe = + 50; h_ie = 1 K Ω; h_re = 4 × 10^–4; h_oe = 25 × 10^–6 mhos

Since            R_C = 2 KΩ and R_L = 10 KΩ

The effective load Z_L for amplifier =

A_vs refers to voltage gain taking the signal source resistance R_s into consideration

A_Is refers to current gain taking R_S into consideration.

Example 2   Find all the following quantities A_I; Z_i; A_V and Z_O for the following common base transistor amplifier. h_fb = – 0.99; h_ib = 20Ω h_rb = 2 × 10^–4 h_ob = 0.5 × 10^–6 Siemens.

       h_0b. Z′_L = 0.5 × 10^–6 × 1.6 × 10³ = 8 × 10^–4

  1 + h_0b. Z′_L = 1 + 8 × 10^–4 = 1.0008

Current Gain

From the above calculations for the common base transistor amplifier, the amplifier gain is less than one. The input impedance Z_in is only a few ohms and the output impedance Z_out is very high and is of the order of megaohms. The reasons for such behaviour of common base amplifiers are well discussed in discussing the common base transistor characteristics. Common base transistor amplifier is a non-inverting amplifier.

Example 3    Find A_I, Z_i, A_V, and Z_o for the following common collector amplifier circut. Data: R_S = 1 Kohms, Z_L = 3.3 Kohms; h_fc = 51; h_0C = 25 × 10^–6; h_rC = 1 and h_iC = 1 Kohms

Small Signal Low Frequency Model for a Common Emitter Transistor Amplifier

In the following circuit R₁ and R₂, V_CC; R_E and R_C provide forward bias to emitter junction and reverse bias to collector junction of the transistor to keep the transistor in the active region. R_E provides bias stabilization. R_C forms the D.C. load. The collector supply voltage V_CC, R_C and R_E are so chosen to keep the operating point for class A operation.

Mostly, voltage amplifiers are CE type and use resistive loads and operate under class A condition. The input impedance for various values of load resistances and the output impedance for various values of source resistance for CE transistor operation will be fairly constant. CE transistor amplifier configuration is normally preferred.

Between base and emitter; voltage across R₂ and voltage across R_E are such that V_BE = V_R2 – V_RE For an N-P-N transistor, V_R2 > V_RE to satisfy the forward bias condition, that is, base should be more positive with respect to the emitter

V_BE forward biases the base to emitter junction of the transistor. Input signal V_s is an alternating signal source in nature that is connected to the input port of the amplifier. Input signal V_s is coupled to the base through a coupling capacitor C_Cin or C_in or C_C or C_b. Thus, the capacitor C_in blocks the D.C. bias V_BE from entering the signal source; but allows A.C. signal into the input port. X_{Cc iput} should be as small as possible compared to Z_in and if this is not possible Z_in should be at least 10 times larger than

Instantaneous voltage,

neglecting the source resistance R_S. The above equation requires that X_Cin → zero; Then, maximum voltage will be available between base and the emitter. The series coupling capacitors are so selected as to act as short circuits to A.C. signals, while they act as open circuit for D.C. biasing voltages (of individual stages to be adjusted independently in cascaded amplifiers). Capacitor C_E across R_E should have a reactance less than of the magnitude of R_E at the lowest frequency of the signal base band to be amplified. This is justified since; the reactance is maximum at the lowest frequency and decreases with increasing frequency. Once it is an effective short circuit at lowest frequency of the signal to be amplified, it is more effective short circuit at all higher frequencies. C_E keeps the emitter grounded (for common emitter transistor configuration) for A.C. signals. Similarly, C_out or C_Cout or C_b or C_C should become perfect short circuits for A.C. signals and perfect blocks for D.C.; so that A.C. and D.C. voltages are well separated.

Now, the A.C. input signal V_in is super imposed on the D.C. bias V_BE and the instantaneous voltage V_be will be

 

where V_be is effective changing D.C. between base and the emitter. This causes the base current to vary sinusoidally and the collector current likewise varies from its quiescent value between I_CQ – I_Cmin and I_Cmax – I_CQ. This varying collector current develops a voltage across the resistance R_C that again varies between V_{C max} and V_{C min}. To avoid notational ambiguity the following quantities are defined below.

V_be varying voltage between B and E is the sum of D.C. bias V_BE and instantaneous value of the super imposed A.C. signal V_m sin ωt.

V_be = instantaneous value of the superimposed signal

V_BE the operating quiescent bias between B and E, V_R2 – V_E = V_BE.

Since the output required is A.C. it is developed across R_C. Due to this presence of R_L the effective load resistance R’_L becomes R_L║R_C for the purposes of calculation of gain and so on.

Though it is convenient for analysis to consider C → ∝; no more than the value needed to make are used.

Otherwise, the initial charging current of the capacitance may exceed the maximum rated current of the device and the device blows of.

Determination of frequency response of a common emitter transistor amplifier   To determine the frequency response of an amplifier a function generator (signal generator) is connected to the input terminals of the amplifier. The input signal is also connected to channel one of a CRO to measure the input signal amplitude V_in and observe the wave form. The output signal obtained at the output port is connected to the second channel of the CRO to measure the amplitude V_out and to observe the waveform of output signal. The voltage gain A_V of the amplifier is ; and Voltage gain in db = 20 log₁₀ . The magnitude of V_in is maintained constant and by changing the frequency of the input signal in convenient steps; the output voltage V_out is measured. The results are tabulated as following

Frequency response of the amplifier is plotted on a semi-Log graph sheet with the X-axis representing logarithm of frequency and on the Y-axis voltage gains A_V

It will be observed from the frequency response plot of the amplifier that starting from D.C. frequency; the gain increases with frequency (low frequency region) and enters the knee region, remains almost flat over a range of frequencies (midrange frequencies) and starts falling off with frequency at high frequency region.

The response of the human ears is logarithmic in nature. (For this reason only decibel (db) gain is defined). Even if power of the signal reaching the human ear is reduced to half, it feels only a slight difference in amplification. Between these two power levels, the human ear cannot differentiate (3-db). So, between the two frequencies f₁ (f_L) and f₂ (f_h): the power is at least half of the maximum power. These two frequencies and the range between them (f₂ – f ₁) or (f_h – f_L) is called as bandwidth (B.W) of the amplifier. Between these two cut-off frequencies or corner frequencies the response of the amplifier is considered to be uniform.

In voltage relationships; the 3-db point refers to of A_V mid (0.707 A_mid) where, A_Vmid is the maximum gain A_Vmax in the flat region of the response characteristic. This flat response region is known as midfrequency region of the amplifier response.

Reasons for fall of gain at low frequency (the combined effect of C_in, C_E and C_out).

As the frequency increases, reactance of these capacitances decrease and in the flat region and beyond, they are virtual short circuits. Up to the flat frequency region the equivalent of a CE amplifier acts as a high pass filter with f₁ as cut-off frequency, since high pass filter has stop band region up to f₁, beyond which it has the pass band.

Reason for Fall of Response at High Frequencies.   R_L is the load resistance in the circuit of the appliance connected to the amplifier, which is to receive only the A.C. output from the amplifier. Every appliance will have two terminals with a potential difference across them and so possesses a capacitance. This is represented as a capacitance C_sh, across the resistance R_L.R_L together with the capacitance across it could be the input impedance shunted by its input capacitance of a two-port network connected across the output terminals of the amplifier. This represents a low pass filter with a cut-off frequency of f_h or f₂ and up to f₂ it is the pass band and beyond which it has stop band, that is, up to f₂, all higher frequencies.

C E Amplifier Equivalent Circuits for Mid-frequency, Low Frequency and High Frequency

The exact equivalent circuit for a simplified common emitter model (h_re = h_oe = 0) is shown in the following Fig. 4.35.

At mid-frequencies, the circuit is redrawn as follows, since the series capacitances are short circuits and the shunt capacitance is open circuit. Mid-frequency equivalent circuit is in Fig. 4.36,

Low Frequency Equivalent Circuit   The circuit of Fig. 4.37 can be redrawn as shown in Fig. 4.38

where,

From this equation, it is found that at frequency f = f₁

Thus, f₁ is the lower half-power frequency or low frequency Cut-off point.

High frequency equivalent circuit

The circuit in Fig. 4.39 is redrawn as shown in the Fig. 4.40.

where

at

So, f₂ is the upper half power frequency. And, the bandwidth (B.W.) is (f₂ – f₁) but f₁ << f₂ so bandwidth ≅ f₂. f₁ is dependent on the series combination of R_C and R_L together with C_C.f₂ is dependent on the parallel combination of R_C and R_L together with C_Sh.

In the first case, if C_C becomes large; f₁ will be reduced while if C_Sh is large, f₂ will be reduced. Larger the value of C_C smaller is f₁ and smaller the value of C_Sh; larger is the f₂. So, for maximum bandwidth C_C should be as large as possible and C_Sh should be made as small as possible.

4.6 Emitter Follower

Emitter follower is another form for a common collector amplifier, since the collector is at A.C. ground as can seen from the circuit of Fig. 4.41. The name emitter follower arrives from the fact that the output voltage across the resistor R_E in the emitter circuit is almost equal to or slightly less than input base-ground voltage (i.e. base-collector voltage). (Emitter voltage follows the changes in input signal voltage). The characteristic features of emitter follower are as following. The voltage gain is less than unity with no phase inversion between the input and the output signals. It has a high input impedance and low output impedance making it an ideal voltage controlled voltage source and is commonly used for impedance transformation over a wide range of frequencies. The circuit has relatively high current gain and power gain.

h-Parameter Model A.C. Equivalent Circuit of Emitter Follower

h-parameter model A.C. equivalent circuit of emitter follower is drawn with an assumption that h_re = h_oe ≅ 0 so that = ∞. That is, an open circuit and so the circuit component parallel to the output current source is omitted in the equivalent circuit of Fig. 4.42. Further, in the following analysis, the effect of R₁ and R₂ is not considered. The effect of R₁ and R₂ is to reduce the input impedance Z_if to Z_if because of the effect of R₁ and R _2′

The input impedance Z_in has been enhanced by an amount [(1 + h_fe).R_E]

                         V_in = h_ie.I_B + (1 + h_fe).I_B.R_E

But,                     V_out = I_E.R_E = (1 + h_fe).I_B.R_E

∴ Voltage Gain

Output impedance Z₀ across the output terminals is by definition Z₀ = ; where, V is the open circuit voltage across the output terminals and I is the short circuit current. When the emitter is open, the open circuit voltage V₀ is V_in = I_B.h_ie. The short circuit current I_SC = I_E and I_SC = I_E and I_SC = I_E = (1 + h_fe).I_B

Then, the output impedance Z₀ is , a low value when compared to the input impedance Z_in where, ⌊ h_ie + (1 + h_fe).R_E⌋ which is relatively very large.

Example on emitter follower circuit   For the following emitter follower circuit of Fig. 4.43; R₁ = R₂ = 20 KΩ; h_ie = 1 KΩ; h_fe = 100; R_E = 5 KΩ, neglect the effect of h_oe. Determine the input impedance Z_in; Z′_in; output impedance Z₀ and Z’₀ and voltage gain A_V.

4.7 Junction Field Effect Transistor (JFET) Amplifiers

To provide the necessary negative voltage V_GS, better biasing scheme is voltage divider biasing, where R₁ and R₂ form a voltage divider together with R_S and the supply voltage V_DD provides a negative voltage at the gate of the JFET device as shown in the Fig. 4.44.

For a specified Q point of JFET amplifier circuit (I_D, V_GS) and chosen values of V_GN and R_G, the required values of R₂; R₁ and R_S are easily calculated from

Furthermore, the effect of any shift in V_GS is reduced by making | V_SN | large compared to | V_GS |.

Example   The JFET is to be operated at a quiescent point defined by I_D = 4 mA. V_DS = 8 V and V_GS = – 2 V. Design an appropriate biasing circuit with V_DD = 30 volts.

Solution   Using the voltage divider bias circuit, assume V_GN = + 12 volts, so that V_GN – V_GS = V_SN is large compared to V_GS for stability. That is, the effect of any shift in V_GS is reduced.

Assume R_G = 6 M Ω to keep the input resistance high.

Then,                V_SN = I_DR_S = V_GN – V_GS = 12 – (– 2) = 14 volts

Summing voltages around the drain loop yields ∑V = 0 i.e.V_DD – I_D.R_D – V_DS – I_DR_S = 0

For V_DS = 8 volts (from the data of the given Q point (Quiescent operating point))

Thus, the magnitudes of component values of R₁; R₂; R_S and R_D are estimated based on the given data of the D.C. equivalent circuit of common source JFET amplifier.

Small signal low frequency model of a FET device   A small signal to an amplifier input is one to which a given device responds in a linear fashion. The following equivalent circuits are discussed for small signal low frequency operation of the FET amplifier. During the discussions on the characteristics of the FET devices, the significance of drain resistance r_d as the device internal resistance and transconductance g_m from the transfer characteristics of the device are clearly explained

The FET device parameters g_m, r_d and μ allow an A.C. equivalent circuit for field effect transistor (FET) just like a BJT.

In the Fig. 4.47 irrespective of the configuration common source, common gate and common drain amplifier (similar to h-parameter equivalent circuit for CE, CB and CC configurations of BJT), the active device FET can be represented by a derived voltage source μV_GS with the shown polarity between source and drain in series with the drain resistance r_d.

Alternate representation for FET amplifier equivalent circuit is shown in Fig. 4.48.

Common Source FET Amplifier

In the Fig. 4.49, V_DD, R_S – C_S, R_G and R_D provide the required biasing voltages to the FET device for the required class of operation of the amplifier and in this case for a linear amplifier, class A amplifier for small signal and low frequency operation. The input signal voltage V _in is applied between the gate and the source. The A.C. signal output voltage V₀ is developed across the drain circuit resistance R_D. C_Cout is the blocking capacitor, which blocks the D.C. from the drain to source of the FET to the output load or next stage of amplifier as the case may be and also acts as the coupling capacitor that couples or allows A.C. output signal voltage to the load. On similar lines, C_Cin has dual roles of acting as a blocking capacitor, which prevents the D.C. from entering the driving source, and couples the input signal voltage to the input port between the gate and source of the FET device. R_G is the gate leak resistance or gate resistor to provide high input impedance as well as a leakage path for the capacitance to discharge. R_G also provides the connecting path for the D.C. bias developed across the source resistance R_S to be applied to the input terminal, the gate. R_S provides the necessary bias and C_S provides bypass path for A.C. signals (around R_S) to make the source at the ground potential (and also eliminates feedback to the input port), justifying the common source configuration or common source operation of the FET amplifier as shown in Fig. 4.50.

The above circuit shown in the Fig. 4.50 is the small signal low frequency A.C. equivalent circuit of a common source FET amplifier. The following rules have to be followed while drawing the A.C. equivalent circuit:

1. The FET device is replaced by a controlled voltage source of μV_GS with the indicated polarity in series with the drain resistance r_d between the source and the drain terminals. The gate terminal is left free and can be connected to points depending on the actual components in the circuit.
2. No other component can be replaced and they have to be represented in tact depending upon the actual circuit.

Thus, for the actual common source FET amplifier circuit of Fig. 4.49, the A.C. equivalent circuit is shown in Fig. 4.50.

At above the frequencies when X_Cci << R_G and X_Cco << R_L and X_Cs << R_S, the above circuit gets simplified as shown below in Fig. 4.51.

The voltage gain A_V; Z_in and Z_out can be calculated using the conventional network methods. By inspection of the equivalent circuit in Fig. 4.50, it can be seen that V_GS = V_S at the input port of the amplifier. In the output port applying Kirchoff’s Voltage Law to the loop SDS from the source to drain and then back to source.

μ.V_S + I_D.r_d + I_D.R_d||R_L = 0

or,

An alternate approach is to replace the FET by its Norton’s equivalent circuit as shown in the following Fig. 4.52.

The input impedance Z_in = R_G and Z_out = R_eQ = r_d ║ R_d ║ R_L

Thus, the input impedance and the output impedances remain the same.

For maximum voltage gain A_V it requires that r_d << R_d║ R_L. Then, the maximum value of the voltage gain will be approximately equal to μ.

This is the maximum theoretical gain one can ever realise from the FET amplifier circuits.

The common source mode FET amplifier is the most popular circuit in applications.

Common Gate FET Amplifier Circuit

The following is the circuit of a common gate amplifier. The gate is grounded and the driving signal source is connected in the source lead terminal. The load resistance R_d in the drain path and the external load resistance R_L are connected between the drain and the gate electrodes as shown in the following Fig. 4.53

Common gate FET amplifier circuit with self-bias arrangement is shown in the Fig. 4.54.

When C_Cin = C_Cout = C_S are all so large as to make their reactances negligible compared to the resistances R_in, R_out and R_s the following equivalent circuit in Fig. 4.54 is drawn.

From the equivalent circuit of Fig. 4.55, it is clear that V_GS = V_S.

On the loop DSGD in the Fig. 4.55,

                 –V_s + μ.V_GS + I_D (R_d + r_d) = 0

But                                                 V_GS = –V_S

∴                   –V_s – μ.V_S + I_D. (R_d + r_d) = 0

But,

∴ Voltage Gain

The voltage gain A_V is almost the same as for common source model FET amplifier with no inversion between the input and the output voltages. Thus, this common gate amplifier is a non-inverting amplifier with a gain derived as

But the input impedance Z_in of the common gate amplifier will be very low as seen from the following equation

If r_d >> R_d, then

4.8 Common Drain FET Amplifier (Source Follower)

When the drain terminal is common to both the input port and the output port of the FET amplifier, the circuit is called as common drain FET amplifier or the source follower.

The source follower just like the emitter follower is an impedance matching network. It provides a low output impedance so as to make this an almost ideal voltage source. Thus, the total amplifier works as an ideal voltage controlled voltage source.

The common drain FET amplifier has the input voltage V_IN between gate and the common drain and the output voltage V_OUT is available between the source and the common drain terminals of the FET device. The output voltage is developed due to the flow of the drain current I_d through R_S. Therefore, V_S = I_d. R_S. The output voltage and the input voltages will be in phase, which can be seen from the directions and polarities of the input signal voltage and the output voltages. The output voltage V_OUT at the source terminal (source voltage) follows the input signal changes at the gate terminal of the amplifier. So, this common drain amplifier circuit is also known as source follower circuit. Since the output voltage of the source follower circuit is almost equal to the input voltage, the gain of the source follower is approximately unity.

From Fig. 4.57 V_GS = V_in – I_D·R_S and also

                                    −μ.V_GS + (r_d + R_S).I_D = 0

∴                    −μ(V_in − I_D.R_S) + (r_d + R_S).I_D = 0

                         −μ.V_in + I_D[(r_d + R_S(μ + 1)] = 0

or,

Output voltage

V_out can be written as V_out =

∴ Voltage Gain

Also, Voltage Gain

∴ Voltage Gain

Therefore, the voltage gain, A_V of a common drain FET amplifier is close to unity, similar to the emitter follower circuit.

From the equation I_D = we can draw a circuit as shown in the Fig. 4.59.

The circuit represents a controlled source with voltage in series with an impedance driving a load resistance R_S.

Thus, the controlled source impedance or the so-called output impedance Z_out or the output resistance R_out of the source follower is

It is interesting to note that the output impedance of the source follower is the same as the input impedance of the common collector transistor amplifier (emitter follower) that is .

Thus, the source follower acts as a unity voltage gain non-inverting amplifier with a very low source impedance of of or acts as an ideal voltage controlled voltage source. Further, it has got

large bandwidth to have good frequency response (from the concept of the product of gain and bandwidth of amplifiers is constant) and stable operation due to inherent negative feedback in the amplifier operation.

Further, the high input impedance Z_in of the source follower circuit is used in measuring instruments when loading on the input signal sources is to be minimised. One of the applications is at the input stages of amplifiers used in cathode ray oscilloscopes.

Unity gain of the source follower and impedance transformation feature, that is, the very low output impedance Z_OUT and high input impedance Z_IN feature of the source follower circuit is used as Unity Gain Buffer Amplifier in instrumentation circuits.

Example   A common source FET amplifier has r_d = 36 KΩ; μ = 50; R_d = 4 KΩ. Calculate the voltage gain A_V using the given data for the common source FET amplifier.

Solution

Voltage Gain

Example   For a common gate FET amplifier circuit, μ = 50, R_d = 2 KΩ and r_d = 38 KΩ, calculate the voltage gain A_V.

Solution   The voltage gain of common gate FET amplifier A_V

Example   The common drain FET amplifier circuit is shown in the following Fig. 4.62. The FET device has μ = 50, r_d = 46 KΩ; g_m = 2 millimhos. R_S = 4 KΩ and R_G = 1 MΩ in the circuit. Calculate the voltage gain A_V for the amplifier and the output resistance of the amplifier.

Solution   The voltage gain A_V of the common drain FET amplifier circuit is given by the following expression,

Output resistance

Solved Examples

Example 1   Draw the circuit diagram of self-biasing circuit for a germanium transistor. Data: V_CC = 20 V; R_C = 2 K; R_E =100 ohms. R₁ = 100 KΩ; R₂ = 5 KΩ; β = 50.

In the potential divider bias circuit of Fig. 1, V_CC in association with R₁ and R₂ provide the bias and R_E provides bias stability as is explained.

Determination of I_CQ and V_CE.Q and stability factor S

Solution

Stability factor

Voltage across

∴ voltage V_RE across R_E = V_R2 – V_BE = 0.95 – 0.3 = 0.65 V (using V_BE = 0.3 V)

∴                    

Collector to Emitter Voltage V_CEQ = [V_CC – I_C.Q.(R_C + R_E)]

V_C.E.Q = [20 – 6.5 × 10^-3(2 × 10³ + 0.1 × 10³)] = [20 – 13.65] = 6.35 volts

Example 2   Discuss the concept of thermal runaway phenomenon in transistors

In a CE transistor                I_C = βI_B + (β +1) I_CO                        (1)

I_CO is reverse current through the base-collector junction, which is reverse biased for active region operation (I_C0 doubles for every 10°C rise in temperature). Since I_CO is temperature dependent, I_c increases with increase in temperature. The increase in collector current I_C increases the power dissipation at collector-junction. This increases the junction temperature causing further rise in collector current. This process becomes cumulative and if proper care is not taken; the transistor gets destroyed, if the transistor ratings of maximum power dissipation are exceeded. The maximum average power dissipation P_Cmax specified by the transistor manufacturers should not be exceeded for its specific application.

This cumulative process or the phenomenon due to self-heating, in which rise in temperature and current chase each other resulting in increased power dissipation P_C, is called thermal runaway and can be prevented by proper biasing for low power circuits and by using heat sinks for transistors operating at large powers.

Example 3   Explain the phenomenon for thermal runaway.

The power dissipation P_C in watts at the collector junction is proportional to variations in temperature at the collector junction with reference to ambient temperature, that is, (T_J – T_A).

 

where, T_J = junction temperature °C in and T_A = Ambient temperature in ° C.

The proportionality between P_c and (T_J – T_A) can be converted into an equality by introducing a constant θ so that

 

where, θ is called the thermal resistance and has a dimension of temperature in °C per watt of power dissipation. The size of the transistor and the device heat transfer methods to surroundings determine the magnitudes of thermal resistance.

and,

Differentiating with respect to T_J;

This gives the relation between the thermal conductivity and power dissipation change dP_C with respect to junction temperature change dT_j as long as

This condition must be satisfied to prevent thermal runaway and to safe guard the device.

Example 4   Derive the condition for thermal stability.

For class A amplifier with resistive load,

∴            V_CEQ = 2V_CEQ − I_CQ(R_L + R_E) and therefore, V_CEQ = I_CQ(R_L + R_E)

But,            P_CJ = V_CCI_CQ − I²_CQ (R_L + R_E)

Condition to avoid thermal runaway

For this inequality to be satisfied, it requires that V_CC – 2V_CEQ is positive so that V_CEQ < . This is the biasing condition requirement to avoid thermal runaway. That is, the operating point is not chosen at V_CEQ = ; but such that V_CEQ < .

Example 5   Data: N-P-N transistor in CE mode. V_CC = 10 volts. R_C = 2 KΩ and R_B. = 100 KΩ. Calculation of quiescent point and S for CE transistor with collector to base bias.

Stability Factor

Example 6   Mention the three methods of Biasing the CE transistor.

The three methods of biasing the transistors to fix up the quiescent operating point

(1) fixed bias or base bias circuit.

The choice of V_CC; R_L and R_B is made such that forward bias V_BE is provided to emitter junction and V_CE provides the required reverse bias to the collector junction for the transistor to be operated as an amplifying device. In addition, V_CC should always be less than V_{CE max}, as prescribed by the specifications given by the manufacturer of the active devices.

(2) collector to base bias circuit

In this circuit of Fig. 2, resistor R_B is now connected between collector and base. It can be seen that stability of the quiescent operating point Q is improved. But this circuit is rarely used or obsolete now because of feedback through R_B connecting the input and the output ports of the device. For the collector to base bias circuit in Fig. 2. (loop ACBEA)

 

(3) Potential divider bias or voltage divider bias or self-bias circuit.

This potential divider bias circuit is now used in most of the applications as the circuit operation is more stable due to maintenance of stable quiescent operating by the Emitter resistor R_E.

Example 7   Draw the circuit diagram of a common emitter transistor amplifier with self-biasing arrangement. Draw the h-parameter equivalent circuit of the amplifier. Derive the expressions for current gain A_I; input resistance R_IN; voltage gain A_V and output resistance R_O using the h-parameter equivalent circuit.

Solution   Circuit diagram of a CE transistor amplifier circuit with self-bias is shown in Figure 1.

ANALYSIS OF AMPLIFIERS USING h-PARAMETER MODEL

Just like equations can be framed for circuits, circuits can be formed from equations. Considering the equations

                                    V_in = h_i.i_in + h_r.V_out

                                    I_out = h_f.i_in + h0.V_out                    (1)

The following circuit of Fig. 2 can be shown with the h-parameters representing the above equations

Derivations

When Z_L is connected across the output port, a current I_L flows in Z_L. Therefore,

 

The current gain A_i is by definition

From the circuit of Fig. 2;         i_out = h_f i_in + h_o (–i_outZ_L)

From the equation (6)

But,

Since

The input impedance

A_v the voltage gain by definition is equal to

From the Fig.

To find Z_o which is defined as

with        V_S = O, h_rV_out = − (R_s + h_i) × i_in (from figure 3)

Example 8   Calculate current gain; voltage gain; R_N and R_OUT using the following data

    Data: h_f.e = 36; R_L = 2 × 10³ and h_o.e = 2 × 10^–6; h_i.e = 1200 Ω. h_r.e = 0. And R_S = 500 Ω.

Solution   Determination of current gain; A_I

Determination of voltage gain; A_V

Determination of input resistance; R_IN

R_IN = Z_IN = h_i.e + A_I.h_re.Z_L is approximately = h_i.e as h_r.e = 0.; Therefore R_IN = h_i.e = 1200 ohms.

Determination of Output resistance; R_O

Example 9   Draw the circuit diagram of a JFET amplifier using potential divider bias and its D.C. equivalent circuit. Draw similar circuits using enhancement MOSFET device.

Solution   Biasing circuit suitable for JFET.

To provide the necessary negative voltage V_GS, better biasing scheme is voltage divider biasing circuit, where R₁ and R₂ form a voltage divider together with R_S and the supply voltage V_DD provides a required negative voltage (according to the design of class of operation of the amplifier) at the gate of the JFET device as shown in the Fig. 1 and 2

For a specified Q point of JFET amplifier circuit (I_D, V_GS) and chosen values of V_GN and R_G, the required values of R₂; R₁ and R_S are easily calculated from

Furthermore the effect of any shift in │ V_GS │ is reduced by making │ V_SN │ large compared to │ V_GS. │. The same potential divider bias circuit can be used to enhancement MOSFET device amplifier circuit as shown in the Fig. 3. and also its D.C. equivalent circuit of Fig. 4 provides more clarification for the method of biasing. For DE MOSFET it needs two types of polarity voltages and this circuit is not suitable.

Example 10   Draw the circuits of common collector amplifier and its h-parameter equivalent circuit. Derive the expressions for current gain A_I, voltage gain A_V, Z_lN and Z_OUT for the common collector amplifier circuit.

Solution   Common collector transistor amplifier (emitter follower circuit).

Common collector amplifier circuit is also known as emitter Follower circuit, since the collector is at A.C. ground as can be seen from the circuit of Fig. 1. The name emitter follower arrives from the fact that the output voltage across the resistor R_E in the emitter circuit is almost equal to or slightly less than input base-ground voltage (i.e. base-collector voltage) (emitter voltage follows the changes in the input signal voltage). The feedback factor β is unity as the voltage across the resistor R_E is entirely feedback to the input port of the amplifier. The characteristic features of common collector amplifier are as following. The voltage gain is less than unity with no phase inversion between the input and the output signals. It has a high input impedance and low output impedance making it an ideal voltage controlled voltage source and is commonly used for impedance transformation over a wide range of frequencies. The circuit has relatively high current gain and power gain.

h-parameter model AC equivalent circuit of common collector amplifier.

h-parameter model A.C. equivalent circuit of common collector amplifier (emitter follower) is drawn with an assumption that

h_re = h_oe ≅ 0 So that = ∞. That is, an open circuit and so the circuit component parallel to the output current source is omitted in the equivalent circuit of Fig. 4.42. Further, in the following analysis, the effect of R₁ and R₂ is not considered. The effect of R₁ and R₂ is to reduce the input impedance Z_if to Z’_if because of the effect of R₁ and R₂

                    Z’_if = Z_if ║ (R₁║R₂)

    –V_in + h_ie.I_B + I_E.R_E = 0

∴                  V_in = h_ieI_B + (1 + h_fe).I_B.R_E using [I_E = (1 + h_fe). I_B]

The input impedance Z_in has been enhanced by an amount [(1 + h_fe). R_E]

                   V_in = h_ie.I_B + (1 + h_fe)I_B.R_E

But,            V_out = I_E.R_E = (1 + h_fe).I_B.R_E

∴ Voltage Gain

Output impedance Z₀ across the output terminals is by definition Z₀ = where V is the open circuit voltage across the output terminals and I is the short circuit current. When the emitter is open, the open circuit voltage V₀ is V_in = I_B. h_ie. The short circuit current I_SC = I_E and I_SC = I_E = (1 + h_fe).I_B

∴                    

Then, the output impedance Z₀ is , a low value when compared to the input impedance Z_in where, Z_in = ⌊h_ie + (1 + h_fe).R_E⌋ which is relatively very large.

Example 11   Compare the features of common emitter and common collector amplifier circuits with reference to voltage gain, current gain, input resistance and output resistance.

Both voltage gain and current gains are much greater than unity for CE amplifier and so the common emitter transistor amplifier circuit is most popularly used in practice whereas, the voltage gain is approximately unity for common collector amplifier

From the above two equations for current gain for both CE and CC amplifiers current gain variations with variations in load resistance are similar.

The expressions for input impedance Z_IN.C.E and Z_IN.C.C.A are as following

 

As h_re ≅ 0; and if substituted in the above equation for Z_IN.C.E;. the input resistance of common emitter transistor amplifier is approximately equal to h_i.e of the transistor which is of the order of 1 KΩ, and varies moderately with variations in the load resistance R_L; whereas the input resistance of common collector amplifier is very high and is of the order of megaohms, because h_r._C ≅ 1 and when substituted in the equation for Z_IN.C.C.A; the input resistance of common collector amplifier is very high and also due to voltage series negative feedback introduced into the common collector amplifier circuit.

The expressions for the output impedances of CE and CC amplifiers are as following.

From the above equation for CC amplifier, the output impedance is very low. As the common collector amplifier has very low output impedance of the order of few tens of ohms and very large input resistance of the order of megaohms, CC amplifier is used to couple between high impedance source and low impedance loads and as impedance transformation circuits and unity gain Buffer amplifier circuits.

The output impedance for common emitter transistor amplifier is the reciprocal of output admittance given as following. Further, the reverse resistance of the output junction of the CE transistor has high resistance. So, the output resistance of CE transistor amplifiers is reasonably large and is of the order of few thousands of ohms

Questions for Practice

1. Discuss the need for biasing the transistor devices when used in amplifier circuits.
2. Draw a transistor biasing circuit using two separate D.C. sources.
3. Draw fixed biasing circuit or fixed current biasing circuit of N-P-N transistor and explain the circuit with necessary equations.
4. Draw fixed biasing circuit or fixed current biasing circuit of P-N-P transistor and explain the circuit with necessary equations.
5. Draw collector base biasing circuit for NPN transistor and explain the process of applying the forward bias to the input junction and reverse bias to the output junction of N-P-N transistor with necessary equations.
6. Draw collector base biasing circuit for P-N-P transistor and explain the process of applying the forward bias to the input junction and reverse bias to the output junction of N-P-N transistor with necessary equations.
7. Draw voltage divider biasing circuit or self-bias circuit for providing forward bias to the emitter junction and reverse bias to the collector junction of N-P-N transistor with necessary equations and explain how stability of operation of the device when used as an amplifier is achieved.
8. Draw potential divider biasing circuit or self-bias circuit for providing forward bias to the emitter junction and reverse bias to the collector junction of P-N-P transistor with necessary equations and explain how stability of operation of the device when used as an amplifier is achieved.
9. Obtain the D.C. load line equation for a transistor using voltage divider biasing circuit. Explain the importance of the D.C. load line in the design of voltage amplifier circuits.
10. Explain the method of graphical determination of fixing the quiescent or D.C. operating point of the transistor amplifier. Discuss the specifications that are considered in the design of a transistor amplifier and any precautions that are to be considered.
11. Discuss the design aspects of fixing up the circuit components of a transistor amplifier using self-biasing arrangement.
12. Define the transistor h-parameters using necessary equations considering a transistor as a two-port network.
13. Using a practical circuit explain the method of obtaining the input and output characteristics of a transistor.
14. Draw common emitter transistor amplifier circuit with fixed bias arrangement using a single D.C. source and explain the concepts involved in the process of amplification using input and output characteristics of the device.
15. Draw common emitter transistor amplifier circuit with collector to base bias arrangement using a single D.C. source and explain the concepts involved in the process of amplification using input and output characteristics of the device.
16. Draw common emitter transistor amplifier circuit with self-bias arrangement using a single D.C. source and explain the concepts involved in the process of amplification using input and output characteristics of the device.
17. Discuss the significance of input resistance and output resistance of an amplifier circuit, when they are used in practical circuits.
18. Draw the common emitter transistor amplifier circuit. Show the wave forms at different points in the circuit with qualitative explanation.
19. Draw the D.C. equivalent circuit and A.C. equivalent of CE transistor amplifier and explain their significance in the circuit analysis.
20. Draw the small signal low frequency equivalent circuit of a CE transistor amplifier circuit and derive the expression for voltage gain at low frequency region.
21. Draw the small signal low frequency equivalent circuit of a CE transistor amplifier circuit at mid-frequency region and derive the expression for voltage gain.
22. Draw the small signal low frequency equivalent circuit of a CE transistor amplifier circuit at high frequency region and derive the expression for voltage gain.
23. Draw the common base transistor amplifier circuit. Show the wave forms at different points in the circuit with qualitative explanation.
24. Draw the common collector transistor amplifier circuit. Show the wave forms at different points in the circuit with qualitative explanation.
25. Draw the small signal low frequency equivalent circuit of a common base transistor amplifier circuit and derive the expression for voltage gain, Z_IN and Z_OUT.
26. Draw the circuit of an emitter follower and explain its working. Derive the expressions for voltage gain, Z_in and Z_out.
27. Discuss the various types of biasing circuits used for FET amplifier circuit.
28. Draw the common source field effect transistor amplifier circuit. Show the wave forms at different points in the circuit with qualitative explanation.
29. Draw common source FET amplifier circuit with self-bias arrangement using a single D.C. source and explain the concepts involved in the process of amplification using input and output characteristics of the device.
30. Discuss the purpose of various coupling capacitors and bypass capacitors used in the amplifier circuits and also mention the design criteria for component selection.
31. Draw the common source FET amplifier circuit. Show the wave forms at different points in the circuit with qualitative explanation.
32. Draw the common gate FET amplifier circuit. Show the wave forms at different points in the circuit with qualitative explanation. Derive the expressions for A_V, Z_IN and Z_OUT.
33. Draw the common drain FET amplifier circuit. Show the wave forms at different points in the circuit with qualitative explanation. Derive the expressions for A_V, Z_IN and Z_OUT.
34. Discuss the reasons for the absence of thermal runaway in FET devices.
35. Explain the small signal A.C. equivalent circuits for FET amplifier circuits.
36. Draw the mid-frequency equivalent circuit of a FET amplifier circuit and derive the expression for voltage gain mentioning the reasons for not including the effect of various capacitances in the equivalent circuit.
37. Draw the typical frequency response characteristic of an amplifier and discuss the significance of the influence of coupling capacitors, shunt capacitors and the load resistors in the circuit.
38. The maximum voltage gain of a transistor amplifier is 100. Low frequency cut-off frequency occurs at 1000Hz and High frequency cut-off occurs at 501KHz. Determine the bandwidth of the amplifier circuit and draw the frequency response marking the values of gain at the salient points.
39. Calculate the value of g_m for a transistor with I_CQ = 26 mA and V_T = 26 mv.
40. Discuss the effect of coupling capacitors on the low frequency response of amplifiers.
41. Draw the circuit of a single stage FET amplifier. Draw the mid-frequency equivalent circuit and derive the expression for voltage gain. Data: g_m = 2 milli mhos; r_d = 200 KΩ.; R_d = 5 KΩ. R_L is very large and does not affect the load. Calculate voltage gain.
42. Draw the transistor amplifier circuit using potential divider biasing arrangement with V_CC = +12 volts. R_C = 0.8 KΩ and R_S = 0.2 KΩ. To obtain maximum output signal swings, select suitable D.C. operating point and calculate I_CQ and V_CEQ.
43. A silicon transistor is used in a CE transistor amplifier circuit with potential divider biasing arrangement with V_CC = 18 volts and R_C = 1.2 KΩ. Transistor β = 100. So as to obtain symmetrical swings of output signals, the quiescent operating point is chosen with I_CQ = 4.5 mA and V_CEQ = 9 volts. Calculate the values of R₁; R₂ and R_E assuming a stability factor S = 10.
44. The D.C. equivalent circuit of a CE transistor amplifier with collector to base bias arrangement has V_CC = 18 volts, with the component values of R_C = 3.4 KΩ, R_E = 0.6 KΩ. The collector to base resistance R_B = 300 KΩ. V_γ = 0.7 volts and β = 100. Calculate the magnitudes of collector voltage, emitter voltage and base voltage.
45. Draw the CE transistor amplifier circuit with potential divider bias arrangement having V_CC = 14 volts. R₁ = 21 KΩ, R₂ = 7 KW; V_BE = 0.5 volts; R_C = 0.8 KΩ. and R_E = 0.6 KΩ. Draw the D.C. equivalent circuit. Calculate the base voltage, emitter voltage, collector voltage and V_CE. Comment on the results for the operation of the amplifier circuit. Design suitable values of the capacitors to be used in the circuit considering the lowest frequency of the signal to be 116 Hz.
46. Draw the circuit of a common source FET amplifier with R_G = 1 MΩ, R_S = 0.5 KΩ and the load resistance R_d = 1.5 KΩ and V_CC = 20 volts. The pinch-off voltage V_P of the selected FET device is equal to – 3.6 volts. The gate to source bias voltage is to be designed at half the pinch-off voltage so as to have equal signal swings in the amplifier circuit. Calculate the magnitudes of source voltage and drain voltage. Calculate the magnitude of the input resistance, if the current through gate resistor R_G is zero.
47. Consider common source FET amplifier circuit with potential divider bias circuit. Draw the wave forms at salient points in the circuit and discuss the feature of 180° phase shift between the input and output signal voltages.
48. Consider source follower circuit and discuss the feature of the in phase nature of output and input signals with necessary wave forms. Derive the relation for unity voltage gain.
49. For an emitter follower circuit, explain with necessary wave forms how there is no phase inversion between input and output voltages. Further, discuss the relations for very high input resistance and very low output resistance of the emitter follower circuits and mention a few practical applications of the circuit.
50. For source follower circuits discuss the various features in detail that made it suitable as Unity Gain Buffer Amplifier Circuits. Also, mention a few practical applications.

Points to Remember

1. Electronic devices and circuits here discuss the nature of analogue signals which means that the input signals to the amplifier circuits are derived from the physical systems such as the output of a microphone of an audio system or signals from other measuring instruments such as temperature sensing devices, home appliances and so on.
2. There are many types of continuous signals but the common feature of assuming an input signal is proportional to the physical quantity in nature. A sinusoidal signal is assumed in the analysis because any complex signal in nature can be represented as a combination of sinusoidal signals using network analysis and signal processing.
3. Amplifier circuits are given signal voltages to be amplified at the input port, some process takes place during the signal passage through the passive circuit components and the active device whether it is a bipolar junction transistor or a field effect transistor and increased signal appears at the output port of the amplifier, which is put to the practical utility.
4. As illustrated in one of the practical system of public address system, it is discussed that the processing of electrical signals is easier and using the relevant or appropriate signal conditioning transducers, the electronic circuits play a very much significant and major role in this advanced technology of various communication systems and computer technology.
5. As observed in many of the present day applications such as data transfer to long distances and reception of the signals globally using cell phones, satellite communications and others, the processing of signals is one of the basic features of the communication system.
6. In the amplifier circuits, the input signal, the sine wave has the representation of amplitude, frequency and the phase, which are considered for the faithful reproduction of the input signals at the receiver (or the load terminal) or any changes that may take place during transmission of signals as distortion. For understanding these concepts, it is necessary to have a strong foundation of the concepts.
7. The electronic circuit is considered as an amplifier only if the output signal V_OUT is greater than the input signal V_IN. The amplification is defined as the ratio of the output voltage to the input voltage of the amplifier.
8. The active device a bipolar junction transistor (BJT) or a field effect transistor needs biasing the P-N junctions for their working as basic amplifiers in association with D.C. supply voltage and a few passive circuit components such as resistors, capacitors and inductors.
9. For a BJT to function as an amplifying device the emitter junction (input junction) of the transistor is to forward biased and the collector junction (output junction) is to be reverse biased so that the D.C. operating conditions are fixed in the active region of the output characteristics of the transistor.
10. There are basically three methods of biasing the transistors using a single D.C. source and a few resistors, (a) fixed biasing method, (b) collector to base biasing method, and (c) potential divider biasing method or self-bias.
11. Out of the three methods of biasing the transistor the most popular circuit is the potential divider biasing or self-biasing circuit, because of its stability of operation, as the introduction of emitter resistor has correcting features to variation in the collector current due to bias or temperature variations.
12. For linear operation of the amplifiers and to provide maximum and symmetrical output signal swings, the quiescent or D.C. operating point Q is fixed at the middle of the D.C. load line drawn on the output characteristics of the transistor or FET device.
13. Depending upon the practical application of the transistor amplifiers, the device specifications can be determined. Once the selection of the transistor is done, the load line is drawn below the maximum power dissipation curve on the output characteristics to determine the quiescent operating point Q.
14. The coupling capacitor C_{C IN} couples the A.C. input signal into the input port of the amplifier and at the same time blocks D.C. voltage that may be present in the signal source so that it will not effect the D.C. operating conditions of the transistor/FET.
15. The input signal gets superimposed on the D.C. biasing voltages to the input junction, (emitter junction for transistor or gate to source junction of the FET device) causing varying D.C. as biasing to the devices and resulting increased values of output currents (collector current for BJT and drain current for FET) of the amplifiers.
16. Output currents flowing through the load resistance develop the output voltages at the output port of the amplifiers as per design values.
17. The ratio of the output voltage to the input voltage of the amplifier is known as the voltage gain of the amplifier. If voltage gains are observed for different values of input signal frequencies and plotted on a semilog or a linear graph paper the resulting characteristic of the amplifier is known as the frequency response of the amplifier.
18. There will be 180° phase shift between the output and input signal voltages of common emitter transistor amplifier and common source amplifier.
19. The frequency response characteristic of the amplifier is divided into three operating regions, the low frequency region, mid frequency region and high frequency region.
20. The low frequency region and mid-frequency region are separated by low frequency cut-off point f₁ or f_L defined as the point where the voltage gain is 0.707 times the maximum voltage gain A_MID in the mid frequency region or – 3db down from the mid-frequency gain when the gain is calculated as 20 log A_V.
21. The high frequency region and mid-frequency region are separated by high frequency cut-off point f₂ or f_H defined as the point where the voltage gain is 0.707 times the maximum voltage gain A_MID in the mid frequency region or – 3db down from the mid-frequency gain when the gain is calculated as 20 log A_V.
22. If the maximum voltage gain of an amplifier is 100 in the mid-frequency region of the frequency response of the amplifier, then the gain at the low frequency and the high frequency cut-off points is 70.7.
23. Once the low frequency and the high frequency cut-off points are known on the amplifier frequency response characteristic, and then the bandwidth (B.W.) of the amplifiers is the difference in high frequency cut-off point to the low frequency cut-off point. Product of gain and the bandwidth of the amplifiers is constant.
24. For emitter follower circuit (common collector transistor amplifier circuit), the output voltage is taken between the emitter and the common collector of the transistor amplifier circuit. Output and input voltages are in phase. The output voltage is almost equal to the input voltage. So, the voltage gain of common collector transistor amplifier circuit is approximately unity. The emitter voltage follows the input signal voltage variations. So, the common collector transistor amplifier circuit is also known as emitter follower.
25. For source follower circuit (common drain FET amplifier circuit), the output voltage is taken between the source and the common drain of the FET amplifier circuit. Output and input voltages are in phase. The output voltage is almost equal to the input voltage. So, the voltage gain of common drain FET amplifier circuit is approximately unity. The source voltage follows the input signal voltage variations. So, the common drain field effect transistor amplifier circuit is also known as source follower.
26. For emitter follower circuit the input impedance is very high and the output impedance is very low. So, emitter follower circuits are used as buffer amplifiers wherever impedance transformation is required in practical electronic circuits.
27. For source follower circuit the input impedance is very high and the output impedance is very low. So, emitter follower circuits are used as buffer amplifiers wherever impedance transformation is required in practical electronic circuits.
28. In common base transistor amplifier circuits there is isolation between the output and input circuits. So, they are used in radio frequency amplifier circuits.
29. The amplifier gain increases with increase in load resistance. When the gain of the amplifier increases its bandwidth decreases.
30. The input and the output coupling capacitors in amplifier circuits affect the low frequency response of the amplifier.
31. The shunt capacitances affect the high frequency response of amplifiers.
32. In the mid-frequency region of amplifier response, the affects of capacitors on voltage gain is negligible and hence in the mid-frequency equivalent circuit of the amplifiers the coupling capacitors and the shunt capacitances are omitted.
33. The input circuit time constant which is the product of R_IN (input resistance of the amplifier stage) and the input coupling capacitance C_{C IN} determines f₁ or f_L; the lower cut-off frequency or low frequency cut-off of the amplifier circuit.
34. The output circuit time constant which is the product of (R_C + R_L) (output RC circuit of the amplifier stage) and the output coupling capacitance C_{C OUT} affects the f_L, the lower cut-off frequency or low frequency cut-off of the amplifier circuit.
35. In practical circuits, no amplifier has uniform gain at all signal frequencies. In A.C. coupled amplifier circuits, where the input signal is coupled through C_{C IN} to the input stage of an amplifier and the output signal is obtained through the output coupling capacitor C_{C OUT} (the input and the output coupling capacitors) the associated input and the output circuit time constants affect the low frequency response of amplifier circuits. The shunt capacitances the junction capacitances of the active devices and the stray wiring capacitances affect the high frequency response of the amplifiers.
36. At high frequencies, the reactance of the coupling capacitors and the bypass capacitors across the emitter or the source resistances become very small and do not have any affect on the high frequency response of the amplifier. But the device junction capacitances (the emitter junction capacitance C_BE and the collector junction capacitance’C_BC’) will be in parallel at the input and the output ports of the amplifier circuits. Similarly, the junction capacitances for the FET device C_GS between gate and the source and C_GD between the gate and the drain will be in shunt at the input and output ports of FET amplifiers that affect the high frequency response of amplifier circuits.
37. The useful range of frequencies, that is, the bandwidth of the amplifiers over which the amplifier gain is reasonably uniform decides the practical application of amplifiers. Normally, the amplifier bandwidth is decided by the high frequency cut-off as the low frequency cut-off signal frequency is low compared to high frequency cut-off.
38. The gain at the cut-off frequency or comer frequency or critical frequency on amplifier frequency response of an amplifier is 0.707 × A_MID or –3db down the mid-band gain expressed in decibels.
39. The variation of amplifier gain with input signal frequency is known as the frequency response of the amplifier and it has roll-offs (decrease in gain with frequency) at low frequency and high frequency ranges that is due to the coupling capacitors and bypass capacitors at low frequency range and due to shunt capacitances in high frequency range. The bandwidth of the amplifier is decided by the frequency response of the amplifier circuits and in turn the practical applications of electronic circuits.