68 BIBLIOGRAPHY
ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), pages 96–
109, 2018. DOI: 10.1109/isca.2018.00019 44
Elizabeth J. O’Neil, Patrick E. O’Neil, and Gerhard Weikum. e LRU-K page replacement
algorithm for database disk buffering. ACM SIGMOD Record, pages 297–306, 1993. DOI:
10.1145/170036.170081 19
Gennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip B. Gibbons, Michael A.
Kozuch, and Todd C. Mowry. Exploiting compressed block size as an indicator of fu-
ture reuse. In IEEE 21st International Symposium on High Performance Computer Architecture
(HPCA), pages 51–63, 2015. DOI: 10.1109/hpca.2015.7056021 54
Moinuddin K. Qureshi and Gabe H. Loh. Fundamental latency trade-off in architecting dram
caches: Outperforming impractical SRAM-tags with a simple and practical design. In Proc.
of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, pages 235–246,
2012. DOI: 10.1109/micro.2012.30 56
Moinuddin K. Qureshi and Yale N. Patt. Utility-based cache partitioning: A low-overhead,
high-performance, runtime mechanism to partition shared caches. In e 39th Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 423–432, 2006.
DOI: 10.1109/micro.2006.49 45, 46, 48
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt. A case for MLP-
aware cache replacement. In Proc. of the International Symposium on Computer Architecture
(ISCA), pages 167–178, 2006. DOI: 10.1145/1150019.1136501 21, 22, 40, 41, 42, 54
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely, and Joel Emer. Adaptive
insertion policies for high performance caching. In Proc. of the International Symposium on
Computer Architecture (ISCA), pages 381–391, 2007. DOI: 10.1145/1250662.1250709 13,
14, 15, 21, 22, 24, 27, 47
Kaushik Rajan and Ramaswamy Govindarajan. Emulating optimal replacement with a shep-
herd cache. In e 40th Annual IEEE/ACM International Symposium on Microarchitecture
(MICRO), pages 445–454, 2007. DOI: 10.1109/micro.2007.25 17, 18
John T. Robinson and Murthy V. Devarakonda. Data cache management using frequency-
based replacement. In e ACM Conference on Measurement and Modeling Computer Systems
(SIGMETRICS), pages 134–142, 1990. DOI: 10.1145/98460.98523 19, 20
F. Rosenblatt. Principles of Neurodynamics: Perceptrons and the eory of Brain Mechanisms. Spar-
tan, 1962. DOI: 10.21236/ad0256582 33
Daniel Sanchez and Christos Kozyrakis. Vantage: Scalable and efficient fine-grain cache parti-
tioning. In Proc. of the International Symposium on Computer Architecture (ISCA), pages 57–68,
2011. DOI: 10.1145/2000064.2000073 45
BIBLIOGRAPHY 69
Somayeh Sardashti and David A. Wood. Decoupled compressed cache: Exploiting spatial local-
ity for energy-optimized compressed caching. In Proc. of the 46th Annual IEEE/ACM Interna-
tional Symposium on Microarchitecture, pages 62–73, 2013. DOI: 10.1145/2540708.2540715
54
Somayeh Sardashti, André Seznec, and David A. Wood. Yet another compressed cache: A low-
cost yet effective compressed cache. ACM Transactions on Architecture and Code Optimization
(TACO), 13(3):27, 2016. DOI: 10.1145/2976740 54
Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, and Todd C. Mowry. e evicted-address
filter: A unified mechanism to address both cache pollution and thrashing. In e 21st In-
ternayional Conference on Parallel Architectures and Compilation Techniques (PACT), pages 355–
366, 2012. DOI: 10.1145/2370816.2370868 33
Vivek Seshadri, Samihan Yedkar, Hongyi Xin, Onur Mutlu, Phillip B. Gibbons, Michael A.
Kozuch, and Todd C. Mowry. Mitigating prefetcher-caused pollution using informed
caching policies for prefetched blocks. ACM Transactions on Architecture and Code Optimiza-
tion (TACO), 11(4):51, 2015. DOI: 10.1145/2677956 49
D. Shasha and T. Johnson. 2Q: A low overhead high performance buffer management re-
placement algorithm. In Proc. of the 20th International Conference on Very Large Databases,
pages 439–450, Santiago, Chile, 1994. 19
Yannis Smaragdakis, Scott Kaplan, and Paul Wilson. EELRU: Simple and effective adap-
tive page replacement. ACM SIGMETRICS Performance Evaluation Review, pages 122–133,
1999. DOI: 10.1145/301464.301486 11, 12
Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt. Feedback directed prefetching:
Improving the performance and bandwidth-efficiency of hardware prefetchers. In Proc. of the
13th International Symposium on High Performance Computer Architecture (HPCA), pages 63–
74, 2007. DOI: 10.1109/hpca.2007.346185 49
Srikanth T. Srinivasan and Alvin R. Lebeck. Load latency tolerance in dynamically scheduled
processors. In Proc. of the 31st Annual ACM/IEEE International Symposium on Microarchitec-
ture, pages 148–159, IEEE Computer Society Press, 1998. DOI: 10.21236/ada440304 43,
44
Srikanth T. Srinivasan, R. Dz-Ching Ju, Alvin R. Lebeck, and Chris Wilkerson. Locality
vs. criticality. In Computer Architecture. Proc. of the 28th Annual International Symposium on,
pages 132–143, IEEE, 2001. DOI: 10.1145/379240.379258 43
Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh, Samira Khan, and Onur Mutlu. e
application slowdown model: Quantifying and controlling the impact of inter-application
70 BIBLIOGRAPHY
interference at shared caches and main memory. In Proc. of the 48th International Symposium
on Microarchitecture, pages 62–75, ACM, 2015. DOI: 10.1145/2830772.2830803 46
Masamichi Takagi and Kei Hiraki. Inter-reference gap distribution replacement: An improved
replacement algorithm for set-associative caches. In Proc. of the 18th Annual International
Conference on Supercomputing, pages 20–30, ACM, 2004. DOI: 10.1145/1006209.1006213
26
Elvira Teran, Zhe Wang, and Daniel A. Jiménez. Perceptron learning for reuse prediction. In
Microarchitecture (MICRO), 49th Annual IEEE/ACM International Symposium on, pages 1–12,
2016. DOI: 10.1109/micro.2016.7783705 25, 33, 34
H. S. P. Wong, C. Ahn, J. Cao, H. Y.-Chen, S. B. Eryilmaz, S. W. Fong, J. A. Incorvia, Z. Jiang,
H. Li, C. Neumann, K. Okabe, S. Qin, J. Sohn, Y. Wu, S. Yu, X. Zheng, Stanford memory
trends, https://nano.stanford.edu/stanford-memory-trends, June 6, 2019. 55
Carole-Jean Wu, Aamer Jaleel, Will Hasenplaugh, Margaret Martonosi, Simon C. Steely, Jr.,
and Joel Emer. SHiP: Signature-based hit predictor for high performance caching. In 44th
IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 430–441, 2011a.
DOI: 10.1145/2155620.2155671 28, 30
Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely, Jr., and Joel Emer. PAC-
Man: Prefetch-aware cache management for high performance caching. In 44th Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO)
, pages 442–453, 2011b.
DOI: 10.1145/2155620.2155672 49, 50
Yuejian Xie and Gabriel H. Loh. PIPP: Promotion/insertion pseudo-partitioning of multi-core
shared caches. In Proc. of the 36th Annual IEEE/ACM International Symposium on Computer
Architecture, pages 174–183, 2009. DOI: 10.1145/1555754.1555778 45, 48
..................Content has been hidden....................

You can't read the all page of ebook, please click here login for view all page.
Reset