19.2.1 Phase Noise Characteristics of Free-Running Oscillators and PLLs

The most common circuit solution for frequency generation is to use a Voltage-Controlled Oscillator (VCO). Fig. 19.3 shows a model and the characteristic PN behavior of a free-running VCO in different offset frequency regions, where f₀ is the oscillation frequency, Δf is the offset frequency from f₀, P_s is the signal strength, Q is the loaded quality factor of the resonator, F is an empirical fitting parameter but has physical meaning of noise figure, and Δf_1/f³ is the 1/f-noise corner frequency of the active device in use [57].

The following can be concluded from the Leeson formula in Fig. 19.3:

Thus, there are several parameters that may be used for design trade-offs in VCO development. To make performance comparison of the VCOs made in different semiconductor technologies and circuitry topologies, a Figure-of-Merit (FoM) is often used which takes into account power consumption and thus allows for a fair comparison:

$\mathrm{FoM}={\mathrm{PN}}_{\mathrm{VCO}}\left(\mathrm{\Delta }f\right)-20\log \left(\frac{f_0}{\mathrm{\Delta }f}\right)+10\log (P_{\mathrm{DC}}/1\mathrm{mW})$

Here ${\mathrm{PN}}_{\mathrm{VCO}}\left(\mathrm{\Delta }f\right)$ is the phase noise of the VCO in dBc/Hz and $P_{\mathrm{DC}}$ is the power consumption in watt. One noticeable result of this expression is that both phase noise and power consumption in linear power are proportional to $f_0$². Thus, to maintain a phase noise level at a certain offset while increasing $f_0$ by a factor N would require the power to be increased by N² (assuming a fixed FoM value).

A common way to suppress the phase noise is to apply a Phase Locked Loop (PLL) [18]. Basic PLL building blocks contain a VCO, frequency divider, phase detector, loop filter, and a low-frequency reference source of high stability, such as a crystal oscillator. The total phase noise of the PLL output is composed of contributions from the VCO outside the loop bandwidth and the reference oscillator inside the loop. A significant noise contribution is also added by the phase detector and the divider.

As an example for the typical behavior of an mm-wave LO, Fig. 19.4 shows the measured phase noise from a 28 GHz LO produced by applying a PLL at a lower frequency and then multiplying up to 28 GHz. There are four different offset ranges that show distinctive characteristics:

19.2.2 Challenges With mm-Wave Signal Generation

As phase noise increases with frequency, increasing the oscillation frequency from 3 GHz to 30 GHz, for instance, will result in fundamental PN degradation of 20 dB at a given offset frequency. This will certainly limit the highest order of PN-sensitive modulation schemes usable at mm-wave and thus poses a limitation on achievable spectrum efficiency for mm-wave communications.

Millimeter-wave LOs also suffer from the degradation in quality factor Q and the signal power P_s. Leeson’s equation tells us that in order to achieve low phase noise, Q and P_s need to be maximized, while minimizing the noise figure of the active device. Unfortunately, these three factors contribute in an unfavorable manner when oscillation frequency increases. In monolithic VCO implementation, the Q-value of the on-chip resonator decreases rapidly with frequency increases due mainly to (1) the increase of parasitic losses such as metal loss and/or substrate loss and (2) the decrease of varactor Q. Meanwhile, the signal strength of the oscillator becomes increasingly limited when going to higher frequencies. This is because higher-frequency operation requires more advanced semiconductor devices whose breakdown voltage decreases as their feature size shrinks. This is manifested by the observed reduction in power capability versus frequency for power amplifiers (–20 dB per decade) as detailed in Section 19.3. For this reason, a method widely applied in mm-wave LO implementation is to generate a lower-frequency PLL and then multiply the signal up to the target frequency.

Except for the challenges discussed above, up-conversion of the 1/f noise creates an added slope close to the carrier. The 1/f noise is strongly technology-dependent, where planar devices such as CMOS and HEMT (High Electron Mobility Transistor) generally show higher 1/f noise than vertical bipolar devices such as bipolar and HBTs. Technologies used in fully integrated MMIC/RFIC VCO and PLL solution range from CMOS and BiCMOS to III–V materials where InGaP HBT is popular due to its relatively low 1/f noise and high breakdown. Occasionally also pHEMT devices are used, even if suffering from severe 1/f noise. Some developments have been made using GaN FET structures in order to benefit from the very high breakdown voltage, but 1/f is even higher than in GaAs FET devices and therefore seems to offset the gain due to the breakdown voltage. Fig. 19.5 summarizes phase noise performance at 100 kHz offset vs oscillation frequency for different semiconductor technologies.

Last but not least, recent research reveals the impact of the LO noise floor on system performance [23]. This impact is insignificant if the symbol rate is low. When the rate increases, such as in 5G NR, the flat noise floor starts to increasingly affect the EVM of the modulated signal. Fig. 19.6 shows the measured EVM from a transmitter for different symbol rate and different noise floor level. The impact from receiver LO noise floor is similar. This observation may imply that it requires extra care when generating mm-wave LOs for wideband systems in terms of choice of technology, VCO topology, and multiplication factor, to maintain a reasonably low PN floor.

19.4.1 Possibilities of Filtering at the Analog Front-End

Different implementations provide different possibilities for filtering. For the purpose of discussion, two main cases can be identified:

There are at least three places where it makes sense to put filters, depending on implementation, as shown in Fig 19.9:

The main purpose of F1/F0 is normally to suppress interference and emissions far from the desired channel across a wide frequency range (for example, DC to 60 GHz). There should not be any unintentional resonances or passbands in this wide frequency range. This filter will help relax the design challenge (bandwidth to consider, linearity requirements, etc.) of all following blocks. Insertion loss must be very low, and there are strict size and cost requirements since there must be one filter at each subarray (Figs. 19.9 and 19.10). In some cases, this filter must fulfill strict suppression requirements close to the passband, particularly for high output power close to sensitive bands.

The main purpose of F2 is suppression of LO-, image-, spurious-, and noise-emission, and suppression of incoming interferers relatively far from the desired frequency band. There are still strict size requirements, but more loss can be accepted (behind the first amplifiers) and even unintentional passbands (assuming F1/F0 will handle that). This allows better discrimination (more poles), and better frequency precision (for example, using half-wave resonators).

The main purpose of F3 is typically suppression of LO-, image-, spurious-, and noise-emission, and suppression of incoming interferers that accidentally fall in the IF-band after the mixer, and strong interferers that tend to block the mixers or ADCs. For analog (or hybrid) beam-forming it is enough to have just one (or a few) such filters. This relaxes requirements on size and cost, which opens the possibility to achieve sharp filters with multiple poles and zeroes, and with high Q-value and good frequency precision in the resonators.

The deeper into the RF-chain (starting from the antenna element), the better protected the circuits will get. For the monolithic integration case it is difficult to implement filters F2 and F3. One can expect performance penalties for this case, and output power per branch is lower. Furthermore, it is challenging to achieve good isolation across a wide frequency range, as microwaves tend to bypass filters by propagating in ground structures around them.

19.4.2 Insertion Loss (IL) and Bandwidth

Sharp filtering on each branch (at positions F1/F0) with narrow bandwidth leads to excessive loss at microwave and mm-wave frequencies. To get the insertion loss down to a reasonable level the passband can be made significantly larger than the signal bandwidth. A drawback of such an approach is that more unwanted signals will pass the filter. In choosing the best loss-bandwidth trade-off there are some basic dependencies to be aware of:

To exemplify the trade-off, a three-pole LC-filter with Q=20, 100, 500, and 5000, for 100 and 800 MHz 3 dB-bandwidth is studied, tuned to 15 dB return loss (with Q=5000) is examined, as shown in Fig. 19.11.

From this study it is observed that:

19.4.3 Filter Implementation Examples

There are many ways to implement filters in a 5G array radio. Key aspects to compare are: Q-value, discrimination, size, and integration possibilities. Table 19.1 gives a rough comparison between different technologies and two specific examples are given below.

19.4.3.1 PCB Integrated Implementation Example

A simple and attractive way to implement antenna filters (F1) is to use strip-line or microstrip filters, embedded in a PCB close to each antenna element. This requires a low-loss PCB with good precision. Production tolerances (permittivity and patterning and via-positioning) will limit the performance, mainly though a shift in the pass-band and increased mismatch. In most implementations the passband must be set larger than the operating frequency band with a significant margin to account for this.

Typical characteristics of such filters can be illustrated by looking at the following design example, with the layout shown in Fig. 19.12:

• • Five-pole, coupled line, strip-line filter;
• • Dielectric permittivity: 3.4;
• • Dielectric thickness: 500 μm (ground to ground);
• • Unloaded resonator Q: 130 (assuming low-loss microwave dielectrics).

The filter is tuned to give 20 dB suppression at 24 GHz, while passing as much as possible of the band 24.25–27.5 GHz (with 17 dB return loss). Significant margins are added to make room for variations in the manufacturing processes of the PCB.

A Monte Carlo analysis was performed to study the impact of variations in the manufacturing process on filter performance, using the following quite aggressive tolerance assumptions for the PCB:

• • Permittivity standard deviation: 0.02;
• • Line width standard deviation: 8 μm;
• • Thickness of dielectric standard deviation: 15 μm.

With these distribution assumptions, 1000 instances of the filter were generated and simulated. Fig. 19.13 shows the filter performance (S21) for these 1000 instances (blue traces), together with the nominal performance (yellow trace). Red lines in the graph indicate possible requirement levels that could be met considering this filter.

From this design example, the following rough description of a PCB filter implementation is found:

• • 3–4 dB insertion loss;
• • 20 dB suppression (17 dB if IL is subtracted);
• • 1.5 GHz transition region with margins included;
• • Size: 25 mm², which can be difficult to fit in the case of individual feed and/or dual polarized elements;
• • If a 3 dB IL is targeted, there would be significant yield loss with the suggested requirement, in particular for channels close to the pass-band edges.

19.4.3.2 LTCC Filter Implementation Example

Another promising way to implement filters is to make components for Surface Mount Assembly (SMT), including both filters and antennas, for example based on Low-Temperature Cofired Ceramics (LTCC). One example of a prototype LTCC component was outlined in Ref. [31] and is also shown in Fig. 19.14.

The measured performance of the corresponding filter is shown in Fig. 19.15 and it shows that the LTCC-filter adds about 2 dB of insertion loss for a 2 GHz passband, while providing 22 dB of additional attenuation 1 GHz from the passband edge.

Additional margins relative to this example should be considered to account for manufacturing tolerances and future adjustments of bandwidth, suppression level, guard bandwidth, antenna properties, integration aspects, etc. Accounting for such margins, the LTCC-filter shown could be assumed to add approximately 3 dB of insertion loss, for 17 dB suppression (IL subtracted) at 1.5 GHz from the pass-band edge.

Technology development, particularly regarding Q-values and manufacturing tolerances, will likely lead to improvements in these numbers.

19.5.1 Receiver and Noise Figure Model

A receiver model as shown in Fig. 19.16 is assumed here. The dynamic range (DR) of the receiver will in general be limited by the front-end insertion loss (IL), the receiver (RX) Low-noise Amplifier (LNA), and the ADC noise and linearity properties.

Typically DR_LNADR_ADC so the RX use Automatic Gain Control (AGC) and selectivity (distributed) in-between the LNA and the ADC to optimize the mapping of the wanted signal and the interference to the DR_ADC. For simplicity, a fixed gain setting is considered here.

A further simplified receiver model can be derived by lumping the Front End (FE), RX, and ADC into three cascaded blocks, as shown in Fig. 19.17. This model cannot replace a more rigorous analysis but will demonstrate interdependencies between the main parameters.

Focusing on the small signal co-channel noise floor, the impact of various signal and linearity impairments can be studied to arrive at a simple noise factor, or noise figure, expression.

19.5.2 Noise Factor and Noise Floor

Assuming matched conditions, Friis’ formula can be used to find the noise factor at the receiver input as (linear units unless noted),

$F_{\mathrm{RX}}=1+(F_{\mathrm{LNA}}-1)+\frac{(F_{\mathrm{ADC}}-1)}{G}$

The RX input referred small-signal co-channel noise floor will then equal

$N_{\mathrm{RX}}=F_{\mathrm{LNA}}·N_0+\frac{{\mathrm{N}}_{\mathrm{ADC}}}{\mathrm{G}}$

where N₀=k ··· T ··· BW and N_ADC are the available noise power and the ADC effective noise floor in the channel bandwidth, respectively (k and T being Boltzmann’s constant and absolute temperature, respectively). The ADC noise floor is typically set by a combination of quantization, thermal, and intermodulation noise, but here a flat noise floor is assumed as defined by the ADC effective number of bits.

The effective gain G from LNA input to ADC input depends on small-signal gain, AGC setting, selectivity, and desensitization (saturation), but here it is assumed that the gain is set such that the antenna referred input compression point (CP_i) corresponds to the ADC clipping level, that is the ADC full scale input voltage (V_FS).

For weak non-linearities, there is a direct mathematical relationship between CP and the third-order intercept point (IP₃), such that IP₃≈CP+10 dB. For higher-order non-linearities, the difference can be larger than 10 dB, but then CP is still a good estimate of the maximum signal level while intermodulation for lower signal levels may be overestimated.

19.5.3 Compression Point and Gain

Between the antenna and the RX there is the FE with its associated insertion loss (IL>1), for example due to a T/R switch, a possible RF filter, and PCB/substrate losses. These losses have to be accounted for in the gain and noise expressions. Knowing IL, the CP_i can be found that corresponds to the ADC clipping as

${\mathrm{CP}}_{\mathrm{i}}=\frac{\text{IL}·N_{\mathrm{ADC}}{·\text{DR}}_{\mathrm{ADC}}}{G}$

The antenna referred noise factor and noise figure will then become

$F_i=\text{IL}·F_{\mathrm{RX}}=\text{IL}·F_{\mathrm{LNA}}+\frac{{\mathrm{CP}}_i}{N_0{·\text{DR}}_{\mathrm{ADC}}}$

and

${\mathrm{NF}}_i=10{·\log }_{10}(F_i),$

respectively.

When comparing two designs, for example, at 2 and 30 GHz, respectively, the 30 GHz IL will be significantly higher than that of the 2 GHz. From the F_i expression it can be seen that to maintain the same noise figure (NF_i) for the two carrier frequencies, the higher FE loss at 30 GHz needs to be compensated for by improving the RX noise factor. This can be accomplished by (1) using a better LNA, (2) relaxing the input compression point, that is increasing G, or (3) increasing the DR_ADC. Usually a good LNA is already used at 2 GHz to achieve a low NF_i, so this option is rarely possible. Relaxing CP_i is an option but this will reduce IP₃ and the linearity performance will degrade. Finally, increasing DR_ADC comes at a power consumption penalty (4× per extra bit). Especially wideband ADCs may have a high power consumption, that is when BW is below some 100 MHz the N₀ ··· DR_ADC product (that is BW ··· DR_ADC) is proportional to the ADC power consumption, but for higher bandwidths the ADC power consumption is proportional to BW² ··· DR_ADC, thereby penalizing higher BW (see Section 19.1). Increasing DR_ADC is typically not an attractive option and it is inevitable that the 30 GHz receiver will have a significantly higher NF_i than that of the 2 GHz receiver.

19.5.4 Power Spectral Density and Dynamic Range

A signal consisting of many similar subcarriers will have a constant power-spectral density (PSD) over its bandwidth and the total signal power can then be found as P=PSD ··· BW.

When signals of different bandwidths but similar power levels are received simultaneously, their PSDs will be inversely proportional to their BW. The antenna-referred noise floor will be proportional to BW and F_i, or N_i =F_i ··· k ··· T ··· BW, as derived above. Since CP_i will be fixed, given by G and ADC clipping, the dynamic range, or maximum SNR, will decrease with signal bandwidth, that is SNR_max∝1/BW.

The above signal can be considered as additive white Gaussian noise (AWGN) with an antenna-referred mean power level (P_sig) and a standard deviation (σ). Based on this assumption the peak-to-average-power ratio can be approximated as PAPR=20 ··· log₁₀(k), where the peak signal power is defined as P_sig+k ··· σ, that is there are k standard deviations between the mean power level and the clipping level. For OFDM an unclipped PAPR of 10 dB is often assumed (that is 3σ) and this margin must be subtracted from CP_i to avoid clipping of the received signal. An OFDM signal with an average power level, for example, 3σ below the clipping level will result in less than 0.2% clipping.

19.5.5 Carrier Frequency and mm-Wave Technology Aspects

Designing a receiver at, for example, 30 GHz with a 1 GHz signal bandwidth leaves much less design margin than what would be the case for a 2 GHz carrier frequency, f_carrier with, for example, 50 MHz signal bandwidth. The IC technology speed is similar in both cases but the design margin and performance depend on the technology being much faster than the required signal processing, which means that the 2 GHz design will have better performance.

The graph shows expected evolution of some transistor parameters important for mm-wave IC design, as predicted by the International Technology Roadmap for Semiconductors (ITRS). Here f_t, f_max, and V_dd/BV_ceo data from the ITRS 2007 targets [39] for CMOS and bipolar RF technologies are plotted vs the calendar year when the technology is anticipated to become available. f_t is the transistor transit frequency (that is, where the RF device's current gain is 0 dB), and f_max is the maximum frequency of oscillation (that is, when the extrapolated power gain is 0 dB). V_dd is the RF/high-performance CMOS supply voltage and BV_ceo is the bipolar transistor’s collector–emitter base open breakdown voltage limits. For example, an RF CMOS device is expected to have a maximum V_dd of 750 mV by 2020 (other supply voltages will be available as well, but at a lower speed).

The free space wavelength at 30 GHz is only 1 cm, which is one tenth of what is the case for existing 3GPP bands below 6 GHz. Antenna size and path loss are related to wavelength and carrier frequency, and to compensate the small physical size of a single antenna element multiple antennas, for example, array antennas will have to be used. When beam-forming is used the spacing between antenna elements will still be related to the wavelength, constraining the size of the FE and RX. Some of the implications of these frequency and size constraints are:

Increasing the carrier frequency from 2 GHz to 30 GHz (that is >10×) has a significant impact on the circuit design and its RF performance. For example, modern high-speed CMOS devices are velocity saturated and their maximum operating frequency is inversely proportional to the minimum channel length, or feature size. This dimension halves roughly every 4 years, as per Moore’s law (stating that complexity, that is transistor density, doubles every other year). With smaller feature sizes, internal voltages must also be lowered to limit electrical fields to safe levels. Thus, designing a 30 GHz RF receiver corresponds to designing a 2 GHz receiver using about 15-year-old low-voltage technology (that is today’s breakdown voltage but 15 years old F_t (see Fig. 19.18) with ITRS device targets). With such a mismatch in device performance and design margin it is not to be expected to maintain both 2 GHz performance and power consumption at 30 GHz.

The signal bandwidth at mm-wave frequencies will also be significantly higher than at 2 GHz. For an active device, or circuit, the signal swing is limited by the supply voltage at one end and by thermal noise at the other. The available thermal noise power of a device is proportional to BW/g_m, where g_m is the intrinsic device gain (trans-conductance). As g_m is proportional to bias current it can be seen that the dynamic range becomes the ratio

$\mathrm{DR}\propto \frac{V_{\mathrm{dd}}^2·I_{\mathrm{bias}}}{\mathrm{BW}}=\frac{V_{\mathrm{dd}}·P}{\mathrm{BW}}$

or

$P\propto \frac{\text{BW}·\text{DR}}{V_{\mathrm{dd}}}$

where P is the power dissipation.

Receivers for mm-wave frequencies will have increased power consumption due to their higher BW, aggravated by the low-voltage technology needed for speed, compared to typical 2 GHz receivers. Thus, considering the thermal challenges given the significantly reduced area/volume for mm-wave products, the complex interrelation between linearity, NF, bandwidth, and dynamic range in the light of power dissipation should be considered.