8
Having covered a lot of theoretical ground and described the detail of a number of standards earlier in this book, the purpose of this chapter is to give practical advice in configuring, timing, testing and maintaining digital video interface systems. The techniques and tools needed to test digital interfaces are quite different to the traditional analog approach and will be described here. The great similarity between HD-SDI and SD-SDI means that the same installation and test principles apply. In practice the higher frequency of the HD signal means that the effect of a shortcoming will be more serious in HD.
8.1 Digital Video Routing
Digital routers have the advantage that they need cause no loss of signal quality as they simply pass on a series of numbers. Analog routers inevitably suffer from crosstalk and noise, however well made, and this reduces signal quality on every pass.
The parallel router is complex because of the large number of conductors to be switched and is obsolete. A serial router is potentially very inexpensive as it is a single-pole device. It can be easier to build than an analog router because the digital signal is more resistant to crosstalk. Large routers can easily be implemented with SDI and the long cable drive capability means that large broadcast installations can be tackled.
A serial router can be made using wideband analog switches, so that the input waveform is passed from input to output. This is an inferior approach, as the total length of cable that can be used is restricted; the input cable is effectively in series with the output cable and the analog losses in both will add.
The correct approach is for each router input to reclock and slice the waveform back to binary. Figure 8.1 shows a typical reclocking SDI router. Following the input reclocking stage the actual routing takes place on logic level signals prior to a line driver that relaunches a clean signal. The cables to and from the router can be maximum length as the router is effectively a repeater.
Figure 8.1 A router for SDI signals should be constructed as shown here with a reclocker/slicer at each input to restore the received waveform to clean binary logic levels. The routing matrix proper is then a logic element which is followed by SDI line drivers. If this is not done the output cable is electrically in series with the input cable and the performance margin will be impaired. There is no need to descramble or decode the signal as the router is not interested in its meaning.
It is not necessary to unscramble the serial signal at the router. A phase-locked loop is used to regenerate the bit clock. This rejects jitter on the incoming waveform. The waveform is sliced, and the slicer output is sampled by locally regenerated clock. The result is a clean binary waveform, identical to the original driver waveform. The Gennum GS9005 is an equalizer/reclocker suitable for such an application because it does not descramble the data stream.
The router is simply a binary bitstream switch, and is not unduly concerned with the meaning or content of the bitstream. It does not matter whether the bitstream is HD, PAL, NTSC or 4:2:2 or whether or not ancillary data are carried – the information just passes through.
The only parameter of any consequence is the bit rate. HD runs at 1.485 Gbits/s, SD component runs at 270 or 360 Mbits/s, PAL runs at 177 Mbits/s and NTSC runs at 143 Mbits/s. Whilst it is possible to make a router that will handle HD or SD, this would currently be an expensive option. Many multi-standard routers require a link or DIP switch to be set in each input in order to select the appropriate VCO centre frequency. A separate VCO adjustment may be present for each standard. Otherwise units can be standards independent, which allows more flexibility and economy. With a mixed standard router, it is only necessary to constrain the control software so that inputs of a given standard can only be routed to outputs connected to devices of the same standard and one router can then handle component and composite signals simultaneously.
8.2 Timing in Digital Installations
The issue of signal timing has always been critical in analog video, but the adoption of digital routing relaxes the requirements considerably. Analog vision mixers need to be fed by equal length cables from the router to prevent propagation delay variation. In the digital domain this is no longer an issue as delay is easily obtained and each input of a digital vision mixer can have its own local timebase corrector. Provided signals are received having timing within the window of the inputs, all inputs are retimed to the same phase within the mixer.
Figure 8.2 shows how a mixing suite can be timed to a large SDI router. Signals to the router are phased so that the router output is aligned to station reference within a microsecond or so. The delay in the router may vary with its configuration but only by a few microseconds. The mixer reference is set with respect to station reference so that local signals arrive towards the beginning of the input windows and signals from the router (which, having come farther, will be the latest) arrive towards the end of the windows. Thus all sources can be retimed within the mixer and any signal can be mixed with any other. Clearly the mixer introduces delay, and the signal feedback to the router experiences further delay. In order to send the mix back to the router a frame synchronizer is needed on the output of the suite. This introduces somewhat less than a frame of delay so that by the time the signal has re-emerged from the router it is aligned to station reference once more, but a frame late. An installation of this kind relies on a gen-lockable sync pulse generator having multiple outputs with independent phase control.
Figure 8.2 In large systems some care is necessary with signal timing as is shown here. See text for details.
In an ideal world, every piece of hardware in the station would have component SDI outputs and inputs, and everything would be connected by SDI cable. In practice, unless the building is new, this is unlikely. However, there are ways in which SDI can be phased in alongside analog systems. An expensive way of doing this is to fit every composite device with coders and decoders, and every analog device with convertors so that a component SDI router can be used alone. Figure 8.3 shows an alternative. The SDI router is connected to every piece of digital equipment. Analog equipment continues to be connected to an analog router, and interconnection paths, called gateways, are created between the two routers. These gateways require convertors in each direction, but the number of convertors is much less than if every analog device was equipped. The number of gateways will be determined by the number of simultaneous transactions between analog and digital domains.
Figure 8.3 Digital routers can operate alongside existing analog routers as an economical means of introducing digital routing.
In many cases the two routers can be made to appear like one large router if appropriate software is available in a common control system. This will only be possible if the SDI router is purchased from the same manufacturer as the existing analog router or if the SDI router manufacturer offers custom software.
Whilst modern DVTRs incorporate the audio data in the SDI signal, adapting older devices to do this and subsequently demultiplexing the audio could prove expensive. DVTRs tend also to be inflexible in their audio selection. For example, it may not be possible to record certain audio channels from embedded SDI data at the same time as other channels from the AES/EBU inputs. Also the embedded audio may not contain timecode even though the standard allows it. As a result in some installations it may be more appropriate to retain an earlier audio router, or to have a separate AES/EBU digital audio router layer controlled in parallel with the SDI router.
If the analog router handles composite signals, then coders and decoders will be needed in addition to the convertors. In this case the use of gateways obviates unnecessary codecs when analog devices are connected together.
8.3 Configuring SDI Links
The viability of an SDI link is governed primarily by data rate and proposed distance. It is quite easy to establish what grade of cable will be required from the tables in Chapter 7. As can be seen from Figure 8.4, the data integrity deteriorates rapidly beyond a critical cable length. The sudden upswing in bit error rate is known as the ‘crash knee’ and for reliability only operation to the left of the knee is possible. Figure 8.4 shows the situation for SD. For HD, a similar trend will be observed, but the cable length values should be divided by approximately two.
Figure 8.4 Because of the multiplicative effect of the large number of factors causing signal degradation the error rate increases steeply after a certain cable length. This sudden onset of errors is referred to as the ‘crash knee’.
The existence of the crash knee makes it obvious that quoted cable length figures should not be stretched. As SDI is a point-to-point interface all receivers are equipped with an internal terminator. Thus there is no such thing as passive loop-through and use of a coaxial T-piece for monitoring is ruled out. Active loop-through means that, in the case of a power failure, the loop-through signal will fail. If it is required to drive multiple destinations, a digital distribution amplifier will be needed.
If the distance required is excessive even for the best grade of cable then a repeater will be required. Unlike an analog repeater, a properly engineered digital repeater causes no generation loss and minimal delay. Figure 8.5 shows a typical reclocking repeater. The repeater is not interested in the meaning of the data and need not descramble or deserialize the data stream. It is only necessary to reclock with a phase-locked loop to reject jitter and slice to reject noise. The resultant clean logic level signal can then be supplied to a further SDI cable driver.
Figure 8.5 In a reclocking repeater the input signal is equalized, sliced and reclocked with a phase-locked loop to recover a clean binary signal which then passes to an SDI line driver.
Such a simple reclocking repeater is of limited use in an EDH system as there is no ability to distinguish errors occurring before or after the repeater. If this is important an EDH supporting repeater will be necessary. By definition such a device must descramble and deserialize the data stream in order to make the error-detecting checks on the incoming data. As a result it will cause a greater signal delay than a simple reclocking repeater.
8.4 Testing Digital Video Interfaces
Once video and audio are converted to the digital domain, they become data, or numbers, and if those numbers can be delivered to the other end of a digital interface unchanged then the interface has not caused any loss of quality. This is one of the strengths of digital technology. In the absence of data reduction techniques, the quality is determined in the conversion process and can then be maintained in transmission and recording. In contrast analog signals are subject to generation loss in every recording and to noise and distortion in every transmission. This analog heritage has led to a philosophy where the analog waveform is monitored at every stage so that some adjustment can be made to minimize the quality loss. The waveform monitor and vectorscope tradition is so strong that despite the transition to the radically different digital technology many people think no new monitoring methods are needed.
Unfortunately, traditional analog testing techniques reveal nothing about a digital interface or recorder. Consider the system of Figure 8.6, which could be composite or component. An ADC converts the input waveform to data that are transmitted by the interface. A DAC converts the received data to analog video once more. If a waveform monitor and vectorscope are connected to the DAC, what information is revealed about the interface? If it is assumed that the interface is not suffering bit errors, the monitoring tells us how good the ADC and DAC are, but reveals nothing about the performance of the interface. The interface could be working with 20 dB of noise immunity, or it could be within a whisker of failure. Should the system be marginal such that one bit fails per minute, this will be invisible on an analog monitoring system in the presence of programme material and may just be detectable on colour bars. If the problem is due to a phase-locked loop drifting in an SDI receiver or damp penetration in a cable, it is going to get worse and in the absence of a warning the result will be a sudden failure.
Figure 8.6 Testing waveforms in the analog domain as shown here reveals nothing about the performance margin of the digital interface.
Three distinct testing areas are required in digital video systems. First, on installation, it should be possible to verify that the link is working with an adequate safety margin and that the length of the link is not excessive for the cable type selected. Second, it is necessary to test the data integrity of the link to ensure that the BER (bit error rate) is acceptable and remains acceptable when the system is stressed or margined beyond the conditions it will experience in service. Third, digital systems can suffer from a problem having no parallel in the analog domain. This is the protocol error where the data transmission is flawless but the two units concerned cannot understand each other.
Although the SDI signal is digital in that it carries discrete data, it is an analog waveform as far as the cable and receiver equalizer are concerned. Waveform distortions will occur in the cable and noise and jitter will be added. The magnitude of these distortions indicates the likely reliability of the channel. Figure 8.7 shows that a correctly functioning digital receiver is specifically designed to reject the analog waveform distortions by making discrete decisions. By definition, in doing so it denies us knowledge of the signal quality. Thus what is needed is a complementary approach. Instead of rejecting the distortions to obtain discrete data, what is needed is a system that rejects the data in order to measure the magnitude of the distortions.
Figure 8.7 The reception process is deliberately designed to reject analog waveform distortions whereas only by measuring these can signal integrity be assessed. Thus the measurement process is diametrically opposed to normal reception and needs special techniques.
One approach is to assess the eye pattern generated by the received waveform. After equalization the eye opening should be clearly visible, and the size of the opening should be consistent with the length and type of cable used. If it is not, the noise and/or jitter margin may be inadequate. However, testing the eye pattern on the SDI requires a fast oscilloscope. Some test equipment samples the SDI waveform at high speed and buffers it so it can be seen on a conventional display. Many SDI receivers have a dedicated, buffered, test point for eye pattern monitoring.
Inspection of the eye pattern is acceptable for establishing that the basic installation is sound and has proper signal levels, termination impedance and equalization, but is not very good at detecting infrequent impulsive noise. Contact noise from electrical power installations such as air conditioners is unlikely to exist for long enough to find an eye pattern display. The technique of signature analysis is better suited to impulsive noise problems.
8.5 Signature Analysis
In a digital routing system, reliability is synonymous with data integrity. A data integrity testing system doesn’t care what the video waveform is, or indeed that it is a video waveform at all. A data integrity system considers the digital TV field as a block of binary data and simply checks whether that data was received with bit accuracy or not. The message is to forget the pictures and worry about the data.
Signature analysis is a data integrity testing technique using large quantities of data and tests down to extremely low bit error rates. As a digital interface having no bit errors is transparent, signature analysis is a useful way of verifying the transparency of a channel following installation or maintenance. Signature analysis requires a stationary test signal to be applied at the transmitting end of the interface. Stationary means that in the case of component video every frame contains identical data. In the case of composite video the data repeats every four fields (NTSC) or eight fields (PAL). Digitally generated colour bars are suitable but other patterns work equally well. The received data are then processed to generate a value known as a signature. In typical equipment the signature will be a four-digit hexadecimal number. If the transmitted data are always the same, the received signature should always be the same. Any change in the signature indicates that an error has occurred.
The signature generation process divides the incoming bitstream by a polynomial, as was described in Chapter 3. The remainder of the division expresses an entire frame in component or an entire colour sequence in composite as a single signature word. A change of a single bit is enough to change the signature. Any number of bit errors up to the number of bits in the word will guarantee to change the signature, whereas larger numbers of errors are detected with a high degree of probability. In the presence of high error rates the occasional misdetection is irrelevant as the goal of the testing is to determine whether or not remedial action is necessary.
Signature analysis is similar in principle to EDH except that the signature is not transmitted with the data. This avoids complexity at the transmitting end and the need to reserve word positions in the data. As the transmitted data is not a codeword, the remainder will not necessarily be non-zero but could have any value. An error is indicated when the received signature changes, not by its absolute value.
Signature analysis can be used in two ways shown in Figure 8.8. In absolute analysis, shown in (a), the test signal comes from a special generator that displays the signature of the data. The data are fed down the channel under test and then into the signature analyser. The signature displayed on the analyser is compared with the signature on the generator. If the two remain identical for an extended period, then no errors are occurring.
Figure 8.8 In absolute signature analysis (a) the signature at the generator is known and can be compared with the received signature. In relative analysis (b) the signature is unknown but if the generator is known to be static the signature should be constant. Thus changes in the received signature indicate errors.
It is also possible to use a relative detection method, shown in (b). In relative signature analysis, any stationary generator can be used. The correct signature is not known, but if errors occur, the displayed signature will not be stable but will change. Thus in relative signature analysis the goal is not that the signature is correct but that it should not change for an extended period. Relative signature analysis cannot detect permanent errors, such as a stuck bit in a parallel interface, as the same signature will always be obtained and so its use is restricted to systems having no hard faults.
In case of doubt, the test pattern signature can easily be obtained by connecting the generator directly to the signature analyser as well as to the path under test.
Signature analysers can be designed to work on specific parts of the transmission only. If the interface is carrying programme material, the signature will vary from frame to frame. However, the ancillary data slots can still be used for signature analysis.
In component systems, the signature analyser may be set to operate on only one selected component. Some machines can be set to operate only on selected bits in the sample, making stuck bits in parallel systems very easy to find.
As signature analysis works in the data domain, it cannot be used to test a channel in which the received data are not necessarily the same as the transmitted data. There are a number of cases in which this could occur. If the digital signal is returned to the analog domain and then converted back to digital, noise in the analog domain will cause data differences. In DVTRs, uncorrectable errors due to dropouts result in concealments and changed data values. Thus signature analysis can be used to detect concealment. Note that concealment errors are much less visible than general trans-mission errors by a factor of about 1000:1, i.e. 1000 concealment errors are about the same level of visibility as one transmission error.
Systems using compression are not transparent and signature analysis is of no use if a compression codec is included in the test channel. In order to test the channel the generator must be connected after the compressor and before the decoder.
8.6 Margining
It is a characteristic of digital systems that failure is sudden because deteriorations in the signal are initially rejected until they grow serious enough to corrupt data. Put simply, just because a digital system is working today, there is no guarantee that it will work tomorrow unless its performance margin can be measured. Margining is a long established technique used in the computer industry to prove the reliability of a digital process by testing it under conditions more stressful than will be encountered in service. The degree of additional stress that can be applied before failure is a measure of the performance margin. As digital video is only data, margining techniques can be applied to it with great success and if used correctly will give a much needed confidence factor.
There are two ways in which an SDI system can be stressed. The first of these is to use a special signal generator producing pathological test patterns. These are bitstreams that mimic the convolution process of the SDI scrambler and result in channel signals containing less clock content and lower frequencies than usual. Receivers find it harder to decode pathological signals and so they will result in errors unless the system is in good shape.
A simple alternative to the pathological test signal is the use of a cable simulator that has the same effect as increasing the length of the cable between transmitter and receiver. The Faraday ‘cable clone’ is the best known of these devices. Figure 8.4 shows the non-linear relationship between cable length and error rate and illustrates the ‘crash knee’ in the characteristic. Testing with a cable simulator depends upon the existence of the crash knee. Figure 8.9(a) shows how the test is made. The cable under test is temporarily broken and the ‘cable clone’ is inserted. An error-monitoring system such as EDH or a signature analyser is connected after the receiver under test.
Figure 8.9 Margin testing requires the cable under test to be broken and a ‘cable clone’ or simulator to be inserted as in (a). The cable length is artificially increased until the crash knee is reached. The configuration in (b) is incorrect as the receiver to be used in service is not being tested. In fact the signature analyser’s receiver is being tested: a meaningless exercise.
The configuration shown in (b) is incorrect as it only tests the cable and the transmitter in conjunction with the receiver in the signature analyser. The important receiver is not tested. The cable clone must be installed in the cable and the signature analyser must be connected after the receiver under test.
With the cable clone set to bypass, the system should show no errors. If errors are detected the fault should be rectified. Starting with an error-free system the cable length is gradually increased until a rapid increase in error rate indicates that the crash knee has been reached. The additional length of cable needed to reach the crash knee is a direct measure of the performance margin or head height. It will be seen from Figure 8.4 that the error rate changes from negligible to intolerable with an increase in length of only 20–30 metres. Clearly if less than this figure is achieved in the margining test the system is marginal and should not be put into service.
One potential problem area frequently overlooked is to ensure that the VCO in the receiving phase-locked loop is correctly centred. If it is not, it will be running with a static phase error and will not sample the received waveform at the centre of the eyes. The sampled bits will be more prone to noise and jitter errors. VCO centring can be checked in a number of ways. If a frequency meter is available, this can be used to display the VCO frequency without input. Another method is to display the control voltage. This should not change significantly when the input is momentarily disconnected. However, the best method is to adjust for minimum error rate in conjunction with margining. Errors can be seen on a video monitor.
Using a cable clone, cable length is added until a slight error rate is caused. The VCO centre frequency is now adjusted one way or the other to see if the error rate can be reduced or even eliminated. If there is a range of error-free adjustment, more cable length should be switched in to make a finer adjustment.
In many receivers, the phase-locked loop will stay in lock more readily than it can achieve lock. Thus the VCO can be misadjusted whilst a signal is being received and will continue to lock to it. However, if the input signal is interrupted, lock will be lost. Consequently a good method is to adjust for the minimum errors after an interruption of the signal.
Some early SDI receivers run quite hot and the VCO centre frequency changes with temperature. Placing cards on an extender board may change the airflow enough to alter the centre frequency.
In digital systems it is possible for problems to occur in which the data transmission is flawless but communication is still not achieved. This can happen where the transmitter and receiver have incompatible protocols. The protocol of a signal includes the nature and positioning of TRS patterns, the location of EDH blocks and embedded audio. A further consideration is that in order correctly to adjust analog-to-digital convertors it is necessary to monitor the actual code values coming from a convertor and compare them with the original analog voltages.
Such problems can only be addressed by use of a logic analyser. General-purpose logic analysers can be used on parallel interfaces, but for best results a dedicated digital video analyser is to be preferred. Figure 8.10 shows the layout of a video analyser. An SDI receiver and/or a parallel receiver drive a decoder that identifies TRS patterns for synchronizing purposes. Incoming words are written into a page of RAM that can hold the contents of a few lines of video. The analyser thus takes a snapshot of interface activity. The point within the frame at which the snapshot is taken is determined by the trigger criteria provided to the RAM write logic.
Figure 8.10 A video analyser allows a snapshot of digital video interface activity to be captured in RAM. This data can then be inspected at leisure using a small computer.
Once the RAM is written in real time with the digital video snapshot, the data are frozen and can be inspected using the associated PC and its display. Signals can be displayed graphically as they would appear on conventional analog waveform monitors or vectorscopes, but can also be displayed as tabular data so that the exact binary word values and positions can be established. Any departures from correct protocol can be detected by comparing the data with the relevant standards.
Figure 8.11 shows how a video analyser is used to set up a component ADC. Convertor set-up is critical as digital systems keep the data the same all down the line, so it has to be right from the outset. A precise analog test pattern generator is used to produce colour bars. The signal is looped through an analog waveform monitor to the ADC where it should be terminated with the actual terminator to be used in practice. This is necessary because terminator tolerance is such that changing a terminator can change the analog level by several digital code values. The generator level is adjusted until the waveform monitor displays exactly the correct amplitude in, say, the white bar.
Figure 8.11 Using a video analyser to set the gain of an ADC. The ADC output data are compared with standard values on a known part of the analog waveform.
The analyser then captures the ADC output and the black bar is located in waveform mode with the cursor. The actual data values at the cursor position are displayed, and these can be compared with the ideal so that any offset in the convertor can be revealed and adjusted out. By selecting the white bar the luminance convertor gain can be adjusted. Some analysers allow timed retriggering so that a new snapshot is taken periodically. This mode is useful when making dynamic gain adjustments. The colour difference signal gains are set up in a similar manner.
The analog Y/C timing should be checked with a suitable signal such as bowtie before returning to colour bars to check the relative timings of the green/magenta transitions in the three digital components. This is not as easy as it sounds as the colour difference sample spacing is twice that of luminance and the sample values need to be interpreted carefully to find the transition.