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by Dr. James Aweya
Switch/Router Architectures
Cover
Series Page
Title Page
Copyright
About the Author
Preface
Chapter 1: Introduction to Switch/Router Architectures
1.1 Introducing the Multilayer Switch
1.2 Evolution of Multilayer Switch Architectures
Chapter 2: Understanding Shared-Bus and Shared-Memory Switch Fabrics
2.1 Introduction
2.2 Switch Fabric Design Fundamentals
2.3 Types of Blocking in Switch Fabrics
2.4 Emerging Requirements for High-Performance Switch Fabrics
2.5 Shared Bus Fabric
2.6 Hierarchical Bus-Based Architecture
2.7 Distributed Output Buffered Fabric
2.8 Shared Memory Switch Fabric
2.9 Shared Ring Fabric
2.10 Electronic Design Problems
Chapter 3: Shared-Bus and Shared-Memory-Based Switch/Router Architectures
3.1 Architectures with Bus-Based Switch Fabrics and Centralized Forwarding Engines
3.2 Architectures with Bus-Based Switch Fabrics and Distributed Forwarding Engines
3.3 Architectures with Shared-Memory-Based Switch Fabrics and Distributed Forwarding Engines
3.4 Relating Architectures to Multilayer Switch Types
Chapter 4: Software Requirements for Switch/Routers
4.1 Introduction
4.2 Switch/Router Software Development Methods
4.3 Stability of the Routing Protocols
4.4 Network Management
4.5 Switch/Router Performance
4.6 Interaction Between Layer 3 (Routing) and Layer 2 (Bridging) Functions in Switch/Routers
4.7 Control and Management of Line Cards
4.8 Distributed Forwarding
Chapter 5: Architectures with Bus-Based Switch Fabrics: Case Study—Decnis 500/600 Multiprotocol Bridge/Router
5.1 Introduction
5.2 In-Place Packet Forwarding in Line Cards
5.3 Main Architectural Features of the Decnis 500/600
5.4 Decnic 500/600 Forwarding Philosophy
5.5 Detail System Architecture
5.6 Unicast Packet Reception in a Line Card
5.7 Unicast Packet Transmission in a Line Card
5.8 Multicast Packet Transmission in a Line Card
Chapter 6: Architectures with Bus-Based Switch Fabrics: Case Study—Fore Systems Powerhub Multilayer Switches
6.1 Introduction
6.2 Powerhub 7000 and 6000 Architectures
6.3 Powerhub Software Architecture
6.4 Packet Processing in the PowerHub
6.5 Looking Beyond the First-Generation Architectures
Chapter 7: Architectures with Bus-Based Switch Fabrics: Case Study—Cisco Catalyst 6000 Series Switches
7.1 Introduction
7.2 Main Architectural Features of the Catalyst 6000 Series
7.3 High-Level Architecture of the Catalyst 6000
7.4 Catalyst 6000 Control Plane Implementation and Forwarding Engines: Supervisor Engines
7.5 Catalyst 6000 Line Card Architectures
7.6 Packet Flow in the Catalyst 6000 with Centralized Flow Cache-Based Forwarding
Chapter 8: Architectures with Shared-Memory-Based Switch Fabrics: Case Study—Cisco Catalyst 3550 Series Switches
8.1 Introduction
8.2 Main Architectural Features of the Catalyst 3550 Series
8.3 System Architecture
8.4 Packet Forwarding
8.5 Catalyst 3550 Software Features
8.6 Catalyst 3550 Extended Features
Chapter 9: Architectures with Bus-Based Switch Fabrics: Case Study—Cisco Catalyst 6500 Series Switches with Supervisor Engine 32
9.1 Introduction
9.2 Cisco Catalyst 6500 32 Gb/s Shared Switching Bus
9.3 Supervisor Engine 32
9.4 Catalyst 6500 Line Cards Supported by Supervisor Engine 32
9.5 Cisco Catalyst 6500 32 Gb/s Shared Switching Bus Modes
9.6 Supervisor Engine 32 QoS Features
9.7 Packet Flow Through Supervisor Engine 32
Chapter 10: Architectures with Shared-Memory-Based Switch Fabrics: Case Study—Cisco Catalyst 8500 CSR Series
10.1 Introduction
10.2 Main Architectural Features of the Catalyst 8500 Series
10.3 The Switch-Route and Route Processors
10.4 Switch Fabric
10.5 Line Cards
10.6 Catalyst 8500 Forwarding Technology and Operations
10.7 Catalyst 8500 Quality-of-Service Mechanisms
Chapter 11: Quality of Service Mechanisms in the Switch/Routers
11.1 Introduction
11.2 QoS Forwarding Operations within a Typical Layer 2 Switch
11.3 QoS Forwarding Operations within a Typical Multilayer Switch
11.4 QoS Features in the Catalyst 6500
Chapter 12: Quality of Service Configuration Tools in Switch/Routers
12.1 Introduction
12.2 Ingress QoS and Port Trust Settings
12.3 Ingress and Egress Port Queues
12.4 Ingress and Egress Queue Thresholds
12.5 Ingress and Egress QoS Maps
12.6 Ingress and Egress Traffic Policing
12.7 Weighted Tail-Drop: Congestion Avoidance with Tail-Drop and Multiple Thresholds
12.8 Congestion Avoidance with Wred
12.9 Scheduling with WRR
12.10 Scheduling with Deficit Weighted Round-Robin (DWRR)
12.11 Scheduling with Shaped Round-Robin (SRR)
12.12 Scheduling with Strict Priority Queuing
12.13 Netflow and Flow Entries
Chapter 13: Case Study: Quality of Service Processing in the Cisco Catalyst 6000 and 6500 Series Switches
13.1 Introduction
13.2 Policy Feature Card (PFC)
13.3 Distributed Forwarding Card (DFC)
13.4 Port-Based ASICs
13.5 QoS Mappings
13.6 QoS Flow in the Catalyst 6000 and 6500 Family
13.7 Configuring Port Asic-Based QoS on the Catalyst 6000 and 6500 Family
13.8 IP Precedence and IEEE 802.1p CoS Processing Steps
Appendix A: Ethernet Frame
A.1 Introduction
A.2 Ethernet Frame Format
Appendix B: IPv4 PACKET
B.1 Introduction
B.2 IPv4 Packet Format
B.3 IPv4 ADDRESSING
B.4 Address Resolution
B.5 IPv4 Address Exhaustion
B.6 IPv4 Options
B.7 IPv4 Packet Fragmentation and Reassembly
B.8 IP Packets Encapsulated into Ethernet Frames
B.9 Forwarding IPv4 Packets
References
Index
End User License Agreement
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