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by Octavian Lascu
IBM z14 (3906) Technical Guide
Front cover
Notices
Trademarks
Preface
Authors
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Chapter 1. Introducing the IBM z14
1.1 Design considerations for the IBM z14
1.2 z14 server highlights
1.2.1 Processor and memory
1.2.2 Capacity and performance
1.2.3 Virtualization
1.2.4 I/O subsystem and I/O features
1.2.5 Reliability, availability, and serviceability design
1.3 z14 server technical overview
1.3.1 Models
1.3.2 Model upgrade paths
1.3.3 Frames
1.3.4 CPC drawer
1.3.5 I/O connectivity: PCIe Generation 3
1.3.6 I/O subsystem
1.3.7 I/O and special purpose features in the PCIe I/O drawer
1.3.8 Storage connectivity
1.3.9 Network connectivity
1.3.10 Coupling and Server Time Protocol connectivity
1.3.11 Cryptography
1.3.12 zEDC Express
1.4 Reliability, availability, and serviceability
1.5 Hardware Management Consoles and Support Elements
1.6 Operating systems
1.6.1 Supported operating systems
1.6.2 IBM compilers
Chapter 2. Central processor complex hardware components
2.1 Frames and drawers
2.1.1 The A frame
2.1.2 Z Frame
2.1.3 z14 cover (door) design
2.1.4 Top exit I/O cabling
2.1.5 PCIe I/O drawer
2.2 CPC drawer
2.2.1 CPC drawer interconnect topology
2.2.2 Oscillator
2.2.3 System control
2.2.4 CPC drawer power
2.3 Single chip modules
2.3.1 Processor unit chip
2.3.2 Processor unit (core)
2.3.3 PU characterization
2.3.4 System Controller chip
2.3.5 Cache level structure
2.4 Memory
2.4.1 Memory subsystem topology
2.4.2 Redundant array of independent memory
2.4.3 Memory configurations
2.4.4 Memory upgrades
2.4.5 Drawer replacement and memory
2.4.6 Virtual Flash Memory
2.4.7 Flexible Memory Option
2.4.8 Pre-planned memory
2.5 Reliability, availability, and serviceability
2.5.1 RAS in the CPC memory subsystem
2.5.2 General z14 RAS features
2.6 Connectivity
2.6.1 Redundant I/O interconnect
2.6.2 Enhanced drawer availability
2.6.3 CPC drawer upgrade
2.7 Model configurations
2.7.1 Upgrades
2.7.2 Concurrent PU conversions
2.7.3 Model capacity identifier
2.7.4 Model capacity identifier and MSU value
2.7.5 Capacity Backup
2.7.6 On/Off Capacity on Demand and CPs
2.8 Power and cooling
2.8.1 Power and cooling
2.8.2 High Voltage Direct Current power feature
2.8.3 Internal Battery Feature
2.8.4 Power estimation tool
2.8.5 Cooling
2.8.6 Radiator Unit
2.8.7 Water-cooling unit
2.9 Summary
Chapter 3. Central processor complex system design
3.1 Overview
3.2 Design highlights
3.3 CPC drawer design
3.3.1 Cache levels and memory structure
3.3.2 CPC drawer interconnect topology
3.4 Processor unit design
3.4.1 Simultaneous multithreading
3.4.2 Single-instruction multiple-data
3.4.3 Out-of-Order execution
3.4.4 Superscalar processor
3.4.5 Compression and cryptography accelerators on a chip
3.4.6 Decimal floating point accelerator
3.4.7 IEEE floating point
3.4.8 Processor error detection and recovery
3.4.9 Branch prediction
3.4.10 Wild branch
3.4.11 Translation lookaside buffer
3.4.12 Instruction fetching, decoding, and grouping
3.4.13 Extended Translation Facility
3.4.14 Instruction set extensions
3.4.15 Transactional Execution
3.4.16 Runtime Instrumentation
3.5 Processor unit functions
3.5.1 Overview
3.5.2 Central processors
3.5.3 Integrated Facility for Linux
3.5.4 Internal Coupling Facility
3.5.5 IBM Z Integrated Information Processor
3.5.6 System assist processors
3.5.7 Reserved processors
3.5.8 Integrated firmware processor
3.5.9 Processor unit assignment
3.5.10 Sparing rules
3.6 Memory design
3.6.1 Overview
3.6.2 Main storage
3.6.3 Hardware system area
3.6.4 Virtual Flash Memory
3.7 Logical partitioning
3.7.1 Overview
3.7.2 Storage operations
3.7.3 Reserved storage
3.7.4 Logical partition storage granularity
3.7.5 LPAR dynamic storage reconfiguration
3.8 Intelligent Resource Director
3.9 Clustering technology
3.9.1 CF Control Code
3.9.2 Coupling Thin Interrupts
3.9.3 Dynamic CF dispatching
3.10 Virtual Flash Memory
3.10.1 IBM Z Virtual Flash Memory overview
3.10.2 VFM feature
3.10.3 VFM administration
Chapter 4. Central processor complex I/O system structure
4.1 Introduction to I/O infrastructure
4.1.1 I/O infrastructure
4.1.2 PCIe Generation 3
4.2 I/O system overview
4.2.1 Characteristics
4.2.2 Supported I/O features
4.3 PCIe I/O drawer
4.4 PCIe I/O drawer offerings
4.5 Fanouts
4.5.1 PCIe Generation 3 fanout (FC 0173)
4.5.2 Integrated Coupling Adapter (FC 0172)
4.5.3 HCA3-O (12x IFB) fanout (FC 0171)
4.5.4 HCA3-O LR (1x IFB) fanout (FC 0170)
4.5.5 Fanout considerations
4.6 I/O features (cards)
4.6.1 I/O feature card ordering information
4.6.2 Physical channel ID report
4.7 Connectivity
4.7.1 I/O feature support and configuration rules
4.7.2 Storage connectivity
4.7.3 Network connectivity
4.7.4 Parallel Sysplex connectivity
4.8 Cryptographic functions
4.8.1 CPACF functions (FC 3863)
4.8.2 Crypto Express6S feature (FC 0893)
4.8.3 Crypto Express5S feature (FC 0890)
4.9 Integrated firmware processor
4.10 zEDC Express
Chapter 5. Central processor complex channel subsystem
5.1 Channel subsystem
5.1.1 Multiple logical channel subsystems
5.1.2 Multiple subchannel sets
5.1.3 Channel path spanning
5.2 I/O configuration management
5.3 Channel subsystem summary
Chapter 6. Cryptographic features
6.1 Cryptography enhancements on IBM z14 servers
6.2 Cryptography overview
6.2.1 Modern cryptography
6.2.2 Kerckhoffs’ principle
6.2.3 Keys
6.2.4 Algorithms
6.3 Cryptography on IBM z14 servers
6.4 CP Assist for Cryptographic Functions
6.4.1 Cryptographic synchronous functions
6.4.2 CPACF protected key
6.5 Crypto Express6S
6.5.1 Cryptographic asynchronous functions
6.5.2 Crypto Express6S as a CCA coprocessor
6.5.3 Crypto Express6S as an EP11 coprocessor
6.5.4 Crypto Express6S as an accelerator
6.5.5 Managing Crypto Express6S
6.6 TKE workstation
6.6.1 Logical partition, TKE host, and TKE target
6.6.2 Optional smart card reader
6.6.3 TKE hardware support and migration information
6.7 Cryptographic functions comparison
6.8 Cryptographic operating system support
Chapter 7. Operating system support
7.1 Operating systems summary
7.2 Support by operating system
7.2.1 z/OS
7.2.2 z/VM
7.2.3 z/VSE
7.2.4 z/TPF
7.2.5 Linux on IBM Z (Linux on Z)
7.2.6 KVM hypervisor
7.3 z14 features and function support overview
7.3.1 Supported CPC functions
7.3.2 Coupling and clustering
7.3.3 Network connectivity
7.3.4 Cryptographic functions
7.3.5 Special purpose features
7.4 Support by features and functions
7.4.1 LPAR Configuration and Management
7.4.2 Base CPC features and functions
7.4.3 Coupling and clustering features and functions
7.4.4 Storage connectivity-related features and functions
7.4.5 Networking features and functions
7.4.6 Cryptography Features and Functions Support
7.4.7 Special-purpose Features and Functions
7.5 z/OS migration considerations
7.5.1 General guidelines
7.5.2 Hardware Fix Categories (FIXCATs)
7.5.3 Coupling links
7.5.4 z/OS XL C/C++ considerations
7.5.5 z/OS V2.3
7.6 z/VM migration considerations
7.6.1 z/VM 7.1
7.6.2 z/VM V6.4
7.6.3 ESA/390-compatibility mode for guests
7.6.4 Capacity
7.7 z/VSE migration considerations
7.8 Software licensing
7.9 References
Chapter 8. System upgrades
8.1 Upgrade types
8.1.1 Overview of upgrade types
8.1.2 Terminology that is related to CoD for z14 systems
8.1.3 Permanent upgrades
8.1.4 Temporary upgrades
8.2 Concurrent upgrades
8.2.1 Model upgrades
8.2.2 Customer Initiated Upgrade facility
8.2.3 Concurrent upgrade functions summary
8.3 Miscellaneous equipment specification upgrades
8.3.1 MES upgrade for processors
8.3.2 MES upgrades for memory
8.3.3 MES upgrades for I/O
8.3.4 Feature on Demand
8.3.5 Summary of plan-ahead features
8.4 Permanent upgrade through the CIU facility
8.4.1 Ordering
8.4.2 Retrieval and activation
8.5 On/Off Capacity on Demand
8.5.1 Overview
8.5.2 Capacity Provisioning Manager
8.5.3 Ordering
8.5.4 On/Off CoD testing
8.5.5 Activation and deactivation
8.5.6 Termination
8.5.7 z/OS capacity provisioning
8.6 Capacity for Planned Event
8.7 Capacity Backup
8.7.1 Ordering
8.7.2 CBU activation and deactivation
8.7.3 Automatic CBU enablement for GDPS
8.8 Nondisruptive upgrades
8.8.1 Components
8.8.2 Concurrent upgrade considerations
8.9 Summary of Capacity on-Demand offerings
Chapter 9. Reliability, availability, and serviceability
9.1 RAS strategy
9.2 Technology change
9.3 Structure change
9.4 Reducing complexity
9.5 Reducing touches
9.6 z14 availability characteristics
9.7 z14 RAS functions
9.7.1 Scheduled outages
9.7.2 Unscheduled outages
9.8 z14 enhanced drawer availability
9.8.1 EDA planning considerations
9.8.2 Enhanced drawer availability processing
9.9 z14 Enhanced Driver Maintenance
9.9.1 Resource Group and native PCIe MCLs
9.10 RAS capability for the HMC and SE
Chapter 10. Environmental requirements
10.1 Power and cooling
10.1.1 Rear cover design for vectored air output
10.1.2 Power requirements and consumption
10.1.3 Cooling requirements
10.1.4 Internal Battery Feature
10.1.5 Emergency power-off switch
10.2 Physical specifications
10.3 Physical planning
10.3.1 Raised floor or non-raised floor
10.3.2 Top Exit Power option
10.3.3 Top Exit I/O Cabling feature
10.3.4 Weight distribution plate
10.3.5 Bolt-down kit for raised floor
10.3.6 Nonraised floor frame tie-down kit
10.3.7 Service clearance areas
10.4 Energy management
10.4.1 Environmental monitoring
Chapter 11. Hardware Management Console and Support Elements
11.1 Introduction to the HMC and SE
11.2 HMC and SE changes and new features
11.2.1 Driver Level 36 HMC and SE new features
11.2.2 Driver Level 32 HMC and SE changes and features
11.2.3 Enhanced Computing and z14 HMC
11.2.4 Rack-mounted HMC
11.2.5 New SEs
11.2.6 New backup options for HMCs and primary SEs
11.2.7 SE driver support with the HMC driver
11.2.8 HMC feature codes
11.2.9 User interface
11.2.10 Customize Product Engineering Access: Best practice
11.3 HMC and SE connectivity
11.3.1 Network planning for the HMC and SE
11.3.2 Hardware prerequisite changes
11.3.3 TCP/IP Version 6 on the HMC and SE
11.3.4 OSA Support Facility changes
11.3.5 Assigning addresses to the HMC and SE
11.3.6 HMC Multi-factor authentication
11.4 Remote Support Facility
11.4.1 Security characteristics
11.4.2 RSF connections to IBM and Enhanced IBM Service Support System
11.4.3 HMC and SE remote operations
11.5 HMC and SE key capabilities
11.5.1 Central processor complex management
11.5.2 LPAR management
11.5.3 Operating system communication
11.5.4 HMC and SE microcode
11.5.5 Monitoring
11.5.6 Capacity on-demand support
11.5.7 Server Time Protocol support
11.5.8 CTN Split and Merge
11.5.9 NTP client and server support on the HMC
11.5.10 Security and user ID management
11.5.11 HMC 2.14.1 Enhancements
11.5.12 System Input/Output Configuration Analyzer on the SE and HMC
11.5.13 Automated operations
11.5.14 Cryptographic support
11.5.15 Installation support for z/VM that uses the HMC
11.5.16 Dynamic Partition Manager
Chapter 12. Performance
12.1 IBM z14 performance characteristics
12.2 LSPR workload suite
12.3 Fundamental components of workload performance
12.3.1 Instruction path length
12.3.2 Instruction complexity
12.3.3 Memory hierarchy and memory nest
12.4 Relative Nest Intensity
12.5 LSPR workload categories based on relative nest intensity
12.6 Relating production workloads to LSPR workloads
12.7 Workload performance variation
12.7.1 Main performance improvement drivers with z14 servers
Appendix A. IBM Secure Service Container framework
A.1 What is IBM Secure Service Container?
A.2 SSC LPAR
A.3 Why Secure Service Container?
A.4 IBM Z servers and SSC
Appendix B. Channel options
Appendix C. Native Peripheral Component Interconnect Express
C.1 Design of native PCIe adapter management
C.2 Native PCIe feature plugging rules
C.3 Native PCIe feature definitions
Appendix D. Shared Memory Communications
D.1 Overview
D.2 Shared Memory Communication over RDMA
D.3 Shared Memory Communications - Direct Memory Access
Appendix E. IBM Dynamic Partition Manager
E.1 Introduction to IBM Dynamic Partition Manager
E.2 Reasons to use DPM
E.3 IBM Z servers and DPM
E.4 Setting up the DPM environment
Appendix F. IBM zEnterprise Data Compression Express
F.1 Overview
F.2 zEDC Express
F.3 Software support
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IBM z14 (3906)
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ISBN 0738457256
SG24-8451-01
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