4.1.1 Polytype Replication in SiC Epitaxy

As described in Chapter 2, 4H-SiC is the polytype chosen for major device applications. The polytypism of SiC means that perfect polytype control is an essential aspect of epitaxial growth of SiC. Early epitaxial growth of -SiC (mainly 6H-SiC at that time) was performed by liquid phase epitaxy (LPE) [1, 2] or CVD methods [3–6]. Although advantages of CVD include precise control and uniformities of epilayer thickness and impurity doping, polytype mixing was a serious problem. For example, in the case of 6H-SiC CVD on basal planes of 6H-SiC Lely platelets, a growth temperature as high as 1800 °C was required for reproducible homoepitaxy, with twinned crystalline 3C-SiC grown at lower temperatures [3–6].

The concept of perfect polytype replication in 6H-SiC epitaxial layers on 6H-SiC substrates was proposed by Matsunami et al. in 1987 [7, 8]. They investigated the polytype of SiC layers grown on substrates with various off-angles and different off-directions, and proposed the optimum off-direction and off-angle to achieve high-quality homoepitaxy of 6H-SiC [7]. Davis et al. also reported homoepitaxial growth of 6H-SiC on an off-axis substrate in 1987 [9, 10]. Using step-flow growth on 2–6° off-axis , homoepitaxial growth of 6H-SiC with a very smooth surface was achieved by CVD at 1450–1550 °C. In the same manner, homoepitaxial CVD growth of 4H-SiC was demonstrated on 5–6° off-axis [11]. This growth technique is applicable to homoepitaxy of other polytypes such as 15R-SiC and 21R-SiC. The success of 4H-SiC homoepitaxy and demonstration of high-performance 4H-SiC Schottky barrier diodes on the homoepitaxial layers [12, 13] triggered the exclusive development of 4H-SiC for power device applications. This epitaxial growth technique was named “step-controlled epitaxy”, since the polytype of the epilayers can be controlled by surface steps existing on the off-axis substrates. Homoepitaxial growth of high-quality SiC on off-axis substrates has been reviewed in numerous papers [14–26].

Figure 4.1 shows the surface morphology (a, d), -azimuth reflection high-energy electron diffraction (RHEED) pattern (b, e), and surfaces after etching with molten KOH (c, f) for epilayers grown on on-axis and 6° off-axis 6H-SiC(0001) substrates at 1500 °C at a growth rate of [15]. On an on-axis (0001) face, the epilayer exhibits a mosaic-like surface morphology, and relatively smooth domains are separated by step- or groove-like boundaries. From the RHEED analysis, the grown layer is identified as 3C-SiC(111) with twinning. Triangular etch pits indicating threefold symmetry are observed, which suggests the growth of cubic phase. Note that the etch pits are rotated by 180° relative to each other across the groove boundaries. This result means that the neighboring domains separated by the boundaries have a twin relationship, and form a so-called “double positioning twin” [27]. In contrast, the epilayers on off-axis substrates exhibit specular smooth surfaces, and the RHEED pattern shows the growth of single crystalline 6H-SiC(0001). The polytypes of the grown layers were verified by transmission electron microscope (TEM) observation, Raman scattering, and photoluminescence. Homoepitaxial layers with smooth surface morphology can also be obtained on an off-axis face.

The preferred off-direction is , because CVD growth on off-axis (0001) substrates inclined toward often exhibit a stripe-like morphology, which is caused by pronounced step bunching [8, 10]. The inclusion of 3C-SiC domains is occasionally observed after prolonged growth times on off-axis (0001) substrates inclined toward . Although successful epitaxial growth on off-axis (0001) inclined toward was reported [28], several degree (typically 4°) off-axis toward is the standard used in the state-of-the-art technology.

Figure 4.2 shows a schematic illustration of growth modes and stacking sequences of the layers grown on (a) on-axis 6H-SiC(0001) and (b) off-axis 6H-SiC(0001). The bond configuration near an atomic step and on the (0001) terrace is also shown in Figure 4.2c. The precursors are heated and decomposed in the gas phase or near the substrate, and the source species diffuse toward the substrate surface. Adsorbed species migrate on the surface and are incorporated into a crystal at steps and/or kinks where the potential is low. However, there exists another competitive growth process of nucleation on terraces, which takes place when the supersaturation is high enough. The detailed descriptions of both growth processes follow:

1. On on-axis , the step density is very low, and large terraces exist. Then, crystal growth may initially occur on terraces through two-dimensional nucleation because of high supersaturation. The polytype of the grown layers is determined by growth conditions, especially the growth temperature. This leads to the growth of 3C-SiC, which is stable at low temperature [29]. This phenomenon has been predicted by theoretical studies using a quantum-mechanical energy calculation [30] and an electrostatic model [31]. It is pointed out that defects such as polishing-induced damage on the surface can trigger 3C-SiC nucleation when the supersaturation is high [32]. Because the stacking order of 6H-SiC is ABCACB, the growing 3C-SiC can take two possible stacking orders of ABCABC and ACBACB, as shown in Figure 4.2a.
2. On off-axis , the step density is high, and the terrace width is narrow enough for adsorbed species to migrate and reach steps. At a step, the incorporation site (A, B, C) is uniquely determined by bonds from the step, as shown in Figure 4.2b. Hence, homoepitaxy can be achieved through the lateral growth from steps (step-flow growth), inheriting the stacking order of the substrate. Homoepitaxy with greatly improved crystal quality by using off-axis substrates has also been observed in sandwich-sublimation growth [33], LPE [34], and molecular beam epitaxy (MBE) [35] of hexagonal SiC. In general, step-flow growth on off-axis (vicinal) substrates has been extensively studied in many materials. In SiC epitaxy, the polytype of SiC epilayers can be controlled by the step density of substrates. The surface steps serve as a template, which forces the replication of the substrate polytype in the epilayer. This is the origin of the term “step-controlled epitaxy” [15].

Homoepitaxial growth of hexagonal at lower temperature has been investigated. The growth temperature can be reduced to 1200 °C or even lower without 3C-SiC inclusions [36, 37], but the density of surface defects, such as triangular defects, increases significantly with decreasing growth temperature. At such a low growth temperature, the growth rate must be kept low, below a few , to minimize 3C-SiC inclusions. A larger off-angle is helpful to achieve SiC homoepitaxy at low temperature. These results are described in a quantitative manner in the next subsection. Another severe problem that occurs during low-temperature growth is the considerable increase in the background nitrogen doping density. For example, the donor density of undoped SiC(0001) epilayers grown at 1200 °C is approximately [38], which is completely unacceptable for device fabrication.

4.1.2 Theoretical Model of SiC Homoepitaxy

A simple surface diffusion model based on the BCF (Burton, Cabrera, and Frank) theory [39] is considered, where steps with height are separated by an equal distance as shown in Figure 4.3. The adsorbed species diffuse on terraces toward steps. Some of the adsorbed species can reach steps and are incorporated into the crystal, and the others re-evaporate to the vapor. When nucleation on terraces does not occur, the continuity equation of adsorbed species is expressed by [39]:

4.1

where is the number of adsorbed species per unit area on the surface (hereafter, is described as the adatom density), the flux of reactants arriving at the surface, the mean residence time of adsorbed species, and the surface diffusion coefficient. Here, the steps are assumed to be uniform and to act as perfect sinks for the incoming species, that is, the capture probability of adsorbed species at steps is unity, independent of the direction from which the adsorbed species approach the steps. Under the boundary condition that the supersaturation ratio equals unity at steps: at , the adatom density on the terraces can be given as a solution of Equation 4.1:

4.2

where is the adatom density at equilibrium and is the surface diffusion length of adsorbed species, which is given by the following equation [39]:

4.3

Here, , , and are the jump distance (interatomic distance), the Boltzmann constant, and the absolute temperature, respectively. and are the activation energies for desorption and surface diffusion. This is an average length for adsorbed species to migrate on a “step-free” surface before desorption. In step-flow growth, the growth rate is given by the product of the step velocity and , where is the substrate's off-angle. Thus, the following equation is satisfied:

4.4

Here, is the density of adsorption sites on the surface ( for ).

Figure 4.4 shows the distribution of adatom density and the supersaturation ratio on a surface. Since takes a maximum value at the center of a terrace, nucleation occurs most easily at this location. Based on Equations 4.2 and 4.4, can be expressed by [39]:

4.5

depends on experimental conditions, such as the growth rate, growth temperature, and terrace width, and is an essential parameter that determines whether the growth mode is step-flow or two-dimensional nucleation. Because the two-dimensional nucleation rate increases exponentially with the supersaturation ratio on a surface, nucleation becomes significant when exceeds a critical value . Thus, the growth modes are determined according to the relationship between and as follows:

4.6

4.7

In the case of hexagonal SiC homoepitaxy on off-axis , stable step-flow growth is required to ensure homoepitaxy, as described above. Two-dimensional nucleation on terraces or “defect sites” is likely to lead to inclusions of 3C-SiC or other foreign polytypes.

Under the critical growth condition, should be equal to , which means that [40]

4.8

This is the basic equation that describes the growth mode on an off-axis substrate. In this equation, and are determined by growth conditions, is also dependent on the growth condition, due to the occurrence of step bunching, while is an inherent parameter of a material. If the values of and are known and several critical conditions are found experimentally, the surface diffusion length can be estimated from Equation 4.8. can be calculated from the equilibrium vapor pressure using Knudsen's equation (from the kinetic theory of gases) [41]. Here, can be calculated from the chemical equilibrium constants of the reaction system [40]. Because the supply of Si species mainly controls the growth in the present case, in SiC CVD growth can be assumed to be an equilibrium vapor pressure of the Si species that undergo surface reactions [36, 42]. The equilibrium vapor pressure of as a function of temperature is obtained from the equilibrium equations for several reactions between Si and hydrocarbon species [40].

Nucleation on terraces becomes dominant when exceeds a critical supersaturation ratio . When the critical nucleation rate is assumed to be , for example, which corresponds to one nucleation per unit time on a area, for a disk-shaped nucleus is given by the following equation [43]:

4.9

where and are the volume of a Si-C pair and the surface free energy. The surface free energy values of hexagonal have been calculated as 2220 and for (0001) and , respectively [44]. The step height can be determined by atomic force microscopy (AFM), and typically ranges from c/2 to several . The temperature dependence of for (0001)Si and faces is shown in Figure 4.5. The for face takes very low values, indicating that nucleation occurs much more frequently on the face than on the (0001)Si face under the same supersaturation conditions.

Critical growth conditions can be found through CVD growth experiments under various growth conditions. The growth temperature and off-angle are varied in the range of 1100–1700 °C and 0.2–10°, respectively. Table 4.1 summarizes some of the critical growth conditions at various growth temperatures for epitaxial growth of 4H-SiC(0001). These data are updated from an old reference [40]. Higher growth temperature, larger off-angle, and lower growth rate are preferable for homoepitaxy of 4H-SiC (step-flow growth). Furthermore, CVD growth with a low C/Si ratio (the ratio of carbon and silicon atoms in the supplied precursors) is beneficial to promote homoepitaxy [42].

Growth temperature ( °C)	Off-angle (°)	Growth rate
1100	6	0.8
1200	4	2.4
1400	1	14
1500	0.2	6
1600	2	90

Figure 4.6 shows the temperature dependence of surface diffusion length on 4H-SiC(0001), calculated from Equation 4.8 using several data points, as discussed above. In the figure, a dotted line denotes results of fitting to Equation 4.3. Since the surface diffusion lengths obtained in this study are the average lengths to migrate on a “step-free” surface before desorption, they decrease at high temperatures, where desorption is enhanced. The surface diffusion length on the C face has not been estimated due to the lack of various growth data. In an old study on , the diffusion length on the C face is much longer than that on the Si face [40]. Although nucleation occurs much more easily on the C faces, the longer surface diffusion lengths on the C face may compensate for the frequent nucleation on the terraces.

Because the temperature dependences of and have been obtained, critical growth conditions can be predicted using Equation 4.8. For example, if the growth temperature and off-angle of substrates (terrace width) are fixed, a critical growth rate (maximum growth rate to realize step-flow) can be calculated. Curves for these critical growth conditions are shown in Figure 4.7 for substrates with off-angles of 0.2°, 1°, 4°, and 8°. Note that this chart has been significantly updated from one presented in reference [40], because recent experimental data were employed in the analyses. In the figure, the top-left and bottom-right regions separated by the curves correspond to the two-dimensional nucleation (severe 3C-SiC inclusions) and step-flow growth (homoepitaxy) conditions, respectively. Growth with a high growth rate and small off-angle can proceed via a step-flow mode at high growth temperatures. At 1700 °C, a very small off-angle of 0.2°, which yields almost “on-axis” , is sufficient to achieve step-flow growth with a growth rate of about . The role of surface defects in nucleation of 3C-SiC becomes important on substrates with small off-angles [32]. Note that spiral growth around threading screw dislocations (TSDs) is not considered in the present model. Spiral growth naturally promotes homoepitaxial growth, and this effect is pronounced on with very small off-angles. Conversely, large off-angles greater than 4° are needed to achieve homoepitaxy at a low temperature of 1200 °C with a reasonable growth rate .

4.1.3 Growth Rate and Modeling

Under typical conditions for CVD growth of SiC, differences in the growth rates on different SiC faces such as (0001), , and are very small, indicating that the SiC growth is diffusion limited, and the supply of source species onto the growing surface is the rate-determining step [36].

Figure 4.8a shows the C/Si ratio dependence of the growth rate for CVD of off-axis 4H-SiC(0001) [45]. In this particular experiment, the C/Si ratio was varied by changing the flow rate while fixing the flow rate. When the C/Si ratio is lower than 1.0–1.3, the growth rate increases with increasing C/Si ratio ( flow rate). Above some C/Si ratio, the growth rate does not change if the C/Si ratio ( flow rate) is increased. In this saturation region, the growth rate is almost proportional to the flow rate. These are common trends in CVD growth of compound semiconductors. When the ambient is Si-rich, the growth rate is dominated by the carbon supply, whereas the growth rate is mainly determined by the silicon supply under C-rich conditions. Near the “kink point” (C/Si ), a nearly stoichiometric condition must be established on the growing surface. In general, very good surface morphology is obtained near this stoichiometric condition. When the C/Si ratio is too low, the surface suffers from formation of severe macrosteps and Si droplets. In contrast, surface morphological defects, such as triangular defects, are easily generated when the C/Si ratio is too high. The change in surface stoichiometry and supersaturation by changing the ratio of C and Si source supply was modeled and shown in Figure 4.8b.

Figure 4.9 shows the growth rate at 1650 °C versus flow rate at a fixed C/Si ratio of 1.2 [46]. The growth rate increases almost in proportion to the flow rate, and reaches at a flow rate of 20 sccm. However, at higher flow rates, the growth rate exhibits a sub-linear dependence on the flow rate and tends to saturate, when the growth was performed at 11 kPa. This is caused by Si polymerization in the gas phase, and is further discussed in the context of fast epitaxy (Section 4.4). This Si polymerization can be reduced by decreasing the growth pressure (4 kPa), and a high growth rate over can be attained. The intercept of the vertical axis in Figure 4.9 gives a negative value, which implies that etching of SiC by is faster than growth when the flow rate is very small. The etching rate of SiC by at 1600–1650 °C is estimated at when the pressure is 4 kPa.

Interaction between SiC and at high temperature is of academic and technological interest. At temperatures of 1500–1700 °C, silicon is removed by desorption because of its high equilibrium pressure, while carbon is removed as (or ) through reaction with .

4.10

4.11

Here “g” and “s” mean the gas phase and solid phase, respectively. Therefore, the etching becomes faster as the process pressure is decreased (because silicon desorption is enhanced at lower pressures), as long as sufficient is supplied for carbon removal. Conversely, silicon desorption is hampered at relatively high pressures, such as atmospheric pressure, although carbon removal is enhanced further at higher pressures. Thus, preferential etching of carbon proceeds at high pressure (and high temperature), leading to formation of silicon droplets. These silicon droplets are, of course, harmful for subsequent epitaxial growth. Addition of a small amount of HCl [19, 20, 47, 48] or hydrocarbon [49, 50] during etching is an effective way to obtain a clean SiC surface without silicon droplets. However, carbon removal by , as expressed by Equation 4.11, becomes extremely slow below 1200 °C. Therefore, when SiC is etched with at low pressure and at 900–1200 °C, preferential desorption of silicon takes place, leading to surface graphitization. Annealing SiC in vacuum at high temperature is one way to form graphene on the SiC surface [51–53]. By treatment of SiC at atmospheric pressure and about 1000 °C, a clean SiC surface passivated with hydrogen can be obtained [54].

Chemistries in SiC CVD have been studied intensively. Allendorf and Kee analyzed gas-phase and surface reactions at 1200–1600 °C in a system [55]. Stinespring and Wohmhoudt also reported similar analysis of gas-phase kinetics [56]. Their analyses have shown that the dominant species that contribute to SiC growth are Si, , and species from , and , and molecules from . These simulation results suggest that Si (or ) may be preferentially adsorbed and then migrates on the surface. In fact, very little deposition of carbon films occurs in a standard CVD system if is not supplied.

Nishizawa and Pons [57–60] and Danielsson et al. [61, 62] established accurate simulation models for SiC CVD. In these models, the heat transfer and mass transfer equations are solved, as in the case of SiC boule growth (see Section 3.1.3). In simulation of CVD, however, a complete set of complicated chemical reactions must be taken into account. Although the CVD process is more easily controlled than the sublimation growth process, one has no way of knowing the real C/Si ratio on the growing surface, and how this varies when the C/Si ratio at the gas inlet is changed. Simulation of SiC CVD gives very important insights into the temperature distribution of wafers, surface kinetics (including actual C/Si ratio, doping efficiency), and guidelines for up-scaling a reactor. Tables 4.2 and 4.3 show the major chemical reactions in the gas phase (homogeneous) and on the surface (heterogeneous), respectively [57]. In the simulation, the temperature dependence of individual chemical reaction constants is, of course, considered. The effects of changes in the precursor supply, the C/Si ratio, the growth temperature, and the pressure on growth rate can be well predicted. Figure 4.10 shows the real C/Si ratio on the SiC surface simulated for SiC CVD growth at 25 kPa [57]. The figure shows the dependence of C/Si ratio on flow rate for a few fixed flow rates. The real C/Si ratio is defined as the ratio of the C- and Si-molar fractions on the growing surface (not at the gas inlet) calculated by using the simulation model. Note that the increase in the C/Si ratio is nonlinear when the flow rate is increased. Furthermore, the real C/Si ratio decreases significantly when the growth temperature is elevated at fixed and flow rates. Figure 4.11 shows the real C/Si ratio as a function of the flow rate simulated for a few fixed C/Si ratios at the gas inlet [57]. The growth temperature and pressure are 1873 K and 25 kPa, respectively. Even if the C/Si ratio at the inlet is fixed at 1.0, the real C/Si ratio on the growing surface exhibits a continuous decrease as the precursor flows are increased to obtain high growth rates. When the C/Si ratio at the inlet is 0.5 (Si rich) or 1.5 (C rich), the real C/Si ratio is considerably shifted toward the Si-rich or C-rich condition, respectively, as the precursor flows increase. These results are important to understand the changes in surface morphology and impurity incorporation when the growth conditions are varied. The dependence of nitrogen and aluminum doping on the growth conditions has also been well described using simulation results [57, 60].

Major homogeneous reactions

Major heterogeneous reactions

4.1.4 Surface Morphology and Step Dynamics

The surfaces of SiC homoepitaxial layers are smooth when the growth process is optimized [20, 22, 23, 48]. Figure 4.12 shows the surface morphology of a 4H-SiC(0001) epitaxial layer observed by (a) Nomarski microscopy and (b) AFM. The surface is mostly featureless, and the density of macroscopic surface defects is typically . The surface roughness defined by the root mean square is 0.14–0.22 nm for a scan area of . Although the surface roughness tends to increase in thick layers, chemical mechanical polishing of substrates, and optimized etching and growth conditions greatly improve the surface morphology, even for very thick layers. When 4H-SiC(0001) with small off-angles (2–4°) is employed, formation of macrosteps is often observed [63–65]. Macrostep formation is not desirable because electric field crowding can take place, especially in gate oxides formed on such a surface. CVD growth under Si-rich conditions [64, 65] or the use of substrates [65, 66] is effective at suppressing macrostep formation. Surface morphological defects are described in Section 4.3.1.

Step bunching in step-flow growth on off-axis substrates is an interesting and important aspect of both crystal growth and surface science. The step structure of 6H- and homoepitaxial layers has been studied using AFM and TEM. In AFM observations, a distinctive difference in surface structures was observed on the (0001)Si and faces. SiC epitaxial growth on the off-axis (0001)Si face yields apparent macrosteps with a terrace width of 200–600 nm and a step height of 2–8 nm. In high-resolution observation, each macrostep is not a single multiple-height step but is instead composed of a number of microsteps as shown in Figure 4.13a [67]. This phenomenon is pronounced in 4H-SiC(0001) growth on substrates with a small off-angle (2–4°) or under C-rich conditions [64, 65]. On the off-axis face, however, the surface is rather flat, and macrosteps are rarely observed, as shown in Figure 4.13b. Although the mechanism of apparent macrostep formation is not very clear, the surface is similar to the so-called hill-and-valley (or faceted) structure often observed in step-flow growth of other materials [68, 69]. The off-axis SiC(0001) surface may spontaneously rearrange to minimize the total surface energy by increasing the area of a low-energy surface. When one looks at the heights of the steps, SiC exhibits unique step structures for each particular polytype. Figure 4.14 shows the histograms of step heights for the surfaces of (a) 4H-SiC and (b) 6H-SiC(0001) epitaxial layers grown on 3.5° or 8° off-axis substrates, respectively [48]. For 4H-SiC, the majority of the surface steps exhibit a two-bilayer height (half unit cell of 4H-SiC), though four-bilayer-height (full unit cell) steps are also observed. In the case of 6H-SiC, most steps possess a three-bilayer height (half unit cell of 6H-SiC). The distribution of step heights is, of course, dependent on the growth condition, but the appearance of half- or full-unit-cell height (c/2 or ) steps is common on SiC epitaxial layers grown by CVD.

Similar observations have been reported for 6H-SiC surfaces grown by the Lely method [70] and MBE [35]. 4H- and 6H-SiC surfaces around a TSD (or micropipe) also exhibit a similar step structure: the step height is along the direction and c/2 along the direction [71, 72]. Thus, the formation of surface steps with a c/2 or height seems to be an inherent aspect of 4H- and 6H-SiC growth. In 15R-SiC growth, the dominant step heights are two, three, and five bilayers, which corresponds to the zigzag stacking structure of 15R-SiC [48]. Heine et al. suggested that the surface energy is different for each SiC bilayer plane because of the peculiar stacking sequence [30]. Different surface energies may lead to different step velocities for each Si-C bilayer, thereby causing “structurally-induced macrostep formation” [73].

4.1.5 Reactor Design for SiC Epitaxy

Because very high temperature (1500–1700 °C) is required in SiC CVD, several unique reactor designs have been proposed. For example, buoyancy-driven convection is significant at these temperatures. A low growth pressure with a high carrier gas flow is an effective way to reduce the thermal convection. Note that radiation dominates as the main mechanism for temperature (heat) loss in this temperature range. Figure 4.15 shows schematic illustrations of several typical reactors employed for SiC CVD. Conventional horizontal [16, 19] and vertical [17] cold-wall CVD reactors are shown in Figure 4.15a,b, respectively. These conventional reactors are simple in configuration but possess some disadvantages when used for SiC CVD. Because of the high growth temperature, the temperature gradient normal to the wafer surface becomes very large , which causes severe warpage of SiC wafers [74]. It is difficult to establish uniform temperature distributions over a large scale at such high temperatures with this reactor configuration. The heating efficiency is very poor, since significant heat is lost by radiation.

These problems have been overcome by introduction of the hot-wall CVD concept by Kordina, Henry, Janzen, and coworkers [18, 23, 75]. In hot-wall CVD reactors, SiC wafers are placed inside a gas-flow channel formed in a susceptor. The susceptor is made of dense graphite coated with polycrystalline SiC or TaC. This susceptor is surrounded by a thermal insulator, such as porous graphite. By adjusting the frequency employed for rf-induction (rf: radio frequency) heating, the susceptor can be efficiently heated with minimal loss in the thermal insulator. The thermal insulation is so good that water cooling of the outer quartz tube is usually not necessary, in spite of the high growth temperature. In hot-wall CVD reactors, SiC wafers are heated from both sides, by radiation from the front side and by conduction (as well as radiation) from the back side. Therefore, the temperature gradient is considerably reduced , and good temperature uniformity can easily be established, which is critical for large-scale production of high-quality epitaxial wafers. The heating efficiency is also very high in hot-wall CVD (the required rf power is much smaller than that in cold-wall CVD). Since the horizontal hot-wall CVD reactor was proposed, several other hot-wall (or warm-wall) configurations have been proposed, as shown in Figure 4.15c [18, 21, 76, 77], (d) [78, 79], and (e) [80]. Among these reactor designs, a horizontal hot-wall CVD reactor with a rotating holder and a planetary warm-wall CVD reactor are commonly used for mass production of SiC epitaxial wafers.

4.2.1 Background Doping

Through process optimization and purification of source materials, the purity of nominally undoped (or unintentionally doped) SiC epitaxial layers is very high. The major source of unintentional dopants is nitrogen, for obvious reasons. Key ways to obtain high purity are to (i) increase the C/Si ratio [81, 82] and (ii) decrease the growth pressure [83, 84]. Figure 4.16 shows the C/Si ratio dependence of the doping density of nominally undoped epitaxial layers grown by hot-wall CVD. In the case of a C/Si ratio of 0.5, the donor density is about , irrespective of the substrate polarity. On the (0001)Si face, the donor density can be drastically reduced by increasing the C/Si ratio; for example, it reaches for growth with a C/Si ratio of 2. Further increase in the C/Si ratio causes a switch of the conduction type from n-type to p-type in the nominally undoped epitaxial layers. Here, the p-type materials are obtained by reduction of nitrogen incorporation and enhancement of aluminum or boron incorporation, being consistent with the site competition concept. On the face, however, the C/Si ratio dependence of the doping density is much smaller, and the lowest donor density is about in this particular case. Higher nitrogen incorporation (and lower aluminum incorporation) on the C face is commonly observed in SiC CVD [81, 85–87] as well as in other growth techniques, including bulk growth. This result can be qualitatively explained by the different bond configurations on SiC(0001) and faces, as described in Section 3.4. Figure 4.17 shows the growth pressure dependence of the doping density of nominally undoped and nitrogen-doped epitaxial layers grown by hot-wall CVD [83]. Nitrogen incorporation is clearly suppressed when the growth pressure is decreased. This is partly attributed to an increase in the actual C/Si ratio on the growing surface at low pressure, mainly because of enhanced desorption of silicon atoms. Desorption of nitrogen atoms during surface migration may also be enhanced at low pressure.

4.2.2 n-Type Doping

In situ n-type doping is easily achieved by the introduction of during CVD growth. Figure 4.18 shows the donor density versus flow rate in hot-wall CVD of 4H-SiC(0001) at 1550 °C. The donor density determined from capacitance–voltage characteristics is proportional to the flow rate over a wide range for CVD on both (0001)Si and faces. When the growth temperature and pressure are fixed, the flow rate and the C/Si ratio are important parameters to achieve wide-range control of nitrogen doping . The pressure dependence of nitrogen doping was investigated in detail [88]. The temperature dependence of nitrogen doping is more complicated. In cold-wall CVD of SiC, the nitrogen incorporation is suppressed on both the (0001) and faces, when the growth temperature is elevated [89]. In hot-wall CVD, however, the nitrogen incorporation increases on (0001) and decreases on as the growth temperature is increased [87]. Growth simulation gives useful insights, but the detailed mechanism is still not fully understood. Although phosphorus doping has been investigated, it seems to be difficult to achieve high doping density [90].

4.2.3 p-Type Doping

The addition of a small amount of trimethylaluminum (TMA: ) is effective for in situ p-type doping in SiC CVD [91]. Figure 4.19 shows the acceptor density versus the TMA flow rate in hot-wall CVD of at 1550 °C. The acceptor density determined from measurements agrees well with the aluminum atom density determined by secondary ion mass spectrometry (SIMS) measurements. The doping efficiency is much higher (by a factor of 10–80) on the Si face than on the C face; again, this can be explained by the occupation site of aluminum atoms and the bond configuration. On the Si face, the acceptor density increases super-linearly with the TMA supply. This super-linearity may be attributed to the increased effective C/Si ratio under high TMA flow conditions, because the supply of TMA causes the growth conditions to become more C-rich as a result of release of species from TMA molecules. The accessible range of aluminum doping is about on SiC(0001). It is noted that heavily-doped p-type layers can be easily grown only on the Si face, while it is difficult to grow heavily-doped p-type layers on the C face. When the TMA supply is high, growth on the C face suffers from two- or three-dimensional nucleation, leading to a rough surface. Details of the dependence of aluminum doping on the growth conditions (temperature, pressure) are found in references [87, 92]. Other p-type dopants include boron (B) and gallium (Ga), which can be doped using gas [93] or trimethylgallium (TMG), respectively [94]. However, boron- or gallium-doped SiC exhibits high resistivity, because of the large ionization energy of these dopants. Abnormal diffusion of boron atoms also causes problems in device processing [95].

Thus, the doping range can be greatly expanded by controlling the C/Si ratio during CVD. Furthermore, control of the C/Si ratio is an effective way to obtain a sharp transition between n-type and p-type epitaxial layers [96]. By synchronizing the change in the C/Si ratio to a dopant switch (from nitrogen to aluminum, for example), abrupt depth profiles of dopant atoms can easily be formed.

4.3.1 Extended Defects

Various kinds of extended defects are present in SiC epitaxial layers. Some defects come from the substrates, while other defects are instead created during the epitaxial process. In this subsection, the classification and nature of extended defects observed in hexagonal SiC epitaxial layers are described.

4.3.1.1 Surface Morphological Defects

Except step bunching, SiC epitaxial layers grown on off-axis substrates exhibit several types of surface defects. Figure 4.20 shows the typical surface defects observed in 4H- and homoepitaxial layers, (a) “carrot” defect [23, 97–100] and shallow pit [20, 48], (b) triangular defect [99–101], and (c) down-fall. Although the exact formation mechanisms of these defects are not fully understood, they are usually created by technical issues such as incomplete removal of polishing damage or non-optimized growth processes. The down-fall is generated by a SiC particle initially formed on the susceptor wall falling down. The density of these defects is mostly influenced by the surface quality of the substrates and the conditions used for the growth process. The density of these defects depends only slightly on the substrate quality.

The carrot (in some case “comet” depending on the defect shape and structure), and triangular defects are usually elongated along the down-step direction of step-flow growth, which is a sign of disturbance of step-flow growth. As schematically shown in Figure 4.21, the defect length along the off-direction is very close to the length of a basal plane in the epilayer when projected onto the surface, taking into account the substrate off-angle :

4.12

where is the epilayer thickness. This observation has a very important implication – these defects are nucleated at the very initial stage of epitaxial growth. If these defects are observed (though they are not desirable), the epilayer thickness can be estimated from the defect length.

Careful TEM studies revealed that the carrot (and comet) defects contain both a basal plane fault and a prismatic plane fault [97–100]. It was also clarified that several types of carrot defects exist, where each has a slightly different arrangement of extended defects [98]. Figure 4.22 shows schematically the structure of a typical carrot defect [98], where a TSD in a substrate is dissociated into two components of and . The component is deflected into a basal plane and forms a Frank partial dislocation with the insertion of a single bilayer. This insertion naturally induces a basal slip, and the Burgers vector of this Frank partial dislocation is expected as . The other component penetrates into an epitaxial layer as a threading dislocation. Because of a stacking sequence mismatch, a prismatic fault is formed on in the case of off-direction toward . Note that only a limited number of TSDs in the substrate become nucleation sites for carrot (or comet) defects. Though the mechanism of the defect formation is not very clear, small pits created during in situ etching prior to CVD may play a key role in the carrot/comet defect formation [102]. It is also reported that a TSD in the substrate is not always necessary for nucleation of carrot (or comet) defects. Instead, generation of a TSD and a carrot (or comet) defect can occur simultaneously [98]. The triangular defects also exhibit a variety of structures. In some triangular defects, the triangular region is indeed 3C-SiC, while in other triangular defects only a 3C-like laminar region with a thickness of several Si-C bilayers is extended in the basal plane [100, 101]. In some cases, no 3C-SiC regions are observed, and a partial dislocation runs along the two sides of the triangular shape. So far, extended defects are not always observed beneath the shallow pits (typical depth: 20–100 nm), such as the one shown in Figure 4.20d. It is of interest that higher densities of carrot (or comet) defects and triangular defects are generated when the epitaxial layers are grown under Si-rich and C-rich conditions, respectively. Under Si-rich conditions, TSDs tend to be deflected into basal planes, forming Frank-type stacking faults. On the other hand, the migration length of adsorbed species decreases [103] and the supersaturation is increased under C-rich conditions [42]. These phenomena may influence the formation of carrot and triangular defects, respectively.

The typical density of these macroscopic defects in SiC homoepitaxial layers is approximately . The generation of shallow pits can be suppressed by minimizing the formation of Si droplets during the in situ etching process [20, 48]. When SiC devices include carrot (or comet) defects or triangular defects, the devices exhibit excessive leakage currents and significantly decreased breakdown voltages, while the impacts of shallow pits are negligibly small [104]. This is not surprising, because the stacking faults involved in carrot, comet, and triangular defects (in both basal and prismatic planes) should behave as leakage paths. Figure 4.23 shows the surface morphology of a 4H-SiC epitaxial layer observed by scanning electron microscopy (SEM) [105]. The image is taken with low acceleration voltage SEM to enhance the resolution. It is found that small depressions, in size, are formed at the locations of TSDs and threading edge dislocations (TEDs) (it is hard to observe these depressions by normal optical microscopy). These depressions must be formed by disturbance of step flow at the dislocations. The depressions are shallow, about 3–20 nm in depth. Note that the shape and depth of these depressions depend greatly on the growth conditions including in situ etching and cooling processes. If deep depressions are formed, geometric effects, such as electric field crowding, significantly affect the device characteristics, as further described in Section 5.2.3.

4.3.1.2 Micropipes

In SiC CVD, most micropipes in a SiC substrate are replicated in the epitaxial layer grown on the substrate. Kamata et al. discovered that micropipes in an off-axis SiC(0001) substrate can be dissociated into several elementary closed-core screw dislocations during CVD growth, leading to “micropipe closing” [106, 107]. The mechanism is the same as that described for micropipe closing during bulk growth (Section 3.3.2). As shown in Figure 4.24, part of a superscrew dislocation, the core of a micropipe, is deflected into the basal plane through interaction with the lateral growth of steps. The deflected screw dislocation tends to change direction again and thread along the direction; the overall outcome is that one elementary screw dislocation has been separated from the superscrew dislocation. By repeating this conversion process several times, a micropipe is completely dissociated into individual elementary screw dislocations. The probability of micropipe closing depends strongl on the C/Si ratio during CVD; Si-rich conditions enhance micropipe closing [107]. By decreasing the C/Si ratio to 0.7, the micropipe closing probability reaches 99% or even higher. On the growing surface, competition exists between spiral growth around a micropipe and step-flow growth as a result of the off-axis substrate. It is believed that micropipe closing takes place when step-flow growth is dominant, even near the core of a micropipe, and the core is directly swept by steps proceeding in the lateral direction [107]. Under Si-rich growth conditions, step-flow growth is enhanced, while spiral growth is promoted under C-rich conditions [108]. Although micropipes are now almost eliminated in the substrates (wafers), micropipe closing during epitaxial growth is an interesting phenomenon from the viewpoint of defect engineering.

4.3.1.3 Dislocations

Now that the micropipe density in SiC wafers has been reduced down to well below (almost eliminated), normal dislocations and epi-induced defects such as carrot defects remain important quality issues in SiC epitaxial layers. Most dislocations in 4H-SiC homoepitaxial layers originate from dislocations in 4H-SiC substrates. Therefore, the dislocation density of a SiC homoepitaxial layer depends greatly on the quality of the substrate, assuming that the epitaxial growth process is sufficiently optimized. Major dislocations in SiC substrates include TSDs, TEDs, and basal plane dislocations (BPDs), as described in Section 3.3.

Figure 4.25 illustrates the dislocation replication and conversion typically observed in 4H-SiC epitaxial layers grown on off-axis by CVD [25, 77]. Almost all the TSDs in a substrate are replicated in an epilayer, but a small portion (typically ) of TSDs are converted to Frank-type partial dislocations [109]. A TSD in the substrate can act as a nucleation site for a carrot defect, as described above.

Behavior of BPDs during epitaxial growth is much more complicated. A BPD is a detrimental defect for SiC bipolar devices because it can be the source of a Shockley-type stacking fault upon carrier injection, and such a stacking fault causes local reduction of carrier lifetimes (increase of on-resistance) and increase in leakage current [110–112]. This is called “bipolar degradation”, and is treated in a separate section (Section 5.2.2). Here, two important phenomena related to BPDs are described.

Conversion of BPD to TED

BPDs and TEDs possess the same Burgers vector ; the naming is different depending on the dislocation direction (perpendicular or parallel to the -axis). When a BPD is replicated in an epitaxial layer, it extends in a basal plane, which is inclined by several degrees from the crystal surface. Since the elastic energy of a dislocation is naturally proportional to the dislocation length [113], BPD replication in an epitaxial layer grown on off-axis results in a large increase in elastic energy of the dislocation. This energy is greatly decreased by conversion of a BPD to a TED, by which process the dislocation length is considerably shortened by a factor of (where is the off-angle). This dislocation conversion can be explained by a so-called “image force” applied to a BPD [113].

In reality, most BPDs in the substrate are converted to TEDs within a few micrometers of an initial epitaxial layer without any special treatment [114–116]. Some BPDs are, however, replicated in a SiC epitaxial layer. It has been discovered that all these BPDs propagating in basal planes of an epitaxial layer are of a screw character [25, 117, 118]. It is known that a perfect BPD in SiC is dissociated into two partial dislocations, and a single Shockley-type stacking fault is created between the two partials [111, 119, 120]. This is expressed by using the Burgers vector as follows (also see Figure 4.26):

4.13

The schematic illustration of the BPD split is shown in Figure 4.27. The created stacking fault has a structure of (31) in Zhdanov's notation. This dissociation of a BPD takes place because of the energy gain. In a simple model, the energy balance per unit length is expressed by:

4.14

where is the stacking fault energy per unit area and the stacking fault area. and are the proportion constants associated with the shear modulus and defect geometry. Because the stacking fault energy in SiC is low, the relationship shown in Equation 4.14 is satisfied. The width of the Shockley-type stacking faults is typically 30–70 nm [119], and depends on the dislocation direction inside a basal plane as well as the doping density. The Shockley-type stacking fault width is usually wider for heavily-nitrogen-doped SiC; this arises from a gain in electrostatic energy caused by capture of free electrons at the localized level of the stacking faults. Because the two partial dislocations and the Shockley-type stacking fault between them cannot be directly deflected to the -axis, it is supposed that the two partial dislocations must merge into a perfect BPD before conversion to a TED. This has recently been confirmed by three-dimensional synchrotron X-ray topography analyses [121] and a careful TEM study [122].

Conversion from BPDs to TEDs is enhanced by several techniques, such as molten KOH etching [123–125] or etching [126] prior to epitaxial growth or interruption during growth [127]. These techniques form depressions at the location where BPDs intersect with the surface. Inside the depressions, the advance of surface steps is three-dimensional and two partial dislocations are forced to merge into a perfect BPD [125]. The use of a substrate with a lower off-angle is naturally effective to enhance the conversion, owing to the increased image force [128]. High-temperature annealing in Ar induces spontaneous conversion from a BPD to a TED near the surface (without growth) [129], which is consistent with the energy balance according to Equation 4.14. Furthermore, increasing the growth rate also effectively enhances the BPD-TED conversion [46]. By combining these techniques, the conversion ratio has been increased to 99.8% or even higher. Thus, if the BPD density in a substrate is , the density of BPDs replicated in an epitaxial layer is about .

Formation of Interface Dislocation

BPDs easily glide under stress, because the critical resolved shear stress is relatively low in SiC, especially at high temperature, as described in Section 3.3. The glide motion of BPDs during epitaxial growth has in fact been observed by X-ray topography [130–133]. Figure 4.28a illustrates schematically the glide of a BPD during epitaxial growth of SiC [130]. A BPD replicated in an epitaxial layer is deflected to the direction normal to the step flow and the BPD often lies near the interface between a lightly-doped epitaxial layer and a heavily-doped substrate [130]. Thus, a BPD lying at the epitaxial layer/substrate interface is called an “interface dislocation”. Note that this is not a pure misfit dislocation resulting from lattice relaxation caused by doping-induced misfit strain [134], because such interface dislocations are not observed, even for more than -thick -type SiC epitaxial layers, when they are grown under appropriate conditions. A large temperature inhomogeneity can induce significant thermal stress, and when this stress is added to the misfit stress (i.e., acts in the same direction) pre-existing BPDs glide for lattice relaxation [133]. The direction of glide motion depends on the Burgers vector of the BPD and the stress direction. The situation is more complicated when a BPD is converted to a TED in the initial stage of epitaxial growth. The BPD component existing near the epitaxial layer/substrate interface glides, and a number of half-loop dislocations are created along the glide direction, as shown in Figure 4.28b [130, 135]. As a result, an array of half-loop dislocations is formed along when the off-direction is . These dislocations can be identified as an array of TED pairs on the surface, as shown in Figure 4.28.

4.3.1.4 In-Grown Stacking Faults

Nucleation of stacking faults (SFs) takes place during epitaxial growth, even if the substrate is free of stacking faults. In an early study, the existence of microscopic stacking faults in “high-quality” SiC epitaxial layers has been suggested, based on the observation of various abnormal photoluminescence peaks [136]. So far, several types of in-grown SFs have been identified by cross-sectional TEM. A majority of these SFs are caused by slips in basal planes (Shockley type). Note that most in-grown SFs are invisible in optical microscopy but photoluminescence (PL) mapping/imaging is a powerful method to detect these defects [137–140].

Figure 4.29 shows the micro-PL spectra acquired from several areas with and without in-grown SFs in a thick, high-purity 4H-SiC(0001) epitaxial layer at room temperature [141]. In the spectrum of the 4H-SiC matrix without SFs only one peak is observed, located at 390 nm and assigned to free excitons. In the spectra from the SF regions, however, distinct PL peaks at 455, 480, and 500 nm were observed, in addition to the weak band edge (free exciton) peak at 390 nm. Thus, PL-intensity mapping at a wavelength specific to each SF gives detailed information (location, shape, and density) about in-grown SFs. Figure 4.30 shows examples of PL-intensity maps taken at (a) 455, (b) 480, and (c) 500 nm from the same location [141]. The optical microscope image is also shown in Figure 4.30d. As shown in Figure 4.30, the shape of those SFs that show PL peaks at 455 nm is a right-angled triangle with its apex pointed toward the upstream side of the step flow. Conversely, the shape of the SF that shows 480 nm emission is an isosceles triangle, elongated along the off-direction. The lengths of all these SFs along the off-direction again agree with the projected length of a basal plane in the epitaxial layer, as was the case for carrot defects. This result implies that these SFs also nucleated in the initial stage of epitaxial growth. Although misalignment of atoms during step-flow growth has been suggested as the nucleation mechanism for SFs [142, 143], the detailed mechanism is not very clear at present. Figure 4.31 shows high-resolution TEM images taken from the major in-grown SFs that exhibit PL peaks at (a) 455, (b) 480, and (c) 500 nm [141]. The stacking sequences have been determined as (44), (53), and (62) types, respectively, in Zhdanov's notation. One-to-one correlation has been established between the PL peak position and the stacking sequence.

These in-grown SFs adversely affect device characteristics, for example, increase of leakage current [144]. Optimization of in situ etching and using lower growth rates at the start of epitaxial growth effectively reduce the density of these SFs. The total density of SFs is typically in the range for epilayers grown at a standard growth rate ; the SF density usually increases when the growth rate is increased [143]. Several kinds of Frank-type stacking faults (stacking sequences: (50), (42), and (41) in Zhdanov's notation) have also been identified [145]. Each Frank-type stacking fault also exhibits a luminescence peak at a particular wavelength. Elimination of Shockley- and Frank-type SFs remains an important issue in fast epitaxy of SiC.

4.3.2 Deep Levels

Another important type of defect in epitaxial layers is point defects, which create deep level(s) in a bandgap [146]. Deep levels are usually characterized by deep level transient spectroscopy (DLTS) measurements [147, 148] on SiC Schottky structures. The density of deep levels in lightly-doped as-grown 4H-SiC(0001) epitaxial layers is typically , depending on the growth conditions. This value is fairly low, for a compound semiconductor and is acceptable for fabrication of unipolar devices. In fabrication of power metal-oxide-semiconductor field effect transistors (MOSFETs), for example, deep levels created by ion implantation are more important. For bipolar device applications, however, the above-mentioned density is not low enough, especially when a long carrier lifetime is required. Details are described in Section 5.3.

Figure 4.32 shows the typical DLTS spectra obtained from (a) n-type and (b) p-type 4H-SiC epitaxial layers with a doping density of about . Figure 4.33 illustrates the energy levels of major deep levels observed in as-grown n-type and p-type 4H-SiC epitaxial layers [149–154]. Among these levels, the [149] and EH6/7 [150] centers are the dominant defects (commonly observed at densities of in all as-grown epitaxial layers by CVD. Both centers are extremely stable against high-temperature annealing. In the lower half of the bandgap, the HK2 , HK3 , and HK4 [153] centers are dominant deep levels. The densities of HK2, HK3, and HK4 centers are typically in the range . Because the HK2, HK3, and HK4 centers almost disappear upon annealing at 1450–1550 °C [153], the and EH6/7 centers are more important. Indeed, the center has been identified as the dominant lifetime killer, at least for n-type 4H-SiC [155, 156]. Thus, it is very important to reduce and control the density of the center to optimize the carrier lifetime in SiC bipolar devices. Note that the and EH6/7 centers are also dominant in ion-implanted regions and dry-etched regions of 4H-SiC [149, 157–159]. As well as these levels, a few impurity-related levels are often observed in as-grown SiC epitaxial layers. For example, boron is a typical impurity that can be unintentionally doped from reactor parts (such as graphite susceptors). Boron (B) contamination creates the boron acceptor level [160] and the boron-related “D center” [160]. Another common impurity is titanium, which also comes from graphite parts as well as from pumping oil. Titanium (Ti) creates very shallow electron traps in 4H-SiC [161]. The typical impurity density in CVD-grown 4H-SiC epitaxial layers is about for boron and for titanium.

The densities of and EH6/7 centers are strongly dependent on the C/Si ratio and growth temperature; however, the growth rate only has a minor effect on defect generation, even if the growth rate is changed from 5 to [83, 162–164]. Figure 4.34 shows the C/Si ratio dependence of the densities of and EH6/7 centers in as-grown n-type 4H-SiC(0001) and epitaxial layers [165]. Both the and EH6/7 densities can be considerably reduced by increasing the C/Si ratio during CVD on (0001). In recent years, the origin of these centers has been identified as a carbon monovacancy with different charge states [166, 167]. Therefore, it is reasonable that the density is high under Si-rich conditions and low under C-rich conditions. It is difficult to obtain a low density in as-grown epilayers on the face. The growth-temperature dependence of the and EH6/7 densities is shown in Figure 4.35. The density of both defects exhibits significant increase with increasing growth temperature. This can be attributed to a higher equilibrium density of the carbon vacancy at higher temperatures, as described in detail in Section 5.3.1. In general, a higher growth temperature is preferable to obtain good surface morphology with a reduced density of extended defects (such as carrot-defects, in-grown SFs). However, high-temperature growth results in a high density of the center, leading to a short carrier lifetime. Therefore, there is a trade-off between the low density of extended defects and a long carrier lifetime in as-grown epitaxial layers. After optimization of growth conditions, the typical density of the center is about in as-grown n-type 4H-SiC(0001) epitaxial layers, which gives a high-injection carrier lifetime of about [168]. Enhancement of carrier lifetimes by defect reduction is described in Section 5.3.

4.5.1 SiC Homoepitaxy on Nearly On-Axis

A major driving force for developing SiC homoepitaxy on nearly on-axis substrates is elimination of BPDs in the epitaxial layers. The wafer cost may be reduced by using nearly on-axis wafers when the SiC boules are grown on on-axis seeds. It is, however, not very easy to ensure stable step-flow growth if the substrate's off-angle becomes smaller than 2°, as shown in Figure 4.7. This is especially true in fast epitaxy on nearly on-axis substrates. The disturbance or instability of step-flow growth can result in nucleation of 3C-SiC and/or stacking fault generation.

In an early study by Powell et al. [32], homoepitaxy of 6H-SiC on 0.2° off-axis 6H-SiC(0001) was demonstrated by removal of defective sites by appropriate in situ etching. This process was refined, and relatively large area homoepitaxy of 6H-SiC on nearly on-axis (0001) substrates was achieved under Si-rich conditions [189]. CVD growth under Si-rich (low C/Si ratio) conditions is a common approach in homoepitaxial growth of SiC on substrates with low off-angles. This is because Si-rich conditions increase the surface migration length of adsorbed species, and thus result in low supersaturation on the growing surface [103]. The major drawback of CVD under Si-rich conditions is greater nitrogen incorporation in SiC epitaxial layers. Neudeck et al. developed homoepitaxy of dislocation-free 4H- and 6H-SiC(0001) by using small mesa structures [190, 191].

More recently, Kojima et al. discovered that 4H-SiC without 3C-SiC inclusions can be homoepitaxially grown on nearly on-axis (about 0.3° off-axis) [66, 192]. Although the reasons for this success are unclear at present, the difference in the surface energy is suggested (this is also the reason that bulk 4H-SiC can be easily grown on a seed by sublimation) [193]. Homoepitaxy on nearly on-axis 4H-SiC(0001) has been significantly improved by adopting in-situ etching with addition prior to CVD growth [194]. Figure 4.37 shows optical microscopy images of 4H-SiC epitaxial layers grown on (a) and (b) (0001) substrates with various off-angles from 0.24° to 0.79° [194]. Here, the growth temperature and growth rate are 1600 °C and about , respectively. Homoepitaxy of 4H-SiC with good morphology is attained on 0.3° off-axis and 0.79° off-axis (0001). The use of chlorine-based chemistry for 4H-SiC homoepitaxy on nearly on-axis (0001) substrates is also very effective, and homoepitaxy at high growth rates, over , was realized [195–197]. Chlorine may preferentially etch defective islands and/or 3C-SiC inclusions during growth.

Achieving wide-range doping control capability and characterizing defects in more detail remain issues. Another concern is the role of TSDs. Spiral growth around TSDs naturally enables polytype replication in SiC epitaxial layers because the stacking sequence appears perfectly along the step edges created by the spiral. In the future, however, the density of TSDs will be greatly reduced by improvements in bulk growth technology. Therefore, homoepitaxy on nearly on-axis will become more difficult when TSDs in SiC wafers are almost eliminated.

4.5.2 SiC Homoepitaxy on Non-basal Planes

The typical non-basal planes used for epitaxy include , and (equivalent to in 6H-SiC) faces. Note that the face is crystallographically equivalent to the (110) face in a cubic crystal, and the face is semi-equivalent to the (001) face [198]. In an early study, low-temperature (1200–1350 °C) homoepitaxy by CVD was demonstrated on [199] and [200]. The stacking sequence of 6H-SiC (ABCACB) appears directly on the surfaces of these faces, and no intentional off-angles are required to realize homoepitaxy of 6H- or 4H-SiC on these non-basal planes. As a consequence, the occupation site of adsorbed species is uniquely fixed by the bonds at any site on the surface, enabling homoepitaxy at low temperature. However, the range of optimum values for other conditions (such as the C/Si ratio) become narrow with decreasing growth temperature and macroscopic defects are easily generated. The residual nitrogen density also increases in SiC epitaxial layers grown at low temperature [89]. Thus, low-temperature homoepitaxy is not attractive for power device applications.

The growth rates on the non-basal planes are almost the same as that on off-axis (0001) under the same conditions, indicating that the growth is controlled by mass transport [201]. The , and epitaxial layers exhibit very good morphology and a small surface roughness of 0.12–0.22 nm in a area, without any of the triangular defects and “carrot” defects that occasionally appear on off-axis SiC(0001) epitaxial layers [201–203]. No signs of “step-flow” growth (such as step bunching) have been observed for these epilayers, suggesting layer-by-layer growth.

The doping efficiencies of nitrogen and aluminum in CVD growth on these non-basal planes are in between those on off-axis (0001) and faces. The typical background doping density is on off-axis (0001), on and , and on off-axis . When nitrogen is introduced during CVD, the epitaxial layers grown on , and always show higher donor densities than those of the layers grown on off-axis (0001). Figure 4.38 shows the C/Si ratio dependence of nitrogen density, determined by SIMS, for 4H-SiC epitaxial layers grown by hot-wall CVD on , and off-axis (0001) and faces. The nitrogen incorporation is significantly reduced by increasing the C/Si ratio on , and off-axis (0001), as a result of the site competition effect. The C/Si ratio dependence is the largest on (0001), while and faces show smaller changes in nitrogen incorporation. On the face, however, a higher C/Si ratio does not always lead to lower nitrogen density. In aluminum doping, the doping efficiency on these non-basal planes is lower than that on (0001) and higher than that on . Interestingly, the densities of the major deep levels, and EH6/7 centers, in 4H-SiC epitaxial layers on , and are higher than those on (0001) and lower than those on [165].

Major extended defects observed in and epitaxial layers are BPDs replicated from the substrates. Stacking faults are also often observed in these epitaxial layers [204]. In CVD growth of 4H-SiC , the situation is more complicated. Threading screw and edge dislocations tend to deflect into basal planes under Si-rich conditions, whereas they propagate along nearly under C-rich conditions [205].

4.5.3 Embedded Homoepitaxy of SiC

Embedded homoepitaxial growth of SiC is useful for fabricating unique structures without needing ion implantation. Examples of such structures include the channel regions of vertical static induction transistors (or junction field effect transistors) [206, 207] and of lateral metal-semiconductor field effect transistors [208]. Reports of homoepitaxial growth of SiC on trench structures have been published [209–211]. When a trench is formed on off-axis SiC(0001), homoepitaxial growth takes place from the trench bottom, as well as from the trench sidewalls. In general, the growth rate and impurity incorporation for the layer grown from the bottom are different from those for the layers grown from the sidewalls. Furthermore, the crystal planes of trench sidewalls are important, because the crystalline quality and impurity incorporation also depend on these planes. When the off-axis is introduced along the direction, and are typical planes of trench sidewalls (if the sidewall angle is nearly 90°). Another set of trench sidewalls can be and , but in this case, the actual sidewall planes are tilted from the original and by the off-angle (typically 4°). It is reported that SiC pn junctions formed by embedded epitaxy exhibit lower leakage current when the sidewalls are rather than [212]. Selective embedded epitaxy by using carbon [213] or TaC [214] as masking materials has also been reported.

Figure 4.39 shows a cross-sectional TEM image of SiC trenches filled by embedded epitaxy [211]. When the CVD growth was carried out with a standard C/Si ratio at a growth temperature of 1550 °C, the epitaxial layer near the top of a trench became thicker, leading to formation of a void inside the trench (not shown). In contrast, a low C/Si ratio and a high growth temperature of 1650 °C were employed in Figure 4.39, where complete trench filling without voids is achieved. In CVD growth under Si-rich conditions at high temperature, surface migration of adsorbed atoms is enhanced. Thus, a trench is filled from the bottom region, because of the greater surface migration, leading to complete filling.

4.7.1 Heteroepitaxial Growth of 3C-SiC on Si

Heteroepitaxial growth of 3C-SiC on Si must overcome large mismatches of the crystal lattice (20%) and thermal expansion coefficient (8%). The growth temperature is restricted to below 1350 °C because of the melting point of Si (1415 °C). Substantial slip lines can be introduced into the Si substrate during growth close to the melting point. Nevertheless, growth of monocrystalline 3C-SiC layers is achieved by a two-step growth program [225–233]. Figure 4.40 shows the typical growth program employed for CVD of 3C-SiC on Si. In the first step, the surface of Si is cleaned by in situ HCl/H₂ etching and a “carbonized buffer layer” is formed by introduction of hydrocarbon [225]. This step is immediately followed by the second step, which is the main growth of 3C-SiC. The carbonized buffer layer is actually very thin monocrystalline 3C-SiC [227, 230]. This layer must be free of pinholes and grain boundaries. If some pinholes and grain boundaries exist, Si atoms are supplied from the substrate underneath during subsequent CVD growth [234], leading to formation of voids below the 3C-SiC layer as well as to abnormal growth on the surface. To seal off the Si supply from the substrate, the nucleation density must be very high and the grown buffer layer should be of high crystal quality. To satisfy these requirements, hydrocarbon is introduced from relatively low temperatures, and the temperature ramp rate must be sufficiently high. By using this two-step growth, 3C-SiC can be heteroepitaxially grown on Si in a reproducible manner [225, 226]. When a Si(001) substrate is employed, a 3C-SiC(001) layer is obtained, and 3C-SiC(111) is grown on Si(111). The typical growth temperature and growth rates are 1350 °C and , respectively.

Inside the buffer layer and the initial 3C-SiC layer grown on it, a high density of dislocations and stacking faults exist. These extended defects meet each other and can be considerably reduced after the first several-100-nm-thick layer [230, 235, 236]. As a result, monocrystalline 3C-SiC with much improved quality is grown on Si. The density of dislocations in subsequent 3C-SiC layers is . Various types of stacking faults and microtwins are also observed in the 3C-SiC layers. Although these stacking faults can be reduced by employing “undulant Si substrates” [237, 238], as described in Chapter 3, the stacking fault density is still far from a satisfactory level. Another issue is severe wafer warpage because of the significant stress caused by the lattice and thermal expansion mismatch.

Another type of extended defect in 3C-SiC grown on Si is anti-phase domains (APDs). These are common defects that appear in many compound semiconductors grown on element semiconductors, such as GaAs on Si and GaAs on Ge [27]. Figure 4.41 shows a schematic illustration of the bond configuration near the 3C-SiC(001)/Si(001) interface, where the lattice mismatch has been neglected. On the Si(001) surface, atomic steps naturally exist after in situ cleaning prior to CVD growth, and the height of some steps can be that of a monoatomic layer. When SiC is grown on this face, the monolayers of carbon can misalign with each other because of the atomic steps. At the domain boundaries (called anti-phase boundaries (APBs)), a number of Si-Si or C-C bonds are formed. Remarkable reduction of APDs in 3C-SiC layers has been attained by the use of a Si(001) substrate with a few degrees off-axis toward the [110] direction [239]. Figure 4.42 shows Nomarski microscope images of 3C-SiC layers grown on (a) on-axis Si(001) and (b) 2° off-axis Si(001). The cross-hatched morphology is changed to a stripe-like morphology by the introduction of an off-axis, and structural characterization by TEM and molten KOH etching revealed that APDs are mostly eliminated on the off-axis substrate. More recently, it has been reported that APDs can be almost eliminated by low-pressure CVD [240, 241].

In spite of these efforts, the density of extended defects in 3C-SiC grown on Si is still high. 3C-SiC pn junctions and Schottky barrier diodes fabricated on these heteroepitaxial layers exhibit large leakage currents and low breakdown voltages. The relatively high level of background nitrogen doping in 3C-SiC (typically in the mid ) because of the relatively low growth temperature is another issue that must be solved. Considerable efforts are being made, aiming at drastic improvement of the crystal quality. A thin 3C-SiC layer grown on Si is an attractive material for MEMS (microelectromechanical system) applications [242, 243].

4.7.2 Heteroepitaxial Growth of 3C-SiC on Hexagonal SiC

Hexagonal is an attractive substrate for 3C-SiC growth, because it has a very small lattice mismatch. There is a definite difference in the lattice constants (or Si-C bond lengths) between 3C-SiC and hexagonal SiC (see Chapter 2), but the mismatch is much smaller than that for 3C-SiC/Si. From the crystallographic point of view, 3C-SiC(111) can be coherently grown on 4H- or 6H-SiC(0001). Another advantage of using SiC substrates is that high growth temperatures can be employed (without the restriction of the Si melting point), which makes it easier to obtain high-quality, high-purity 3C-SiC. Growth of 3C-SiC on 4H- or 6H-SiC(0001) has been performed using almost the same reactors and conditions as those employed for homoepitaxy of 4H- or 6H-SiC. Typical growth temperatures and growth rates are 1500–1600 °C and , respectively. Of course, the 4H- and 6H-SiC(0001) substrates must be on-axis in this case, to suppress step-flow growth that would result in homoepitaxy of 4H- or 6H-SiC. Furthermore, hexagonal SiC(0001) is the substrate chosen, because three-dimensional growth often takes place on , because of the much higher nucleation probability on this face [15, 40].

In addition to replication of threading dislocations from the hexagonal SiC substrates, new extended defects are generated during the heteroepitaxial growth. The most common type of defect is stacking faults. In 3C-SiC, is the main plane for stacking fault generation. Because of the low stacking fault energy of SiC, 3C-SiC always suffers from generation of a high density of stacking faults, but the exact mechanism of stacking fault generation is not clear at present. These stacking faults are the main cause of large leakage currents in electronic devices fabricated on 3C-SiC(111) grown on hexagonal SiC(0001) (although leakage currents are much smaller than those in devices fabricated on 3C-SiC/Si).

Another type of extended defect observed in 3C-SiC grown on hexagonal SiC is double positioning domains (DPDs). As briefly explained in Figure 4.2a, 3C-SiC grown on on-axis 6H-SiC(0001) can take two possible stacking orders, ABCABCand ACBACB [244, 245], because the stacking order of 6H-SiC is ABCACB. The situation is similar when on-axis 4H-SiC(0001) is employed as a substrate. The domain with ABC stacking is rotated by 180° with respect to the domain with ACB stacking, and the domain boundary is called a double positioning boundary (DPB). When devices are fabricated on SiC that contains DPBs, unacceptably large leakage currents are observed. It has been revealed that the ABC and ACB stacking domains follow the stacking sequence of the top surface in the substrate; this phenomenon has been discussed, considering minimization of stacking energy in SiC polytypes [245]. The area of (0001) terraces with an ABC stacking must be identical to that with an ACB stacking for 6H-SiC (stacking: ABCACB), and the situation is similar for 4H-SiC. This area ratio can be 3 : 2 when 15R-SiC(0001) is employed as a substrate. In fact, remarkable reduction of DPBs has been reported in thick 3C-SiC growth on 15R-SiC(0001) [246]. However, so far, DPBs have not been completely eliminated. Ideally, DPBs can be eliminated if 3C-SiC is grown on a perfect SiC(0001) face, which is free of any atomic steps. Although this has been demonstrated on a small scale using small mesas [190, 191], it is not very realistic to prepare perfectly step-free surfaces across the entire area of 150-mm-diameter SiC(0001) wafers.

Thus, significant improvement in quality and doping control is required before 3C-SiC is suitable for electronic applications. In the future, an attractive approach may be to grow 3C-SiC on high-quality free-standing 3C-SiC substrates, produced by fast epitaxial growth of 3C-SiC on Si wafers and subsequent etching of Si.