In Cortex-M, the control block region related to MPU configuration is located in the system control block, starting at address 0xE000ED90. Five registers are used to access the MPU:

• The MPU Type Register (offset = 0x00) contains information about the availability of the MPU system and the number of regions supported. This register is also available on systems without an MPU to indicate that the functionality is not supported.
• The MPU Control Register (offset is 0x04) is used to activate the MPU system, and to enable the default background mapping for all the regions that are not explicitly mapped in the MPU. If the background mapping is not enabled, accessing non-mapped regions is not allowed.
• The MPU Region Number Register (RNR, offset is 0x08) is used to select the region to configure.

• The MPU Region Base Address Register (RBAR, offset is 0x0C) can be accessed to change the base address of the selected region.
• The MPU Region Attribute and Size Register (RASR, offset is 0x10) defines the permissions, attributes, and size of the selected region.