Chapter 5

Frontiers of ΣΔ Modulators: Trends and Challenges

Since the introduction of the modulation technique, there has been a pleiad of ICs published; implemented using many diverse technology processes, architectural, and circuit techniques, which have targeted a huge number of applications that span from sensors and instrumentation to ultra-low power, biomedical applications, and broadband communications [1–3].

An in-depth understanding of the performance of state-of-the-art Ms, their trends, challenges, and circuits and systems solutions, constitutes a powerful and empirical tool for designers to select the optimum M architecture, circuit implementation, technology process, etc, for a given set of specifications and/or a particular application. With this objective in mind and following the practical approach considered throughout this book, this chapter gives an overview of reported cutting-edge M ICs fabricated in CMOS technologies. The main purpose of this overview is to make an exhaustive analysis of the evolution trends, design challenges, and reported solutions in order to extract practical conclusions and guidelines which may be useful for designers in their own projects.

The study described here is inspired by previous surveys on state-of-the-art performance of ADCs [3–10]. In the majority of cases, these surveys cover different kinds of ADCs, not only Ms. Among others, the surveys published by Walden [4], Murmann [5], and more recently Jonsson [8, 9] and Manganaro [10], are particularly exhaustive and accurate. Compared to these works, the study described in this book focuses on M ICs; emphasizing on the different architectures and circuits used in many different applications. Moreover, in addition to analyzing statistics and comparing data collected from publications and extracted from standard performance metrics, the study presented in this chapter gives an overview of cutting-edge M circuits and systems techniques which are at the frontier of state-of-the-art performance, highlighting the incoming trends and challenges as well as the proposed efficient solutions.

The data used for this study was mainly collected from the IEEE Journal of Solid-State Circuits as well as the major conferences sponsored by the IEEE Solid-State Circuits Society (SSCS), namely International Solid-State Circuits Conference (ISSCC), European Solid-State Circuits Conference (ESSCIRC), Custom Integrated Circuits Conference (CICC), Symposium on VLSI Circuits (VLSI), Asian Solid-State Circuits Conference (ASSCC), and Radio Frequency Integrated Circuits Symposium (RFIC). In addition to these SSCS publications, some other remarkable M ICs published in the IEEE Transactions on Circuits and Systems (parts I and II) and the IEEE International Symposium on Circuits and Systems (ISCAS) have also been collected in the survey.Overall, more than 300 M ICs have been analyzed in detail and considered in this review. Although the works under study include papers published since 1990 to June 2012, data was more exhaustively collected in the last 10 years.

All data collected and analyzed in the survey is compiled in an Excel spreadsheet that is available online at http://www.imse-cnm.csic.es/∼jrosa/CMOS-SDMs-Survey-IMSE-JMdelaRosa.xlsx. The database in this spreadsheet file is periodically kept up to date every six months and aims to be a complement to the popular and highly cited Murmann's ADC survey data collection [11].

Following this introduction, the chapter is organized as follows. Section 5.1 gives an overview of the state-of-the-art Ms, comparing their performance with Nyquist-rate ADCs. The diverse families of M architectures and circuit techniques are exhaustively analyzed and compared in Section 5.2 in order to extract practical and empirical design guidelines. Section 5.3 reviews some of the most significant cutting-edge M techniques, analyzing the design trends and challenges in the frontiers of Ms. Finally, the chapter is concluded with a classified description of state-of-the-art references.

5.1 Overview of the State of the Art on Ms

Tables 5.13 sum up the performance of the state-of-the-art M ICs considered in this survey. For the sake of clarity and simplicity, the ICs included in the study have been classified according to their architecture/circuit characteristics into the following tables:

• SC-Ms: single-loop single-bit LP-Ms (Table 5.1), single-loop multibit LP-Ms (Table 5.2), cascade single-bit LP-Ms (Table 5.3), cascade multibit LP-Ms (Table 5.4), and BP-Ms (Table 5.5).
• CT-Ms: single-loop single-bit LP-Ms (Table 5.6), single-loop multibit LP-Ms (Table 5.7), cascade LP-Ms (Table 5.8), and BP-Ms (Table 5.9).
• Ms with time-coded quantization (Table 5.10).
• Hybrid Ms: CT/DT Ms, active/passive Ms, digital-based Ms, and M/Nyquist-rate ADCs (Table 5.11).
• Reconfigurable Ms implemented using SC (Table 5.12) and CT circuits (Table 5.13).

Table 5.1 State-of-the-art SC single-loop single-bit LP-Ms

The M ICs are sorted by FOM. Engineering notation is used for and power consumption.

Table 5.2 State-of-the-art SC single-loop multibit LP-Ms

The M ICs are sorted by FOM. Architecture is expressed in terms of the modulator order and the number of bits/levels of the embedded quantizer. For instance, 2nd-ord(4b) represents a second-order loop filter with 4-bit quantizer and 5th-ord(33L) means a fifth-order architecture with 33-level quantizer.

Table 5.3 State-of-the-art SC cascade single-bit LP-Ms

The cascade topology is expressed in terms of the stage orders. For instance, notation 2-2 is used for representing a fourth-order cascade M made up of two second-order stages.

Table 5.4 State-of-the-art SC cascade multibit LP-Ms

The number of bits per levels of the quantizer is given in parentheses. This way, notation 2-1(5L) is used for denoting a cascade 2-1 M topology with 5-level quantizer in the second stage. If no parentheses are shown, single-bit quantization is assumed in a given modulator stage.

Table 5.5 State-of-the-art SC BP-Ms

Table 5.6 State-of-the-art CT single-loop single-bit LP-Ms

Table 5.7 State-of-the-art CT single-loop multibit LP-Ms

Table 5.8 State-of-the-art CT cascade LP-Ms

I/Q is used for denoting a quadrature topology.

Table 5.9 State-of-the-art CT BP-Ms

Table 5.10 State-of-the-art Ms with time-coded quantization

TDC stands for time-to-digital converter; TEQ stands for time-encoding quantizer.

Table 5.11 State-of-the-art hybrid Ms

Table 5.12 State-of-the-art SC adaptive/reconfigurable Ms

For the sake of clarity, and considering that reconfigurable Ms feature different performance depending on their operating mode, the ICs in this table have been sorted by the year of publication.

Table 5.13 State-of-the-art CT adaptive/reconfigurable Ms

ICs are sorted by date of publication.

In all cases, the main features of each reported IC are summarized in terms of the following performance metrics: DR (measured in bits), , OSR, technology process, supply voltage, and power consumption.¹ In the case of BP-Ms (Tables 5.5 and 5.9), the notch frequency is also given. A schematic description of each M topology is sketched in the tables, highlighting the loop-filter order, the number of stages (in cascade Ms), the number of bits of the embedded quantizer, the type of quantization technique (in time-based quantizers), the operation mode and standard covered (in the case of reconfigurable Ms), etc. A more complete description of the modulators—not shown in the tables of this chapter for the sake of simplicity–can be found in the spreadsheet available on the Web.

5.1.1 DR-versus- Conversion Region

Figure 5.1 represents DR versus for the different families of Ms.² It can be noted in Figure 5.1 that a wide DR-versus- conversion region is covered, ranging over seven decades in frequency and 16 bit in the DR axis. The highest DR is 21 bit, which was reported in 1994 by Kerth et al. who designed a fourth-order single-loop single-bit SC-M in a 3-µm CMOS technology which digitized 400-Hz signals for seismic applications [48]. On the other hand, the highest value of was reported by Shibata et al. at ISSCC in February 2012. This chip consisted of a DC-to-1-GHz tunable notch-frequency sixth-order multibit LP/BP CT-M, implemented in a 65-nm CMOS technology, achieving 12-bit DR within a 150 MHz signal bandwidth [239].

Figure 5.2 compares the conversion region achieved by the state-of-the-art Ms with the one achieved by Nyquist-rate CMOS ADCs. The data in this figure was collected from Murmann's ADC survey [11], as well as from that used in Figure 5.1. It can be observed from Figure 5.2 that ADCs dominate the state-of-the-art DR-versus- front in a wide frequency range: from hundreds of hertz to hundreds of megahertz. Beyond this range, Nyquist-rate are more competitive, reporting state-of-the-art performance in high-frequency applications with signal bandwidths ranging from hundreds of megahertz to dozens of gigahertz.

Analyzing the evolution over time of the handled by Ms, it can be observed that the tendency is toward extending their range of application, particularly increasing the digitized signal bandwidth, although these designs—placed in the so-called technology front—are sometimes less power efficient, as will be discussed later. Figure 5.3 represents the reported by Ms over time of publication for the years 1990–2012. It can be observed how Ms have evolved from low-frequency (high-resolution) to high-frequency (medium-to-low resolution) applications. Note also that the range of is spread over time from two orders of magnitude to over six orders of magnitude. This trend benefits from the technology downscaling and it is expected to continue in the coming years.

5.1.2 Conversion Energy and Figures of Merit

Apart from their main specifications (DR (or SNDR) and ), the efficiency of ADCs is quantified in terms of the power consumption required to achieve these specifications. Taking all these ingredients into account, the amount of energy per converted sample —also referred to as conversion energy [5]—can be calculated as [5, 9],

5.1

where is the power consumption and represents the digital output rate of the ADC, that is, the Nyquist rate, measured in samples per second (S/s).

Thus, it is common to analyze and graphically represent the efficiency of ADCs in the form of plots of conversion energy versus DR or SNDR—also known as energy plots [5, 10]. As an illustration, Figure 5.4 shows the energy plot of state-of-the-art Ms. Note that, in order to compute the overall performance achieved by a given M, both magnitudes involved in Figure 5.4—that is, the conversion energy and the resolution (expressed in terms of either DR or SNDR)—must be taken into account. As expected, there is a direct relationship between DR and , so that the larger the resolution, the more conversion energy is needed.

It is therefore convenient to express the trade-off highlighted in Figure 5.4 between the conversion energy and DR in a single performance metric to quantify the performance of a given M and to compare the performance of different ADC architectures. Such a performance metric is often referred to as figure of merit (), and accounts in a single formula the three basic specifications of an ADC, namely effective resolution, signal bandwidth, and power consumption.

Choosing the appropriate is always a matter of debate and discussion. Among others, the following expressions that relate with ENOB have been most frequently used for comparing the performance of ADCs [4, 102, 301]

5.2

5.3

where is the Boltzmann constant and is the chip temperature (measured in Kelvin).

Note that emphasizes power consumption, whereas emphasizes effective resolution. Therefore, the smaller the value and the larger the value, the “better” the ADC is. In this chapter, has been selected because it has been the most commonly used FOM in the recent years by the majority of the M community. It should be noted that according to the definition of ENOB given in Equation 1.20, DR was used for computing ENOB and consequently for the value of as shown in Tables 5.13. However, in those M ICs presenting a strongly nonlinear behavior, the effective resolution (i.e., ENOB) is indeed limited by the peak SNDR, as stated in Chapter 1 and hence, its corresponding is worse than the one shown in the tables. However, the purpose of this chapter is to analyze the overall performance and trends of ADCs, instead of the specifications achieved by a particular design. From this perspective, and considering that not all authors reported all data required to compute , the analysis was based on expressions of derived from DR, instead of from SNDR.

Thus, following an approach similar to that proposed by Murmann [5], the results reported by state-of-the-art performance Ms are compared in Figure 5.4 with two straight lines for the numerical examples of 100 fJ/conversion-step and 10 fJ/conversion-step. Note that the majority of Ms reaching the lowest values of are placed between both lines and correspond to CT circuit implementations, showing the best efficiency of these kinds of Ms for resolutions in the order of 11–15-bit DR within 1–100 MHz bandwidths, as will be discussed later in this chapter.

Figure 5.5 represents versus for the different M architectures included in Tables 5.13. It can be seen how CT-Ms obtain better performance than SC-Ms for MHz, while SC-Ms are more efficient for lower values of . In terms of architectures, it can be noted how LP-Ms obtain better values of than BP-Ms. This is due to the fact that CT BP-Ms digitize signals placed at a notch frequency , which in the majority of cases is in the order of hundreds of megahertz and even in the gigahertz range (Table 5.9). However, this parameter is not considered in , which penalizes its performance compared to LP-Ms as will be discussed later.

Figure 5.6 compares the value of achieved by state-of-the-art Ms with that achieved by Nyquist-rate ADCs. Note that Ms show a competitive performance in a wide range of , from hundreds of hertz to hundreds of megahertz. Only SAR ADCs achieve lower values of within the interval 10 kHz 10 MHz. Pipeline ADCs are the best choice for those applications with 100 MHz 1 GHz, whereas flash ADCs dominate for 1 GHz.

In terms of conversion energy, (as illustrated in Figure 5.7), ADCs are more efficient than SAR and pipeline ADCs for applications requiring DR 12 bit, while SAR ADCs require the lowest conversion energy within the 8–12-bit resolution interval.

5.2 Empirical and Statistical Analysis of State-of-the-Art Ms

Analyzing in detail the data included in Tables 5.13, a number of interesting conclusions can be drawn. This section aims to identify practical pieces of information that can be used as guidelines for designers to make a better decision on the best architecture and circuit technique for a given set of specifications.

5.2.1 SC versus CT State-of-the-Art Ms

Although SC circuit technique has been traditionally used in most reported Ms, more and more ICs are being implemented using CT circuits, especially in those applications targeting broadband signals and/or requiring low power consumption. Overall, approximately 57 of M ICs included in this survey are implemented using SC circuits, whereas 43 of them are CT-Ms. However, as illustrated in Figure 5.8, there is a tendency, in recent years, to use CT techniques. This trend is expected to continue as this kind of Ms will benefit from the technology downscaling process and the increase in transition frequency. Indeed, the decrease in voltage supplies (and consequently the voltage headroom) together with the increasing use of digital signal processing and calibration techniques are favoring the implementation of CT-Ms in nanometer CMOS processes, increasing their operating frequency more and more [10].

Figure 5.9a represents the aperture plot [5] (i.e., vs DR) corresponding to the state-of-the-art SC- and CT-Ms. Note that two state-of-the-art fronts (highlighted in the figure) can be clearly identified. One front—dominated by CT-Ms—goes from approximately 10-bit to 14-bit DR, covering a range from 10 to 150 MHz. The other front—covered by SC-Ms—goes from 14-bit to 21-bit DR with ranging from 400 Hz to 2 MHz. Therefore, as could be logically expected, it can be empirically deduced from these results that CT-Ms are more suitable for medium-resolution (10–14 bit) and medium–high bandwidths (10–100 MHz), whereas SC-Ms are more appropriate for applications requiring high-resolutions (15–20 bit) within low-medium bandwidths (100 Hz–1 MHz).

The resolution-versus-bandwidth regions covered by the state-of-the-art fronts drawn in Figure 5.9a define the application areas where SC- and CT-Ms are more efficient. This is illustrated in Figure 5.9b, where the energy plot is compared for both circuit techniques. Overall, it can be concluded that CT-Ms are more efficient than SC-Ms for .

5.2.2 Gm-C versus Active-RC State-of-the-Art CT-Ms

As already discussed in this book, CT-Ms can be implemented using either active-RC or Gm-C integrators. Active-RC integrators have the advantages of better linearity and larger signal swing, whereas Gm-C integrators are potentially faster with less power consumption, at the price of reducing their linearity as compared to active-RC integrators [302]. In practice, the majority of state-of-the-art CT-Ms have been implemented using active-RC integrators. Sometimes an active-RC front-end integrator is chosen for its better linearity, whereas the rest integrators of the M loop-filter are of Gm-C type. This is the most common situation in LP-Ms, while most BP-Ms operating at notch frequencies in the order of hundreds of megahertz or in the gigahertz band, have been implemented using either Gm-C or Gm-LC integrators.

Figure 5.10a illustrates the conversion region covered by the different CT circuit techniques by showing the aperture plot of state-of-the-art CT-Ms. For the sake of clarity, the different families of CT-Ms have been organized into three categories: Gm-C, active-RC, and active-RC/Gm-C. The latter assumes that only the front-end integrator is active-RC while the remaining ones in the modulator chain are implemented using Gm-C techniques. It can be noted that the state-of-the-art front (highlighted in the figure) is dominated by active-RC implementations.

In terms of , active-RC CT-Ms have demonstrated to be more efficient than Gm-C implementations, as illustrated in Figure 5.10b. It can be shown how active-RC Ms obtain lower values of in a wide range of —from 100 kHz to almost 100 MHz.

5.2.3 Technology Used in State-of-the-Art Ms

A variety of CMOS processes can be distinguished in Tables 5.13. These technologies have been used in the last 20 years by state-of-the-art Ms—going from micrometer CMOS (3-µm technology node) down to nanometer processes (40 nm). Supply voltages have scaled down with technology evolution from 6.5 to 0.5 V. As an illustration, Figure 5.11 shows an histogram of the CMOS technologies employed by the Ms considered in this survey. Note that 180-nm CMOS process has been the technology node most commonly employed in recent years, mainly using a single 1.8-V supply voltage.

As discussed in Section 5.1.1, Ms have demonstrated state-of-the-art performance in many diverse processes, taking advantage of the technology downscaling to create the conditions to increase their conversion region. This is illustrated in Figure 5.12, where is represented over the technology node. Note that the minimum value of achieved by Ms decreases with the technology downscaling, reaching the lowest values for 180-nm CMOS processes.

5.2.4 Single-Loop versus Cascade State-of-the-Art Ms

Single-loop architectures have been more used than cascade topologies. Overall, approximately 80 of the state-of-the-art M ICs considered in this survey are single-loop topologies, whereas only 20 of them are cascades. The latter have been mainly implemented using SC circuits, although recent synthesis methods are making the implementation of CT cascade ICs possible.

In terms of the loop-filter order of single-loop architectures, the second-order topology was the most used by SC-Ms, in of single-bit architectures and of multibit topologies (Tables 5.1 and 5.2). In the case of CT implementations, third- and fourth-order topologies were preferred by single-bit topologies, in and of cases, respectively (Table 5.6). In the case of multibit implementations, loop-filter orders higher than three were implemented in of ICs, taking advantage of the better stability properties of high-order () implementations with multibit quantization.

As far as the cascade topologies are concerned (Tables 5.4, and 5.8), the majority of implementations used a fourth-order loop-filter with two stages in a 2-2 configuration or three stages in a 2-1-1 configuration. Third-order 2-1 implementations are also used by SC cascades in of cases, as shown in Tables 5.3 and 5.4.

Figure 5.13 compares the aperture plot of single-loop and cascade state-of-the-art Ms. It is noted how single-loop dominates almost all ranges of applications from low-bandwidth high-resolution to broadband low-medium resolution. However, as discussed in Section 5.3.1, enhanced techniques are improving the performance of cascade architectures, which may be very suited to implement reconfigurable/adaptive ADCs, thus taking advantage of the very modular nature of the cascade topology.

5.2.5 Single-Bit versus Multibit State-of-the-Art Ms

Multibit quantization is in general more employed than single-bit quantization. The majority of cascade topologies include dual quantization with a multibit quantizer in the last stage in order to attenuate the impact of the nonlinearity of the feedback DAC. However, increasingly more cascade ICs are including internal quantizers with ranging from 2 to 5 bit in all stages combined with proper linearization techniques. In addition, a number of M ICs are including trilevel quantizers to benefit from the extra level provided by fully differential circuit implementation of the embedded flash ADCs, while keeping an inherent linear behavior of the feedback DAC.

In terms of conversion energy, there are more single-bit Ms than multibit Ms achieving a 100 fJ/conversion-step, as illustrated in the energy plot shown in Figure 5.14a. Although multibit implementations can also achieve a good efficiency for resolutions in the order of 12–16 bit, there are more single-bit solutions reaching state-of-the-art performance within this range.

Figure 5.14b compares the aperture plot of single-bit and multibit Ms. It is shown how multibit modulators dominate the state-of-the-art fronts except for those applications with resolutions over 20 bit within signal bandwidths below 1 kHz. Indeed, a number of CT-Ms intended for broadband communications use multibit quantization. Apart from the obvious benefits in terms of the increased number of bits, multibit quantization (and NRZ DAC) is also appealing in practice for its lower sensitivity to clock jitter error, as discussed in Chapter 2. However, the price to pay for using multibit quantization is the inherent nonlinear operation of the multibit feedback DAC, what forces using linearization techniques, with the subsequent penalty in power consumption, speed limitation, and circuit complexity. To address this problem, some authors propose the use of alternative implementations of the modulator feedback waveforms—such as DACs with finite impulsive response (FIR) [154, 161]—to reduce the sensitivity to clock jitter and to relax the M loop-filter linearity specifications, giving rise to a more competitive performance.

5.2.6 Low-Pass versus Band-Pass State-of-the-Art Ms

As stated in Section 5.1.2, LP-Ms obtain better performance in terms of than BP-Ms. This is better illustrated in Figure 5.15, which compares of LP- and BP-Ms. Figure 5.16a shows the aperture plot of LP- and BP-Ms. Note that the state-of-the-art front is dominated by LP-Ms, although the highest values of have been reached by BP-Ms.

Comparing the energy plot of both types of Ms, it can be shown that LP-Ms consume less energy per conversion-step than BP-Ms, as illustrated in Figure 5.16b, where all Ms with 100 fJ/conversion-step are of LP type. However, it should be noted that might not be adequate for quantifying the efficiency of BP-Ms, because may not always be representative of the operating frequency of the modulator. For instance, looking at Table 5.9, it can be noted that there are several ICs digitizing signals with in the order of 10–20 MHz but placed at center (notch) frequencies in the order of gigahertz. For that reason some authors propose alternative FOMs such as the following one [303]:

5.4

which takes into account not only , but also the notch frequency . As illustrated in Figure 5.15, the use of increases the number of state-of-the-art performance BP-Ms, although the comparison may be not fair in this case for LP-Ms.

Figure 5.16c compares the performance of LP- and BP-Ms, based on the following FOM proposed by Schreier and Temes [2]:

5.5

To be consistent with the rest of the FOMs considered in this chapter, SNDR is replaced with DR in the above expression. Note that increases its value for better performing designs. The horizontal dashed line in Figure 5.16c was called the architecture front by Schreier and Temes, while the vertical front is named technology front. The former is absolutely dominated by LP-Ms, while the most advanced architectures in the technology front are BP-M topologies. The latter push the technology process to its limits in terms of digitized signal bandwidth and sampling frequency, at the price of being less efficient in terms of power dissipation. As discussed in the next section, the new generations of BP-Ms are taking advantage of technology downscaling to push Ms forward in terms of speed and efficiency.

5.3 Cutting-Edge M Architectures and Techniques

To conclude this survey, this section presents a review of some of the most relevant cutting-edge M topologies that are in the frontiers of the M designs, identifying their most significant trends, challenges, and practical solutions. The following architecture/circuit techniques are overviewed:

• Sturdy MASH (SMASH) architectures
• Hybrid M architectures, including M-Nyquist ADCs, active–passive CT-Ms, CT/DT circuit implementations
• Multirate Ms
• Multibit Ms with time-coded quantization
• Ms implemented with digital-based circuit techniques
• Adaptive/reconfigurable Ms
• Ultra-high-speed Ms for RF digitization.

A detailed explanation of the aforementioned Ms is beyond the scope of this book. Instead, this section provides an overview of their most significant features, with emphasis on their advantages/drawbacks, design trends, and challenges.

5.3.1 SMASH M Architectures

One of the main limitations of cascade Ms is their higher sensitivity to mismatch than their single-loop counterparts. This may explain why a vast majority of state-of-the-art M ICs (∼) were implemented using single-loop architectures as stated in Section 5.2.4. This limitation has motivated designers to look for alternative implementations of cascade Ms that reduce the sensitivity to noise leakages.

An interesting alternative cascade topology is the so-called Sturdy MASH (SMASH) [304, 305]. The main idea behind this kind of cascade Ms consists of replacing the DCL by the own analog processing provided by the loop-filter integrators together with an additional interstage digital feedback path. As a result, the modulator output can be obtained from a direct digital addition (or subtraction) operation of the different stage outputs in the cascade, with no need for a DCL as in conventional cascades, and the subsequent elimination of matching requirements between the analog and the digital filtering.

Figure 5.17 shows the conceptual block diagram of a two-stage SMASH M.³ Assuming a linear model for the embedded quantizers, the -transform of the modulator output can be written as [305],

5.6

where and represent the NTF and STF of the th stage in the cascade, respectively. Note that the overall NTF of the cascade modulator—that is, the NTF filtering the second-stage quantization error —is the same as that of a conventional cascade M. However, the first-stage quantization error is not completely canceled. Instead, it is filtered by .

Figure 5.18 illustrates how to implement the concept of SMASH Ms in a fourth-order 2-2 topology [305]. Note that the DCL is replaced by direct feedback paths from the output of the second stage to the input of the first stage, although an additional feedback DAC is required. Analyzing Figure 5.18 considering linear models for the quantizers, it is easy to show that the -transform of the modulator output is given by:

5.7

Note from the above expression that a fourth-order high-pass filtering is obtained for both and . In this case, , which according to Equation 5.6, does not give a complete cancelation of . However, can be ideally canceled if , that is, if unity STF (USTF) [307, 308] is implemented in the second stage of the SMASH topology. Indeed, the performance of SMASH Ms can be notably improved if USTF is used in all stages of the modulator, as proposed in [288]. As stated in Chapter 1, the main advantage of using USTF is that integrators ideally process quantization error only and hence, their output swing can be reduced and the tolerance to amplifiers nonlinearities is increased. However, one of the main drawbacks of applying USTF to CT-Ms is that the resulting modulators do feature a worse implicit AAF function.

Figure 5.19 shows a M architecture that extends the underlying principle of SMASH Ms to the implementation of USTF in both stages, thus taking advantage of both strategies (SMASH and USTF) to achieve higher resolution in wideband applications with lower values of OSR. In this example, the -transform of the modulator output is given by:

5.8

Note that contrary to conventional SMASH Ms, the quantization error in the front-end stage is ideally canceled, while avoiding any digital filtering. In addition, the use of a scaling factor (which is usually implemented as a power of 2) will further reduce the in-band noise power of the second-stage quantization error at the output. Moreover, using USTF in both stages of the modulator allows relaxing of the output swing and gain demands in the amplifiers, while keeping a better sensitivity to mismatch than simple SMASH and cascade topologies. However, the price to pay is that a front-end DAC with a full scale larger than that of the quantizers in the cascade (with resolutions and ) is required to account for the summation of the digital outputs of the stages. Nevertheless, the location of the digital adder helps increase considerably the robustness to capacitor mismatches as demonstrated in [288].

5.3.2 Hybrid Ms

An interesting approach in the design of high-performance Ms consists of using hybrid circuit and/or architecture techniques to improve the efficiency of the digitization as compared to conventional Ms. The term hybrid is used here to denote those kinds of Ms that are not, strictly speaking, pure Ms, according to the classification criteria given in Chapter 1. Thus, several categories of hybrid Ms (H-Ms)—some of them listed in Table 5.11—have reported state-of-the-art performance.

Hybrid M-Nyquist ADCs

A first category of H-M architectures is that which results from combining a Nyquist-rate ADC—usually a pipeline, SAR, or cyclic ADC—and a M [216, 228, 272, 273, 280, 286]. In the majority of cases, the basic strategy followed in this kind of H-Ms consists of replacing the embedded multibit flash ADC with another kind of Nyquist-rate ADC architecture, namely pipeline [280, 286], two-step [273], SAR [216], or cyclic [228, 272]. Essentially, the main advantage of this strategy is to provide a way of increasing the number of levels of the internal quantizer without the prohibitive exponential growth of the power consumption and silicon area of flash ADCs.

The idea of hybrid M-Nyquist ADCs has been implemented in both single-loop and cascade architectures, featuring a competitive performance in different application scenarios. As an illustration, Figure 5.20 shows the conceptual block diagram of one of the first reported hybrid M-Nyquist ICs, which consists of in a cascade of a 5-bit second-order M and a 12-bit fourth-stage pipeline ADC [286].

One of the main inconveniences of combining Ms and Nyquist-rate ADCs is that as the number of bits of the Nyquist-rate subADC increases; the circuit complexity, sensitivity to circuit errors, and latency increases as well, with the risk of losing the benefits provided by Ms in terms of system simplicity and robustness against circuit nonidealities. Therefore, although very competitive performance can be achieved by replacing multibit flash ADCs with other alternative Nyquist-rate ADCs, the mentioned design trade-offs have motivated M designers to explore alternative implementations to conventional multibit quantization, as discussed in Section 5.3.4.

Hybrid Active/Passive Ms

Another kind of H-Ms corresponds to a family of CT-Ms in which the loop filter is implemented by hybrid active–passive circuit elements. Thus, part of the loop-filter integrators (resonators in the case of BP-Ms) are implemented as passive-RC networks, while others are implemented as active-RC or Gm-C circuits. The motivation for using this approach is to reduce the number of OTAs and hence reduce the power dissipation, as OTAs are the circuit blocks that consume most of the power in a M. As already discussed in this book, the design issues associated with loop-filter OTAs aggravate in nanometer CMOS technologies with reduced supply voltage, and particularly in wideband applications where the dynamic requirements of the operational amplifiers yield in many cases to very power-hungry circuit solutions.

In this scenario, replacing some active integrators with passive-RC networks in the M loop-filter results in a more efficient solution. Apart from the power saving, integrated passive-RC networks have better linearity than their active counterparts. However, the main limitation of using passive integrators is that they do not provide any gain that makes the loop filter more sensitive to their error mechanisms. This limitation can be partially palliated if the active integrators are used at the front-end of the modulator, so that the effect of thermal noise of the passive-RC networks and other circuit nonideal effects can be reduced by the preceding active integrators. Figure 5.21 shows an example proposed by Song et al. in [275]. The modulator architecture—consisting of a fifth-order single-loop architecture—uses five integrators, two of them implemented by passive-RC networks. These passive integrators are placed in the second and fourth positions of the modulator chain, so that their nonideal effects can be attenuated by the gain of active integrators.

Prompted by the above mentioned potential benefits, passive-RC networks are becoming a popular circuit solution for the implementation of low-power wideband CT-Ms. A good example is the fourth-order BP-M reported by Chae et al. [236], which digitizes 24-MHz band-pass signals located at 200 MHz with 58-dB SNDR while consuming 12 mW. This circuit is implemented by using single-opamp high-Q resonators that incorporate positive feedback to achieve high Q and are implemented by combining an active LPF and a passive HPF. Another interesting example was proposed by Srinivasan et al. [161], who reported a third-order CT-M made up of a front-end passive-RC integrator followed by two Gm-C integrators. The chip—fabricated in a 45-nm CMOS technology—digitizes 60-MHz signals with 61-dB SNDR and 20 mW power consumption, while clocked at 6 GHz—one of the highest clock frequencies reported by M ICs to date. This trend is expected to continue, with the demand for higher and higher data rates and the technology downscaling, which will facilitate the integration of high-quality passive devices together with conventional active circuits.

Hybrid CT/DT Ms

The third category of H-Ms included in Table 5.11 corresponds to those Ms in which the loop filter is implemented by both SC and CT integrators, thus taking advantage of both circuit techniques. As shown earlier in this chapter, CT-Ms operate at faster rates than their SC counterparts with relatively lower power dissipation. However, CT-Ms are more sensitive than SC-Ms to some circuit and architecture error mechanisms, such as circuit-element tolerances, excess loop delay, and clock jitter error.

Some authors have tried to circumvent the mentioned limitations of CT-Ms by using the so-called hybrid CT/DT Ms, in which some parts of the loop filter—usually the front-end building blocks—are implemented using CT circuits, thus providing potentially faster operation and embedded antialiasing filtering with reduced power consumption [279, 281–283, 294, 309, 310]. Thus, hybrid CT/DT Ms have been demonstrated using both single-loop [281, 283] and cascade ICs [279]. The most common situation in practice consists of using a CT front-end integrator, whereas the remaining integrators in the modulator loop are implemented using SC circuit techniques. As an illustration, Figure 5.22 shows one of the first practical implementations of a hybrid CT/DT cascade M, proposed in [279]. This modulator is a cascade of a second-order (active-RC) CT-M stage with a first-order SC stage, considering 4-bit quantization in both stages.

In spite of the mentioned advantages, reported hybrid CT/DT M ICs do not really exploit the potential capability of CT circuits integrated in CMOS processes to operate up to the gigahertz range with reasonable linearity. This is partially due to the fact that the maximum sampling rate of hybrid CT/DT Ms is indeed limited by the SC part of the modulator loop filter. A possible solution to alleviate this restriction could be using the so-called multirating, as described in the next section.

5.3.3 Multirate Ms

The so-called multirate (MR) Ms are a particular kind of Ms in which a different sampling frequency is used at different parts of the modulator. The most common approach is based on using a lower sampling frequency in the building blocks placed at the front-end of the modulator—where most of the power is consumed—and a higher sampling rate in the subsequent subcircuits, where the dynamic requirements can be relaxed [311]. This concept can be applied to either single-loop or cascade architectures and implemented using SC [311] and CT circuits [312]. Without loss of generality, this section focuses on cascade implementations because the modular nature of these topologies makes the implementation of MR-Ms more simple and robust. However, similar considerations can be derived for single-loop MR-M topologies.

Upsampling Cascade MR-Ms

Figure 5.23a shows the conceptual implementation of a conventional cascade (two-stage) MR-M.⁴ For the sake of generality, multibit quantization will be assumed in all stages of the cascade, with being the number of bits of the internal quantizer in the th stage. The sampling frequency of the different modulator blocks is depicted in the figure. The most common situation in conventional MR-Ms is that the front-end stage operates at , whereas the remaining th stages are sampled at . This approach—also referred to as upsampling MR-M [313]—benefits from increasing values of OSR in the back-end stages—where the dynamic requirements are less demanding than in the front-end stages [311, 312, 314].

The operation behind the modulator in Figure 5.23a is conceptually the same as in a conventional monorate cascade M. All stage outputs are combined by the DCL transfer functions—clocked at —so that ideally only the quantization error of the last stage remains and it is shaped by an NTF whose order () is the sum of the orders of all stages in the cascade (). However, as a consequence of using several sampling frequencies,additional upsampler blocks—represented conceptually in Figure 5.23a—are required.

Assuming that STF and NTF, and defining DCL so that and , it can be shown that the IBN power at the output of the modulator is approximately given by⁵

5.9

where , represents the quantization step of the last quantizer, and [313].

Hybrid CT/DT Cascade MR-Ms

The concept of MR-Ms can be extended to hybrid CT/DT implementations as conceptually depicted in Figure 5.23b, that represents a cascade two-stage MR H-M. The circuit nature (either CT or DT) of the different modulator blocks as well as their corresponding sampling frequencies are highlighted. The use of a complete CT stage (instead of just the front-end integrator for instance) maximizes the embedded AAF, while taking advantage of the relaxed dynamic requirements of the front-end CT circuits as compared to their DT counterparts [279].

The analysis of Figure 5.23b can be carried out by applying a DT–CT transformation to the front-end stage of Figure 5.23b. The resulting MR H-M is equivalent to the original MR DT-M. As stated in Chapter 1, this CT–DT equivalence can be guaranteed because of the DT nature of the (open) loop transfer function from the front-end quantizer output to the sampled quantizer input [315, 316]. This way, considering this CT–DT equivalence and assuming a linear model for the quantizers, it can be shown that the IBN of the modulator in Figure 5.23b is also given by Equation 5.9.

Downsampling Hybrid CT/DT Cascade MR-Ms

Using lower values of the OSR in the front-end CT stage of Figure 5.23b may be beneficial when the subsequent SC stages can operate at high enough values of OSR. However, the use of high values of OSR in the back-end stages is not practical when digitizing wideband signals, for instance in the order of 10–100 MHz. In these cases, sampling rates in the order of gigahertz may be necessary to digitize such signals with low-medium effective resolutions (8–10 bit). Therefore, the use of back-end SC stages may be not feasible because of the prohibitive values of GB required for theoperational amplifiers.

The mentioned problems can be alleviated if the concept of multirating is redefined just in the opposite way as it was conceived, that is, going from an upsampling MR system—in which the front-end stage rate is increased in the subsequent stages—to a downsampling MR system—in which the front-end (CT) stage operates at the highest rate, thus benefiting from their potentially faster operation [313].

Figure 5.24 shows a conceptual block diagram of a downsampling (two-stage) cascade MR H-M architecture proposed in [313]. In contrast to conventional (upsampling) MR H-Ms, the back-end (DT) stage operates at a rate lower than that of the front-end (CT) stage, that is, . The main drawback of this approach is the aliasing caused by the downsampling processing, which requires using an interstage AAF. However, as shown in [313], the operation of the AAF can be completely translated to digital domain by using two additional digital blocks of the transfer functions which are named and . In this way, Figure 5.24 has the same number of analog building blocks as a conventional cascade M.

Therefore, the operation behind the modulator in Figure 5.24 is essentially the same as in conventional cascade Ms. The main difference is that the DCL transfer functions are designed so that they must remove not only the quantization error of the front-end stage , but also its aliased components. To this purpose, and must be reconfigurable and programmable according to the value of the downsampling ratio (). These functions are completely implemented in the digital domain, without any extra analog hardware required, and can be easily synthesized for different values of as detailed in [313]. As a consequence, the resulting MR-Ms are potentially faster, less sensitive to circuit error mechanisms, and more power efficient than conventional upsampling MR architectures.

Compared to single-rate cascade pure CT-Ms, downsampling MR H-Ms may be less power efficient if the same specifications are required. However, under such conditions, downsampling MR H-Ms becomes less demanding in terms of some circuit nonidealities such as finite DC gain and circuit-element tolerances, as demonstrated in [313].

5.3.4 Multibit Ms with Time-Coded Quantization

In addition to increasing the bandwidth of digitized signals, significant efforts have been carried out in recent years to improve the performance of the embedded multibit quantizers used in most state-of-the-art Ms. As already discussed in different parts of this book, multibit quantizers are usually implemented by flash ADCs, which are generically made up of a resistive ladder and a bank of comparators. As already mentioned, the number of comparators increases exponentially with the number of bits , with the subsequent penalty in silicon area and power dissipation.

An alternative technique to reduce the number of comparators is based on the so-called tracking quantizer [199] that uses a counter and a switching matrix to connect the reference voltage to the comparators inputs according to the value of the quantizer input ranges. However, although the power consumption is reduced, the efficient implementation of conventional multibit quantizers based on flash architectures is becoming a design challenge because of the reduction in voltage supplies associated with CMOS technology downscaling. As a consequence, the dynamic range may become severely degraded by the effect of comparator offset and hysteresis [317].

The mentioned problems have motivated the exploration of alternative circuit implementations of multibit quantizers embedded in Ms. The majority of these techniques are based on changing the concept of signal quantization, going from an amplitude coding to a time coding. The main benefit of this approach is that the resulting quantization methods are more suited for the implementation in low-voltage (1 V) nanometer CMOS processes [318], although special care must be taken in terms of those errors that are directly related to the timing, such as clock jitter error in CT-Ms.

Figure 5.25 shows the conceptual block diagram of the three basic alternative approaches for the implementation of time-coded quantizers which have been successfully reported in state-of-the-art M ICs, some of them listed in Table 5.10. The first one—depicted in Figure 5.25a—consists of using a voltage-controlled oscillator (VCO) instead of a multibit quantizer [259–262, 265]. The idea is based on translating the quantized information in the amplitude domain to the time domain by means of a voltage-to-frequency conversion that can be performed by a VCO circuit as proposed in [265]. The principle of operation behind this approach is based on the use of a ring oscillator to count the number of edges within a given time period. The result is directly related to the input signal, thus obtaining a digital representation of the input amplitude.

The main limitation of VCO-based quantization is the inherent nonlinear operation associated with the voltage-to-frequency conversion implemented in the VCO. This limiting factor can be mitigated by using a phase detector instead of a frequency detector as proposed in [259], which provides also a first-order noise shaping. Alternatively, VCO-based quantizers can be embedded in the back-end stage of a cascade M, such that their nonlinearities are attenuated by the noise shaping of precedent stages in the cascade. An interesting implementation of this idea, proposed by Asl et al. [261], consists of a two-stage cascade upsampling MR M, in which the back-end stage (operating at a higher rate) is implemented by a VCO-based quantizer, thus benefiting from its potentially higher operation speed without being penalized by its intrinsic nonlinearity.

An alternative to VCO-based quantizers consists of using pulse-width modulation (PWM) [209], as conceptually depicted in Figure 5.25b. The PWM block converts the voltage at the output of the loop filter into a pulse with corresponding width and a time-to-digital converter (TDC) generates digital codes that are discrete representations of the edges of the signal, that is, a time-quantized representation. One of the main limitations of PWM-based quantizers is their limited dynamic range [317]. It can be enhanced by using the so-called time-enconding quantizer (TEQ) as illustrated in Figure 5.25c [171]. Essentially, the idea underlying TEQ-based Ms consists of using a modulator (a CT-M in the figure) whose loop filter is split into two loops, one of which is made to oscillate, thus providing an independent control of the oscillation as a difference with PWM-based quantization schemes [187].

5.3.5 Mostly Digital Ms

Time-to-digital conversion techniques have not only been used for replacing embedded flash ADCs, but also for the main building blocks of a M. A good example of using voltage-controlled ring oscillators as an essential part of Ms was proposed by Taylor and Galton in [264]. The proposed modulator—mostly implemented by digital circuit techniques—consists of a digitally background-calibrated voltage-controlled ring oscillator (VCRO), in which its inverters are sampled at the required output sample-rate without containing any analog integrators, comparators, or feedback DACs. The main advantage of this approach is that as the M is essentially implemented by digital circuits, it may benefit from the CMOS technology downscaling in terms of speed, with the subsequent advantages for low-voltage low-power wideband applications. Moreover, the operation of VCRO-based Ms essentially depends on the speed of its digital blocks, thus trading accuracy for signal processing. The main limitation of this approach is its higher sensitivity to timing errors, such as clock jitter error and the aforementioned nonlinear behavior of VCOs. These problems are overcome in [264] by using digital backgroundcalibration and self-canceling dither techniques, yielding to state-of-the-art results.

Apart from the mentioned time-coded circuit techniques, there have been some other approaches to digitize M loop filters: by replacing their critical analog building block—essentially the OTAs—with alternative digital-based solutions. This is the case of the comparator-based [36] and inverter-based [12, 276] integrators used in Ms, in which their embedded OTAs are replaced by comparators and inverters, respectively. As an illustration, Figure 5.26 shows the block diagram of the inverter-based second-order single-loop M proposed by Chae and Han in [12]. The modulator—implemented using very simple circuits—achieves 63-dB peak-SNDR within 8-kHz bandwidth, while consuming only 5.6 µW from a 1.2-V supply. These results demonstrate that the use of digital-based circuit techniques may become very energy efficient while keeping a cutting-edge performance. Indeed the use of inverters to emulate the transconductance operation, such as the well-known Nauta's transconductor [319], as well as improved versions of this idea, are gaining popularity in the analog design community, for instance in the design of widely tunable filters [320].

However, despite the aforementioned benefits of replacing OTAs with digital-based circuit solutions, it should be noted that simple circuits such as inverters, cannot be seen as the panacea for all analog design problems in Ms. In practice, there is always a trade-off between the required electrical performance of a given building block and the circuit complexity in terms of number of transistors, with the subsequent penalty in power consumption, silicon area, impact of parasitics, etc. Therefore, a simple inverter circuit cannot replace a high-performance OTA. However, depending on the modulator specifications and target application, digital-based integrators could be a suited circuit solution. For instance, this might be the case in some biomedical applications demanding very low power consumption and/or wideband applications requiring ultra-high-speed loop-filter circuits. In both cases, the required DR is typically below 60–70 dB, which might not be very demanding in terms of finite DC gain of loop-filter building blocks and, consequently, the use of simple digital-based circuit solutions may result competitive. Nevertheless, the use of digital techniques is still at an early stage and it is expected that circuit improvements derived from technology downscaling will make possible that Ms become more and more digital in a near future.

5.3.6 Adaptive/Reconfigurable Ms

The integration of entire wireless telecom systems into mainstream low-cost digitally oriented nanometer CMOS technologies together with the continuous increasing number of standards, operation modes, and applications, is driving the need of the so-called adaptive/reconfigurable ADCs, which are a particular kind of ADC that can reconfigure its performance metrics to different sets of specifications with adaptive power consumption. However, the practical implementation of this kind of ADCs involves a number of practical issues and trade-offs at both architecture and circuit level, which must be taken into account to optimize the performance in terms of power budget. This problem is indeed aggravated as efficiency is required in an increasingly wide tunable region in the resolution-versus-bandwidth plane.

In this application scenario, Ms are very suited for the implementation of this kind of ADC as the variation of their basic parameters—OSR, , and —can easily contribute to adapting the ADC performance to different requirements with optimized power consumption and large hardware reuse [321].

Reconfiguration at Architecture Level

The aforementioned reasons explain why state-of-the-art multistandard, multimode ADCs have been mainly implemented using Ms. Indeed, a number of adaptive/reconfigurable M ICs have been reported in the literature, implemented with both SC and CT circuit techniques, as summarized in Tables 5.12 and 5.13, respectively. The majority of the Ms included in these tables are able to digitize more than three standards [85, 287–295, 297], achieving cutting-edge performance while digitizing signals with ranging from hundreds of kilohertz to tens of megahertz. Although changing the sampling frequency has been the reconfiguration strategy most commonly applied, the mandatory use of low values for OSR in wideband standards has forced Ms to achieve the required DR by resorting to different strategies, including adaptive high-order shaping [287, 292], switchable cascade topologies [290, 291, 297], multirating [290], programmable notches within the signal band [287, 300], and multibit embedded quantizers with adjustable number of bits [85].

Adaptation at Circuit Level

The mentioned architecture reconfiguration strategies are frequently combined with circuit/transistor-level techniques in order to increase the energy efficiency of adaptive/reconfigurable Ms. Among others, one of the most commonly used circuit techniques consists of implementing switchable unit cells, such as OTAs [295, 300], or unit capacitors [237, 298], in which a different number of unit elements is connected depending on the required electrical performance of a given M building block. Apart from the former circuit-level reconfiguration techniques, programmable bias current generators are frequently used in order to adapt the bias current and, subsequently, the power consumption of the amplifiers (and the preamplifiers used for the comparators) to the different operation modes covered by the reconfigurable M [291, 298].

Concurrency

Although both single-loop and cascade topologies report state-of-the-art performance, cascade Ms are a priori more suitable architectures for the implementation of adaptive/reconfigurable ADCs. Indeed, the modular nature of cascade topologies allows to easily turn different stages either on or off depending on the loop-filter order required for a given set of specifications, while keeping system stability and low sensitivity to circuit nonidealities. In addition to reconfiguring its performance parameters, a multimode ADC must digitize signals corresponding to different standards in a parallel or concurrent way—that is, GSM and Bluetooth signals, and/or UMTS and WLAN signals.

Concurrency can be easily implemented in a cascade M as conceptually illustrated in Figure 5.27, where a concurrent switchable network is used for allowing the modulator to be configured as several submodulators working in parallel, each one processing a different input signal. A number of control signals are needed to enable the switches that correspond to the desired operation mode in each case, either concurrent or cascaded. Moreover, a programmable DCL is required, which should be adapted to the concurrent operation and/or the number of stages working as either isolated single-loop modulators or as parts of a cascade. The price to pay is an increase in the complexity of the digital control circuits as compared to conventional Ms. However, the implementation of digital circuits benefits from technology downscaling, which may result in a more efficient solution than using separate ADCs operating in parallel. Thus, the majority of state-of-the-art reconfigurable Ms focus their efficiency in achieving reconfigurability and adaptability. The increasing need of implementing concurrency in modern mobile handheld terminals has motivated doing more research on this topic and the first experimental evidences of implementing this feature have already been reported [322].

5.3.7 Ultra-High-Speed CT-Ms for RF Digitization

As previously explained in this chapter, more and more CT-Ms are demonstrating to be a competitive solution for the implementation of power-efficient ADCs operating in the gigahertz range [154, 161, 181, 207, 232, 239, 251, 323]. This feature has prompted the interest of RF circuit designers to use CT-Ms in digital-intensive RF transceivers. Thus, in addition to digitize signals, CT-M ICs might take advantage of their CT circuit nature to merge some RF functionalities such as blocker-rejection filtering, frequency-mixing process, channel-selection and antialiasing filtering, and so on [155, 176, 203, 233, 284]. All these functionalities can be embedded within the M feedback loop as conceptually depicted in Figure 5.28a, thus resulting in more compact RF receivers, with a reduced complexity in the analog hardware and the subsequent benefits in terms of sensitivity to circuit imperfections and power/area scalability with technology.

A fully digitized RF receiver, conceptually illustrated in Figure 5.28b, should place the analog-to-digital interface as close as possible to the antenna—an approach commonly referred to as RF-to-baseband digitization or RF-to-digital conversion [251]. Although this is the ideal implementation of the so-called software-defined radio (SDR) paradigm [324], its practical application scenario is still far from a consumer product deployment. This is mostly limited by the unfeasible power-hungry requirements demanded by the ADC, particularly in terms of signal bandwidth, linearity, and dynamic range, supporting signal levels from the sensitivity to the full strength. In order to reduce the power consumption, some authors propose using BP-Ms to digitize IF signals [232, 236], by implementing an IF-digitization scheme as that shown in Figure 5.28a. This way, after being preamplified by the LNA and downconverted from RF to IF in the mixer, the incoming signal is digitized by a CT BP-M. A good example of this compact and power-efficient solution is reported by Harrison et al. in [232]. The modulator is integrated in a 40-nm CMOS technology and digitizes 20-MHz signals placed at 700–800 MHz with 70-dB SNDR, dissipating 20 mW when clocked at 3.2 GHz.

In spite of the strong specifications required by RF-to-digital converters, the recent advances in BP-M ICs—particularly some ICs implemented using CT circuits listed in Table 5.9—are pushing RF digitization forward, taking significant steps toward future implementations of SDR mobile devices based on the conceptual scheme of Figure 5.28a. It is interesting to note that one of the ICs in Table 5.9, reported by Martens et al. in [251], is clocked at 8.88 GHz, which is the highest sampling rate reported to date by CMOS Ms. The chip presented in [251] is a fourth-order CT BP-M with a notch-frequency placed at , that is, 2.2 GHz. This high-speed operation can be achieved by combining six time-interleaving quantizers with a polyphase decimation filter, which allows RF digitization at 2.2 GHz with 48-dB DR within 80-MHz bandwidth, while consuming 164 mW.

The majority of these state-of-the-art CT BP-Ms intended for RF-to-baseband digitization use a fixed center frequency or notch frequency and combine diverse strategies to relax the ADC requirements—such as out-of-band embedded filtering [250] or subsampling [234]. A good example was proposed by Ryckaert et al., who reported the design of a six-order BP-M—conceptually depicted in Figure 5.29—which uses the subsampling technique [325] for digitizing signals centered at 2.4 GHz with GHz, that is, a ratio of . The loop filter—implemented by Q-enhanced LC resonators—is made tunable by varying tank capacitors such that the operation of the ADC can be adjusted to the desired center frequency. However, a wider tuning range is required in order to implement an SDR receiver.

Indeed, one of the problems associated with conventional BP-Ms with a fixed notch-frequency is that the RF receiver requires a programmable frequency synthesizer (Figure 5.28) in order to place the signal band within the pass-band of the BP-M. This issue has motivated the interest for reconfigurable BP-Ms with wide tunable notch-frequency. On the basis of this strategy, Yamamoto et al. reported in [326] one of the widest tuning ranges for the notch-frequency achieved by SC BP-Ms, ranging from DC to 12.6 MHz. This tuning range can be significantly increased by using CT-Ms, as reported by Shibata et al. in [239], where a sixth-order reconfigurable LP/BP-M IC features a DC-to-1 GHz tunable notch-frequency, at the price of consuming 550 mW.

Another interesting approach of using CT BP-Ms with a reconfigurable 0.8–2 GHz notch-frequency was reported by Gupta et al. in [253, 323]. In this case, a second-order topology is integrated together with a quadrature phase-locked loop (QPLL) to allow quadrature phase synchronization between a raised-cosine feedback DAC and the embedded quantizer. As shown in Table 5.9, the chip digitizes 1-MHz signals placed at 797 MHz with a DR of 8.3 bit, while consuming 41 mW, out of which 11 mW are consumed by the QPLL.

In conclusion, the trend toward RF digitization is expected to continue, as revealed by the increasing number of CT BP-Ms operating in the gigahertz range that are becoming commonplace. The main issue of this approach is the power consumption that must be reduced in order to be competitive with conventional approaches based on a direct-conversion receiver made up of an analog signal conditioning (basically an LNA, a mixer, and a baseband filter) followed by a reconfigurable LP-M [321].

5.4 Classification of State-of-the-Art References

For the sake of clarity, this chapter is concluded by grouping the references on the state-of-the-art M ICs, according to the same classification criteria followed in Tables 5.13:

• SC single-loop single-bit LP-Ms: [12–54]
• SC single-loop multibit LP-Ms: [22, 55–98]
• SC cascade single-bit LP-Ms: [19, 99–116]
• SC cascade multibit LP-Ms: [38, 76, 110, 117–136]
• SC BP-Ms: [137–153]
• CT single-loop single-bit LP-Ms: [154–192]
• CT single-loop multibit LP-Ms: [193–226]
• CT cascade LP-Ms: [227–231, 297]
• CT BP-Ms: [232–258]
• Ms with time-coded quantization: [259–268]
• Hybrid Ms: [215, 228, 269–286]
• SC reconfigurable Ms: [85, 287–291, 300]
• CT reconfigurable Ms: [292–299].

5.5 Summary

This chapter presented an analysis of the state of the art on CMOS Ms, making a systematic classification of their architectures, circuit techniques, and target applications. On the basis of the practical approach followed in this book, the empirical data extracted from this statistical survey has been applied to identify design trends and challenges in order to help designers select the most suitable M among different families for a given application and/or range of specifications. With this practical objective in mind, a number of design trade-offs have been discussed at different abstraction levels, namely architecture level (i.e., single-loop vs cascade, single-bit vs multibit, low-pass vs band-pass), circuit-level (i.e., SC vs CT, Gm-C vs active-RC), and technology process. The conclusions derived from the presented statistical and empirical analysis can be used as a practical guide to be incorporated in the top-down/bottom-up systematic design procedure described in this book.

The chapter is concluded with a review of cutting-edge M ICs, considering diverse circuits and systems techniques, namely: advanced cascade topologies, hybrid implementations, MR architectures, time-coded quantization, digital-based loop-filter implementations, adaptive/reconfigurable architectures, and ultra-high-speed Ms.

As a final conclusion, it could be said that compared to other kinds of ADCs, M techniques cover the widest resolution-versus-bandwidth region, targeting more and more applications and taking advantage of CMOS technology downscaling. This trend is expected to continue with the development and improvement of some architecture and circuit techniques—particularly using CT circuits, time-code quantization, and an intensive use of digital-assisted analog circuits—which will all push Ms forward, increasing their dominance in a growing number of data-conversion applications.

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¹ The data corresponding to the power consumption accounts only for the M, excluding the power consumed by the decimation filter.

² Some authors use to represent versus DR or SNDR, often referred to as aperture plot [5, 10].

³ The concept of SMASH Ms has been also applied to multistage cascade architectures [306].

⁴ For the sake of simplicity, two-stage cascade architectures are discussed in this section without loss of generality. This analysis can be extended to -stage cascade MR-Ms as shown in [313].

⁵ Subscript USMR is used for noting UpSampling MultiRate in order to differentiate from the downsampling multirate (DSMR) concept discussed later in this section.