6.3 Oxidation and Oxide/SiC Interface Characteristics
A unique advantage of SiC is that it is the only compound semiconductor that can be thermally oxidized to give high-quality 
. Therefore, thermal oxides of SiC are utilized as a gate dielectric in metal-oxide-semiconductor (MOS) devices as well as to passivate the SiC surface. However, the most striking difference from Si technology is, of course, carbon atoms, which are one of the host elements in SiC. A number of review papers on SiC MOS have been published [146–156]. In spite of continuous improvement of the SiC MOS interface, the quality, and the community's understanding of the factors which control this quality, is still at far from a satisfactory level. This subsection describes the common features, present understanding, and problems in SiC MOS technology.
6.3.1 Oxidation Rate
Thermal oxidation of SiC is expressed by the following simple equation:
Therefore, a thermal oxide of SiC is 
, the formation of which can be confirmed by X-ray photoelectron spectroscopy (XPS), electron energy loss spectroscopy (EELS), and Auger electron spectroscopy (AES). Taking into account the Si density in SiC, the amount consumed during thermal oxidation of SiC can be calculated as 46%, which is close to the value for thermal oxidation of Si. For example, to grow 100 nm of 
on SiC, 46 nm of SiC are consumed. During thermal oxidation, most of the carbon atoms in SiC are removed and diffuse out as carbon monoxide (CO) molecules, and a small portion of carbon atoms diffuses into the SiC bulk region, leading to reduction of carbon-vacancy-related defects [157]. However, the thermal oxide is not completely free of carbon, and it is believed that carbon atoms remain near the oxide/SiC interface. More detail is given in Section 6.3.4.
Figure 6.30 shows the oxide thickness versus the oxidation time for thermal oxidation of SiC at various temperatures for (a) (0001) and (b) 
. The oxidation was performed in 100% dry 
, and results on (0001) and 
faces are plotted. Oxidation on the 
face is about 8–15 times faster than that on the (0001) face. This phenomenon can be used to identify the polarity of unknown crystal faces [158]. The oxide thickness shown in Figure 6.30 can be reasonably explained by the Deal–Grove model, which was developed for Si technology [159, 160]:
where 
is the oxide thickness and 
the oxidation time. 
and 
are called the parabolic rate constant and linear rate constant, respectively. Note that a modified Deal–Grove model gives a better agreement with experimental results [161]. The oxide thickness is almost proportional to the oxidation time when the oxide is very thin (surface-reaction-limited regime). The oxidation gradually exhibits slowdown, and the oxide thickness becomes almost proportional to the square root of the oxidation time when the oxide becomes thick (diffusion-limited regime) [161–164]. However, there is large scatter in the reported values of the activation energies of the linear rate constant 
and the parabolic rate constant 
in the literature. In recent years, a clear deviation of experimental results from this model has been pointed out and a modified model has been proposed [165]. In this model, emission of silicon and carbon atoms from the oxidation interface is considered and the abnormally fast oxidation rate in the initial stage can be qualitatively explained. This model explains well the oxidation rate of SiC(0001) and 
under a wide range of oxidation conditions. However, the exact reactions during thermal oxidation of SiC at a microscopic level have not yet been fully clarified.
Figure 6.30 Oxide thickness versus the oxidation time for thermal oxidation of SiC at various temperatures for (a) (0001) and (b) 
( [161] reproduced with permission from AIP Publishing LLC).
As is the case in Si technology, wet (including pyrogenic) oxidation results in a faster oxidation rate than dry oxidation. It is known that long wet oxidation can create surface pits at the locations of dislocations, because of enhanced oxidation near the dislocation cores [166, 167], while the pit formation is much smaller in dry oxidation. Enhanced oxidation is also observed at the implanted region. Even after post-implantation annealing at 1600–1700 °C, an implanted region contains weak 
bonds and can be oxidized at a faster rate. The oxides grown on the implanted regions are usually 10–40% thicker than those on the non-implanted regions; the enhancement factor depends on the implantation, annealing, and oxidation conditions.
As described above, the oxidation rate depends strongly on the crystal face in SiC [158, 168–170], and this anisotropy must be carefully taken into account in device fabrication. Under any oxidation conditions (dry/wet, any temperature), oxidation is the fastest on 
and the slowest on (0001). The oxidation rates on the 
or 
faces are in between those on (0001) and 
. An example of this is shown in Figure 6.31, where the oxide thickness is plotted as a function of the angle from the 
face. This strong anisotropy is particularly important in the fabrication of trench MOSFETs. When trench MOSFETs are processed on a SiC(0001) wafer, the oxide thickness is largest on the trench sidewalls and smallest near the bottom (and top) of a trench. Thus, a special design and structure must be employed to avoid breakdown of gate oxides near the trench bottom. In the case of trench MOSFETs on 
, the profile of oxide thickness in the trench is ideal, the thickness is smallest on the sidewalls and largest near the trench bottom [170].
Figure 6.31 Anisotropy in the oxidation rate in hexagonal SiC, where the oxide thickness is plotted as a function of the angle from the 
face ( [169] reproduced with permission from Wiley-VCH Verlag GmbH).
6.3.2 Dielectric Properties of Oxides
Figure 6.32 shows the current density–electric field 
characteristics for 40-nm-thick thermal oxides grown on n-type 4H-SiC(0001) and 
surfaces. The oxides were formed by dry oxidation at 1200 °C. The 
characteristics were obtained by applying positive voltage to the gate of n-type MOS capacitors (accumulation state). Thermal oxides adequately formed on high-quality SiC exhibit very good dielectric properties, with a resistivity over 
at low electric field 
. The breakdown electric field of thermal oxides on SiC is approximately 
, which depends strongly on the oxidation condition, gate material, and surface roughness [171–174].
Figure 6.32 Current density–electric field 
characteristics for 40-nm-thick thermal oxides grown on n-type 4H-SiC(0001) and 
surfaces. The oxides were formed by dry oxidation at 1200 °C.
In the high-field region, the current through an oxide is governed by the Fowler–Nordheim tunneling current 
, which is expressed by the following equation [8, 175].
Here, 
is the electric field strength in the oxide, 
is the effective mass of an electron in the oxide, 
is the barrier height, or the conduction band offset 
between the oxide and semiconductor. The barrier height can be estimated from the slope of a Fowler–Nordheim 
plot. The barrier height is also obtained from high-resolution XPS [176] or internal photoemission (IPE) measurements [177]. As shown in Figure 6.32, the onset electric fields for FN tunneling current are about 
for 4H-SiC(0001), 
for 
, and 
for Si. This difference is caused by different band structures, as shown in Figure 6.33 [176]. Figure 6.33 shows the band line-ups for dry oxide/n-type 4H-SiC(0001) and 
structures which were determined from synchrotron-radiation XPS. Because of the wider bandgap and smaller electron affinity of SiC compared with those of Si, the barrier height (
or 
) is inherently smaller in SiC. It has been argued that this smaller barrier height may limit the oxide reliability of SiC MOSFETs, especially at high electric field and high temperature [178]. Furthermore, the barrier height for SiC is dependent on the crystal face. Since 
is a polar face, there exists a significant dipole at the 
interface. As a result, the barrier height on 4H-SiC(0001) (2.7–2.8 eV) is higher than that on 
(2.4–2.5 eV). This trend is valid for any 
system, though the absolute values of barrier height vary for different processes (for example, the barrier height is increased on 
in the case of wet oxidation).
Figure 6.33 Band line-ups for dry oxide/n-type 4H-SiC (a) (0001) and (b) 
structures, determined from synchrotron-radiation XPS ( [176] reproduced with permission from Trans Tech Publications).
Oxide reliability under high electric field has been extensively investigated [173, 179–182]. The oxide reliability in terms of dielectric properties is usually evaluated by time-dependent dielectric breakdown (TDDB) tests [183]. For example, a number of MOS capacitors are biased at very high electric field 
in the accumulation state, to force the Fowler–Nordheim tunneling current. The capacitors are either maintained at a fixed voltage (constant field stress) or constant current density (constant current stress). Either the time time-to-breakdown, 
, or the charge-to-breakdown, 
(which is the integrated current until breakdown) is monitored for each capacitor. After collecting these data, the distribution of 
or 
is analyzed by using a Weibull plot [183]:
Here 
is the cumulative failure probability, 
the time-to-failure for each device. 
is the characteristic time-to-failure and 
the shape parameter (or Weibull slope). When 
, the left-hand side of Equation 6.4 goes to zero, indicating that the characteristic time-to-failure 
is the time for 63.212% of the devices to fail. When a number of devices with different areas are compared, the Weibull plot scaled by the area is useful [183, 184]:
Here 
and 
are the areas of the test devices, 
and 
are their cumulative failure probabilities. In TDDB tests on SiC MOS capacitors, dislocations and particles can affect the oxide reliability, and the 
and 
tend to become smaller with increasing device area. When the area-scaled Weibull plot is employed, a more universal trend appears [184].
Figure 6.34 shows Weibull plots of 
for several oxides formed on n-type 4H-SiC(0001) [185]. In this case, a high mean value of 
and its steep slope (tight distribution) are desirable to ensure the oxide reliability. The oxide reliability depends strongly on the oxidation/annealing conditions, the quality (defect density) of SiC, the surface roughness, the device area, and the gate material, as well as other factors. In spite of several concerns pointed out in the early stages, the oxide reliability reported in the literature is rather promising, at least for temperatures below 300 °C. A few groups reported that screw and basal-plane dislocations in SiC epilayers cause severe reduction in 
and 
of the thermal oxides formed on these areas [173, 181]. It was eventually discovered that these dislocations themselves are not always harmful to the oxide reliability. During the post-epitaxial growth (cooling down) process and other processing steps, surface pits can form at these dislocation sites. The surface pits cause electric field crowding of the oxides grown on them, leading to degraded oxide reliability. By suppressing the surface-pit formation or by surface planarization prior to thermal oxidation, very good oxide reliability has been achieved, even on the areas which contain dislocations [186]. Another approach to improve the oxide reliability is the usage of deposited oxides. By using an oxide–nitride–oxide (ONO) stack or a deposited oxide nitrided in NO or 
at high temperature, high breakdown fields over 
and very high 
values of 
have been attained [185, 187–189]. The oxide reliability at high temperature is also described in Section 8.2.11. Owing to rapid progress in SiC process technology, the data on oxide reliability is still being updated. Please refer to the latest papers and conference proceedings for the state-of-the-art in this field.
Figure 6.34 Weibull plots of 
for several oxides formed on n-type 4H-SiC(0001) [185].
6.3.3 Structural and Physical Characterization of Thermal Oxides
Structure analyses of the 
interface are not straightforward and several conflicting results have been reported. One main concern is the detection of carbon, which may remain near the interface as well as in the thermal oxide. The density of carbon atoms is usually below the detection limits of XPS and AES. In early SIMS measurements, carbon contamination in thermal oxides in the range of 
was claimed. However, more recently, it has been confirmed that the residual carbon inside the oxides is close to the detection limit of SIMS when the oxides are grown under appropriate conditions, such as at high temperature and an appropriate nitridation process is conducted. The detection of carbon near the interface by SIMS is difficult, because the interface is rather abrupt and the secondary ion yield is very sensitive to the host material. An early EELS analysis suggested that 
carbon exists near the interface [190], but this result has not always been reproduced in recent investigations. More recently, several groups tried careful TEM/EELS studies of 
structures. One group showed a carbon-rich transition layer near the interface [191, 192], while another group claimed that the interface is very abrupt (the thickness of the transition layer is less than 1–2 nm) and that it is hard to detect it by EELS [193]. Figure 6.35 shows (a) a typical cross-sectional TEM image and (b) intensity profiles of Si, C, and O signals in EELS measurements on a 4H-SiC(0001) MOS structure with a 40-nm-thick thermal oxide. The oxide was grown by dry oxidation at 1300 °C. In the TEM image, neither significant disorder nor a thick transition layer is observed. A slightly darker contrast near the interface in the SiC lattice shown in literature originates from a slight “overfocus” in TEM observation, and this does not mean a transition layer. The contrast can be darker or brighter, depending on the focus condition of the TEM. In the intensity profile of EELS (Figure 6.35b), the measurement point was swept normal to the interface with a resolution below 1 nm. All the Si, C, and O signal intensities exhibit a reasonably abrupt change at the interface, and accumulation of C atoms near the interface is not observed within the resolution of EELS. The thickness of a transition layer, even if it exists, is smaller than 2 nm.
Figure 6.35 (a) Typical cross-sectional TEM image and (b) intensity profiles of Si, C, and O signals in EELS measurements on a 4H-SiC(0001) MOS structure with a 40-nm-thick thermal oxide.
The interface structure has also been investigated by high-resolution XPS [194–196], including synchrotron XPS. In these studies, the interface is more abrupt than one expects, and the existence of only a few monolayer sub-oxides is indicated [196]. Spectroscopic ellipsometry measurements suggested that the interface is rather abrupt, with a very thin 
transition layer at the SiC side of the interface [197]. A high-resolution medium energy ion scattering (MEIS) analysis also revealed a fairly abrupt 
interface [198]. It is important to reveal how the interface structure is changed when the oxidation/annealing conditions are varied. Cathodoluminescence (CL) and attenuated-total-reflectance Fourier transform infrared (ATR-FTIR) spectroscopy measurements have been applied to characterize 
structures. In CL measurements, luminescence peaks, which are attributed to oxygen-vacancy centers, were detected at 460 and 490 nm, and some correlation with interface state density was reported [199]. Theoretical studies [200–205] should be linked to experimental investigations to reveal the real microscopic structure of the SiC MOS interface. Furthermore, one must be aware of the limitation of characterization techniques. In normal structural analyses such as XPS, AES, and EELS, the detection limit of foreign elements is not very good (0.3–1% of the host elements). On the other hand, imperfection of 0.1% of the host elements will cause a huge number of electronic defects, which are detectable in electrical characterization.
Regarding the relative dielectric constant of thermal oxides, it has been assumed to be identical to that of thermal oxides grown on Si 
. Figure 6.36 shows the relationship between the equivalent oxide thickness (EOT) and the physical oxide thickness for SiC MOS structures [206]. The EOT and physical thickness were determined by the accumulation capacitance and AFM, respectively. From this plot, the relative dielectric constant of thermal oxides on SiC is estimated to be 3.51. The physical reason for this low value is not clear at present.
Figure 6.36 Relationship between the equivalent oxide thickness (EOT) and the physical oxide thickness for SiC MOS structures ( [206] reproduced with permission from Trans Tech Publications).
6.3.4 Electrical Characterization Techniques and Their Limitations
6.3.4.1 Basic Phenomena Specific to SiC
To assess the quality of MOS interfaces, electrical characterization such as 
and conductance measurements of MOS capacitors is performed. In electrical characterization of SiC MOS capacitors, one has to bear the following points in mind:
- Since the intrinsic carrier density and the carrier generation rate are extremely low at room temperature, no inversion layers are created in normal SiC MOS capacitors. Thus,
curves exhibit “deep depletion”, even in quasi-static (low-frequency) 
measurements, unless illuminated with appropriate light. - Because of its wide bandgap, the majority of interface states are energetically very deep. The emission time constant of electrons from interface states
follows the simple equation [146, 207]:
- where
is the capture cross section, 
the thermal velocity of electrons, 
the effective density of states of the conduction band, and 
the energy of the conduction band edge, 
the Boltzmann constant, and 
the absolute temperature. Figure 6.37 shows the emission time constant from the interface states as a function of the energy level, assuming a capture cross section of 
. For example, the emission time constant of an interface state at 
is as long as 
(about seven days) at room temperature. This means that electrons trapped at such deep states are never emitted to the conduction band and, unless appropriate illumination, or heating is used, stay trapped for the entire measurement period. In other words, such deep states are frozen and do not respond to any probe frequency or voltage sweep rate employed in the measurements. It should be noted that the capture cross section of interface states is strongly dependent on the energy level, and the emission time constant in actual MOS structures does not change as that shown in Figure 6.37. More accurate discussion is described in Section 6.3.4.7.
Figure 6.37 Emission time constant from the interface states as a function of the energy level, assuming a capture cross section of 
([146] reproduced with permission from Wiley-VCH Verlag GmbH).
Note that these situations are similar to the case of Si MOS at very low temperatures (30–77 K) [208, 209].
Figure 6.38 shows the high-frequency (100 kHz) 
curves of MOS capacitors fabricated on (a) n-type and (b) p-type 4H-SiC(0001). Gate oxides, about 40 nm thick, were formed by either dry or wet oxidation at 1200 °C. Post-oxidation annealing (POA) was carried out in Ar at the same temperature for 30 min. In general, a positive shift in 
curves is observed for n-type SiC MOS capacitors, while a negative shift is seen for p-type MOS capacitors. From the voltage shift at the flat band 
, the effective fixed (or oxide) charge density 
can be determined by the following equation [160]:
where 
is the oxide capacitance, and 
and 
are the theoretical and experimental flat-band voltages, respectively. Since carriers trapped at deep interface states are frozen and act as fixed charges at the interface, 
is the sum of real fixed charges (positive or negative) and the charges of trapped carriers (negative (electrons) in n-type and positive (holes) in p-type MOS). This is the reason why this is called the effective fixed charge density. In this particular case (Figure 6.38), the effective fixed charge density is calculated to be 
(negative) for the dry oxide and 
(negative) for the wet oxide on n-type 4H-SiC(0001). In the case of p-type MOS capacitors, the effective fixed charge density is calculated to be 
for the dry oxide and 
(both positive) for the wet oxide.
Figure 6.38 High-frequency (100 kHz) 
curves of MOS capacitors fabricated on (a) n-type and (b) p-type 4H-SiC(0001). About 40 nm-thick gate oxides were formed by either dry or wet oxidation at 1200 °C.
Separation of real fixed charge (positive or negative) and charges of trapped carriers can be achieved by illuminating MOS capacitors with appropriate below-gap light (so-called “photo 
”). Figure 6.39 shows the high-frequency 
curves of a MOS capacitor with a dry oxide on p-type 4H-SiC(0001) [146]. The voltage is first swept from accumulation to deep depletion in darkness. Light from a Xe lamp was then shone on the capacitor while it was held at a bias voltage of 
, leading to formation of an inversion layer. After stabilization the voltage sweep was started. The 
curve exhibits a large hysteresis in the deep depletion region: After light illumination, the 
curve from 0 V to about 
is shifted significantly and approaches the theoretical curve; this change can be attributed to the greatly reduced positive interface charge upon illumination. From the voltage shift in the deep depletion 
, the charge density of holes trapped at deep donor-like interface states can be estimated to be approximately 
. Thus, the majority of interface charges in p-type MOS structures originate from holes trapped at deep interface states, rather than real fixed charges. Note that the density of effective fixed charges (mostly negative in n-type and positive in p-type) is still rather high, 
, even after process optimization [153, 154], and can affect MOSFET characteristics. The effective charges at the oxide (passivation layer)/SiC interface also affect the charge balance in the junction termination region [210].
Figure 6.39 High-frequency 
curves of a MOS capacitor with a dry oxide on p-type 4H-SiC(0001) ( [146] reproduced with permission from Wiley-VCH Verlag GmbH). After the voltage is first swept from accumulation to deep depletion in darkness, light illumination was performed at 
, leading to formation of an inversion layer. After stabilization, the voltage sweep was started toward the accumulation.
In general, ion motion shows a clockwise hysteresis in 
curves of MOS capacitors, while carrier injection (trapping) produces a counterclockwise hysteresis, regardless of the conduction type [160]. 
curves of SiC MOS capacitors, especially on n-type 4H-SiC(0001), often exhibit a carrier-injection-type hysteresis to some extent. The hysteresis depends on the probe frequency, the voltage sweep rate, and the maximum applied voltage during the accumulation [211, 212]. Figure 6.40a shows an example of high-frequency 
curves of a MOS capacitor with a dry oxide on n-type 4H-SiC(0001) [211]. As the maximum bias voltage is increased, the 
curve from accumulation to depletion is shifted toward the positive direction. This result originates from the increase in electron trapping at shallow (but slow) interface states and/or oxide traps near the interface when a higher positive voltage is applied. This phenomenon is markedly pronounced when 
measurements are performed at low temperature, as shown in Figure 6.40b [212]. This is a useful technique to monitor such trapping but is an obstacle for accurate characterization when using 
curves.
Figure 6.40 (a) High-frequency 
curves of a MOS capacitor with a dry oxide on n-type 4H-SiC(0001) ( [211] reproduced with permission from Elsevier). As the maximum bias voltage is increased, the 
curve from accumulation to depletion is shifted toward the positive direction. (b) High-frequency 
curves measured sequentially at low temperature ( [212] reproduced with permission fro Elsevier).
The interface state density can be characterized by several techniques, which possess their own merits and limitations [146, 160, 207]. Several characterization techniques are summarized below.
6.3.4.2 Equivalent Circuit of a MOS Capacitor
Before describing the characterization techniques, an equivalent circuit of a MOS capacitor must be understood. Figure 6.41 shows the equivalent circuits for (a) depletion to weak accumulation and (b) strong accumulation, where 
, and 
are the oxide capacitance, the semiconductor capacitance, the interface-state capacitance, the interface-state conductance, and the series parasitic impedance, respectively. The value of 
is determined for each frequency with an impedance analyzer. In strong accumulation, 
, and 
can be ignored because of the infinitely large 
, and the measured capacitance, and conductance are almost independent of the gate voltage. Under moderately biased conditions, the effects of 
and 
become prominent.
Figure 6.41 Equivalent circuits for (a) depletion to weak accumulation and (b) strong accumulation, where 
, and 
are the oxide capacitance, the semiconductor capacitance, the interface-state capacitance, the interface-state conductance, and the series parasitic impedance, respectively.
6.3.4.3 Determination of the Surface Potential
It is important to accurately determine the surface potential 
, because it determines the energy position of the interface states and is required in all of the characterization techniques described below. The determination of the surface potential is critical for SiC because the interface state density usually exhibits a sharp increase near the band edge, especially on SiC(0001). According to a theory in MOS physics, the surface potential 
can be calculated from the low-frequency 
curves using [160, 207]:
where 
is the low-frequency (usually quasi-static) capacitance and 
is the gate voltage. Here, a certain ambiguity exists in the determination of the integration constant 
. For example, this constant is often determined based on the flat-band capacitance in high-frequency measurements, by assuming that 
(flat band) when the high-frequency capacitance 
equals the ideal flat-band capacitance 
. This is correct only when the high-frequency capacitance does not include any contribution from the interface states. If the probe frequency is not high enough, the flatband capacitance contains a component from the fast interface states, leading to an error in the surface potential. This method results in a relatively large error of 0.06–0.15 eV when a high density of fast interface states exists, as is the case in SiC MOS structures. Some evidence for this is shown in Figure 6.42, where the high-frequency 
curves of a MOS capacitor on n-type 4H-SiC(0001) at various probe frequencies are shown (The influence of parasitic impedance at very high frequency was calibrated). There exists clear frequency dispersion in the 
curves, and the voltage at which the ideal flat-band capacitance 
is obtained clearly depends on the probe frequency. This result suggests that some interface states respond to such high frequency, and that the interface-state capacitance is involved in the high-frequency capacitance.
Figure 6.42 High-frequency 
curves of a MOS capacitor on n-type 4H-SiC(0001) at various probe frequencies (the influence of parasitic impedance at very high frequency was calibrated) [213].
Taking account of the 
and 
values, 
can be determined by using the equivalent circuit shown in Figure 6.41a. On the other hand, the surface potential 
can be obtained using Equation 6.8, except for the integration constant 
. The integration constant 
can be uniquely determined, as shown in Figure 6.43, where 
is plotted against 
. In Figure 6.43, a linear correlation is evident for sufficiently negative 
(in the depletion region). At a sufficiently high frequency, and upon depletion, the interface states do not respond and no inversion carriers are generated at the SiC MOS interface. Therefore, 
can be approximated as the depletion capacitance 
, and a linear relationship can be established between 
and 
[160, 207, 213]:
where 
is the dielectric constant of the semiconductor, 
the donor density, and 
the area of the gate electrode. Based on Equation 6.9, the constant 
can be determined so that extrapolation of the straight line should intersect the origin of the plot, as shown in Figure 6.43 [213]. The donor density is simultaneously determined from the slope of the plot.
Figure 6.43 
versus the surface potential 
. The integration constant 
can be uniquely determined so that extrapolation of the straight line should intersect the origin of the plot [213].
6.3.4.4 Terman Method
In the Terman method, a voltage shift of a high-frequency 
curve from the ideal curve is extracted and then the interface state density is determined for each energy level (surface potential) [160, 207]. This method is based on the assumption that the interface states do not respond to the high frequency and, therefore, the high-frequency capacitance does not include any contribution from the interface states. However, this assumption is usually not valid. Furthermore, the extracted interface state density includes a relatively large error because a slight deviation in the surface potential or doping density results in a large change in the extracted interface state density. Thus, this method has been employed only when the interface state density is extremely high 
, and is not a preferred method to characterize the interface state density.
6.3.4.5 High–Low Method
In the high-low (or often hi–lo) method, the frequency response of interface states is utilized. The essential assumption is that the interface states fully respond to a frequency used for low-frequency 
measurements and do not respond at all to a frequency used for high-frequency 
. If this condition is satisfied, then the low-frequency capacitance includes contributions from all the interface states, while the high-frequency capacitance does not include any interface state contributions. Under this assumption, the interface state density 
is given by [160, 207]
where 
is the 
measured at high frequency and is assumed to be 
(
at high frequency). The low- and high-frequency 
measurements are usually performed in the quasi-static (QS) mode and at between 100 kHz and 1 MHz, respectively. To minimize the voltage shift in 
curves caused by carrier trapping during the accumulation state, “simultaneous high–low” measurements are employed, where the high-frequency and quasi-static capacitances are measured at every bias point before changing the bias voltage. Figure 6.44 shows the typical high-frequency (1 MHz) and quasi-static 
characteristics measured on a MOS capacitor with a dry oxide on n-type 4H-SiC(0001). The larger value of the quasi-static capacitance than the high-frequency capacitance reflects the interface state density. This is a convenient technique to extract the interface state density, because a theoretical 
curve is not necessary and the technique is rather easy. Therefore, the high–low method has been a popular technique to determine the interface state density in many semiconductors, including SiC. However, it must be pointed out that the essential assumption described above is valid only in a very limited range of energy and measurement conditions. Problems that may occur are described below [146, 207, 214]:
- The quasi-static capacitance does not include the capacitance of the interface states
which possess slow emission rates. For example, the interface states located at energy levels deeper than 
or 
exhibit very long emission time constants (roughly 
) at room temperature and do not contribute to the quasi-static capacitance. Therefore, the interface state density in the energetically deep region is severely underestimated (or almost impossible to be monitored). - The high-frequency capacitance may include the capacitance of the interface states which possess fast emission rates. For example, the interface states located at energy levels shallower than
or 
exhibit very short emission time constants (roughly 
) at room temperature and thus contribute to the high-frequency capacitance. It is reported that even deep interface states can respond to a high frequency of 1 MHz at room temperature when the interface is nitrided [215]. Therefore, the interface state density in the energetically shallow region is severely underestimated. This is particularly detrimental in SiC, because a high density of shallow interface states is usually responsible for the low channel mobility. - Another important character of SiC MOS structures is that they can show a large standard deviation of surface potential
and thereby a large dispersion of the time constant [146, 148, 216, 217]. This large dispersion can broaden the frequency range over which the transition from high-frequency to low-frequency behavior takes place. This leads to severe underestimation of the interface state density [214].
Figure 6.44 Typical high-frequency (1 MHz) and quasi-static 
characteristics measured on a MOS capacitor with a dry oxide on n-type 4H-SiC(0001).
Figure 6.45 shows the limitations in the determination of the interface state density by the high–low method [214]. A typical distribution of interface state density and standard deviation of surface potential 
are assumed. In Figure 6.45a, the interface state density deduced from the high(1 MHz)–low(0.5 Hz) method is plotted, together with the assumed distribution. The relative accuracy of the deduced interface state density is shown in the inset. 
versus angular frequency 
at bias points A, B, and C in (a) are shown in Figure 6.45b. The large time-constant dispersion causes a very gradual transition from low- to high-frequency behavior. Thus, there is only a narrow range of energy where the interface state density can be reasonably estimated. The high–low method at room temperature monitors the interface states in a rather narrow energy range within the bandgap, typically between 0.2 and 0.45 eV from the majority carrier band edge; often the range can be even narrower.
Figure 6.45 Limitations in the determination of the interface state density by the high-low method ( [214] reproduced with permission from IEEE). A typical distribution of interface state density and standard deviation of surface potential 
are assumed. (a) Interface state density deduced from the high(1 MHz)–low(0.5 Hz) method is plotted, together with the assumed distribution. (b) 
versus angular frequency 
at bias points A, B, and C denoted in (a).
To improve the accuracy in extraction of the interface state density, the measurements must be performed over a wider temperature range. Low-temperature 
measurements should be used to monitor fast interface states and high-temperature 
measurements to monitor slow states. This approach, however, still does not provide a very satisfactory result, as shown in Figure 6.46 [214]. To characterize shallow or fast interface states more accurately, the high-frequency measurements can be done at a much higher frequency, such as 100 MHz [213].
Figure 6.46 Extracted interface state density versus energy for a typical SiC MOS structure 
at different temperatures ([214] reproduced with permission from IEEE).
6.3.4.6 C–ψs Method
This is a modified version of the high–low method [213]. By using the theoretical capacitance, the high-frequency limit is considerably extended. Using the obtained surface potential, the theoretical semiconductor capacitance 
of n-type MOS capacitor can be calculated by [207, 213]:
assuming that there are no holes in the n-type semiconductor. Figure 6.47 shows the 
values plotted against the surface potential 
measured for an n-type 4H-SiC MOS capacitor at different frequencies, where 
, theory calculated from Equation 6.11 is also plotted. In this particular MOS capacitor, a 32-nm-thick dry oxide was formed on 4H-SiC(0001). The measured 
approached 
as the frequency increased, because the carriers trapped at the interface states hardly respond once the frequency is sufficiently high 
. A definite difference exists between 
at 1 MHz and 
, indicating that a significant portion of the fast interface states respond at 1 MHz. In contrast, 100 MHz seems to be almost sufficient for the interface carriers to not respond (in the case of dry oxides). The interface state density 
is given by:
where 
is 
measured under quasi-static conditions. This method is superior to the other methods from two points of view. (i) The 
method can detect fast interface states almost without frequency limits. (ii) The 
method requires simple measurements (similar to those needed in the high–low method). An almost continuous 
distribution (as opposed to a point by point measurement) can be obtained by this method. However, it is difficult to monitor very slow states, which cannot respond to the voltage sweep; this problem also occurs with the other techniques. Furthermore, this method can result in an erroneous 
distribution when an accurate surface potential cannot be determined. For example, if the doping density varies significantly along the depth, it is difficult to obtain a good plot (such as the one shown in Figure 6.43). In such a case, erroneous surface potentials give a wrong 
curve, leading to an incorrect 
distribution.
Figure 6.47 
values plotted against the surface potential 
measured for an n-type 4H-SiC MOS capacitor at different frequencies, where 
calculated from Equation 6.11 is also plotted [213].
6.3.4.7 Conductance Method
As expected from the equivalent circuit of a MOS capacitor (Figure 6.41), the conductance–frequency 
characteristics of the MOS capacitor should give a peak at a specific frequency, originating from the interface states. The interface state density is related to 
(
: angular frequency) by [160, 207]:
where the interface state density 
, the time constant of the interface states 
, and the standard deviation 
are fitting parameters. And 
, where 
is the surface potential normalized to 
. This technique is regarded as the most sensitive method to determine the interface state density, and a 
of 
can be measured in Si, though this method is time-consuming when compared with 
analyses [207]. All the interface states give definite peaks in 
curves and can be monitored, as long as the inverse of the response time is roughly within the range of the probe frequency (typically from 1 kHz to 10 MHz). However, it is difficult to monitor very slow states, which cannot respond to these frequencies, and very fast states, which show sufficient response to the highest probe frequency, because no conductance peaks appear in these cases. Since there are lower and upper limits of the probe frequency in the conductance measurements, it is important to perform the conductance measurements over a wide range of temperatures. In other words, however, this is one of the advantages of the conductance technique, because it does not provide data under conditions when that data would be invalid (i.e., the observed peaks give valid data).
It should also be noted that other very important information is obtained from the conductance method, namely, the time constant of the interface states and the standard deviation of the surface potential. The time constant is a useful indicator of the nature of the interface states, and the standard deviation reflects the microscopic fluctuations of the interface structure. Both are essential to understanding the low channel mobility in SiC MOSFETs. The time constant for transitions between interface states and the conduction band is given by
where 
is the capture cross section of the state for electrons, 
the thermal velocity, and 
the volume density of electrons at the interface. Given the position 
of the Fermi level at the surface, the electron density is given by
Inserting Equation 6.15 into Equation 6.14 shows that the interface state time constant increases exponentially as the Fermi level moves further from the conduction band. However, it is routinely observed for both Si and 4H-SiC that the capture cross section 
decreases exponentially with energy toward the majority carrier band edge. This exponential dependence can be characterized by a slope factor 
,
where 
is a constant. In Si, the capture cross sections also fall exponentially toward the band edges, but are typically constant near the middle of the bandgap [218]. In 4H-SiC, no clear indication of a constant region been observed. Figure 6.48 shows capture cross sections from several studies, along with the associated 
values [219, 220]. The strong energy dependence in Equation 6.16 tends to cancel the energy dependence in Equation 6.15, making the time constant only weakly dependent on energy. If 
is close to unity, as observed in Figure 6.48, the energy dependence of the time constants becomes very small. In this situation the 
curves shift very little in frequency as the bias is changed, making it possible to obtain data over a wider energy range in the bandgap. This also makes the 
curves narrower [221], so that the apparent surface potential variation 
is less than the true surface potential variation. The apparent 
in 4H-SiC is typically between 4 and 5, so the actual 
is even larger. To date, the true standard deviation of surface potential has not been accurately determined.
Figure 6.48 Capture cross sections of interface states obtained from several studies, along with the associated 
values [219, 220].
Figure 6.49 shows the frequency dependence of 
at various surface potentials for a MOS capacitor with a dry oxide on n-type 4H-SiC(0001). Bell-shaped peaks originate from the interface states, and the bold lines in Figure 6.49 are the 
curves calculated from Equation 6.13 to fit the experimental results. It is noted that these data were acquired by conductance measurements at up to 100 MHz using a special probe. Figure 6.50 shows the 
and 
values obtained from fitting. The time constant is about 
at 
and becomes longer for deeper states, 
at 
. The standard deviation in SiC MOS structures (typically between 4 and 5) is much higher than that in Si MOS structures 
, indicating inhomogeneity of the SiC MOS interface.
Figure 6.49 Frequency dependence of 
at various surface potentials for a MOS capacitor with a dry oxide on n-type 4H-SiC(0001) ([213] reproduced with permission from AIP Publishing LLC).
Figure 6.50 Emission time constant 
(at room temperature) and standard deviation 
of interface states observed for SiC MOS structures ([213] reproduced with permission from AIP Publishing LLC).
Figure 6.51a shows the interface state densities obtained by the high(1 MHz)–low method, the high(100 MHz)–low method, the 
method, and the conductance method, where the 
(
: energy level of interface traps) of the horizontal axis is determined from the surface potential calculated by Equation 6.9 [213]. In the conductance measurements, the highest probe frequency was 100 MHz. All the measurements were performed on the same MOS capacitor with a 32-nm-thick dry oxide formed on n-type 4H-SiC(0001). The 
distribution obtained by the 
method agrees very well with that obtained by the conductance method. The high(100 MHz)–low method also gave the same interface state density, because 100 MHz is almost sufficient for the fast states not to respond. However, the 
distribution obtained by the conventional high(1 MHz)–low method is two or three times lower than that from the other methods, because fast interface states that respond to higher than 1 MHz are not detected. The interface state density of SiC MOS structures is very high, about 
at 
. It should be noted that this underestimation of interface state density by the conventional high(1 MHz)–low method is more severe in nitrided SiC MOS structures [215]. Figure 6.51b shows comparison of 
distributions obtained by several methods for a 4H-SiC(0001) MOS structure annealed in NO. The 
values near the conduction band edge determined by the high(1 MHz)–low method are one-order-of-magnitude lower than those determined by the 
method. Improvement of interface properties is described in Section 6.3.5.
Figure 6.51 (a) Interface state density 
obtained by the high(1 MHz)–low method, the high(100 MHz)–low method, the 
method, and the conductance method. All the measurements were performed on the same MOS capacitor with a 32-nm-thick dry oxide formed on n-type 4H-SiC(0001). (b) Comparison of 
distributions obtained by several methods for a 4H-SiC(0001) MOS structure annealed in NO ([213] reproduced with permission from AIP Publishing LLC).
6.3.4.8 Other Methods
Several other techniques have been applied to characterize the interface properties of SiC MOS structures. The charge pumping method monitors charge emission from the interface states by applying repetitive pulses to the gate [207, 222–224]. Although this technique gives total density of interface states inside the bandgap, it is difficult to accurately determine the energy distribution. A variety of DLTS measurements, such as constant-capacitance deep level transient spectroscopy (CC-DLTS) have been tried [225, 226]. In this technique, carrier emission from interface states, oxide traps, and bulk traps can be distinguished by carefully designed biasing. For example, two oxide traps, energetically located at 
and 
, are detected in n-type 4H-SiC(0001) MOS capacitors by CC-DLTS [226]. However, the energy position of interface states cannot be determined directly and is usually estimated by assuming a constant capture cross section of interface states, except for distinct peaks in CC-DLTS spectra. The situation is very similar in the thermal dielectric relaxation current (TDRC) method [212]. In the Zerbst method a voltage pulse is applied so that a MOS capacitor reaches deep depletion, and the capacitance transient to recover its steady state is monitored. The generation rate via the interface states can be obtained, but it is difficult to determine the 
distribution [160, 227, 228].
As described in Section 6.3.3, no inversion states appear in normal SiC MOS capacitors, even when large gate bias (negative for n-type, positive for p-type) is applied, because of the extremely low generation rate of minority carriers. A gate-controlled diode (GCD) is a test structure, where the inversion layer is induced and, thereby, the interface states near the minority carrier band edge can be characterized. Figure 6.52 shows the terminal connection of a GCD for 
measurements. The basic structure is a planar MOSFET and the gate capacitance is measured by sweeping the gate voltage. In these measurements, the source and drain terminals are connected to the grounded p-base. When sufficiently positive gate bias is applied, electrons are quickly injected from the source and drain, leading to the formation of an inversion layer underneath the gate oxide (in the case of an n-channel MOSFET). Figure 6.53 shows examples of low-frequency (20 Hz) 
characteristics obtained from a 4H-SiC(0001) GCD with a (a) dry oxide followed by wet-annealing and (b) dry oxide annealed in NO [151]. As in the case of Si MOS capacitors at room temperature, the low-frequency 
curve reaches the oxide capacitance 
when the gate voltage is sufficiently larger than the threshold voltage. The high-frequency 
curve exhibits a saturated capacitance determined by the maximum width of the space-charge region (not shown). From the 
curve, the 
distribution near the conduction band edge can be extracted [229]. It is very useful to determine the 
distribution using the MOSFET structure, because direct comparison between the interface properties and the channel mobility is possible on the same sample. However, this method possesses the same limitations as the conventional high–low method, in that both very fast states and very slow states cannot be detected.
Figure 6.52 Terminal connection of a gate-controlled diode (GCD) for 
measurements.
Figure 6.53 Low-frequency (20 Hz) 
characteristics obtained from a 4H-SiC(0001) GCD with a (a) dry oxide followed by wet-annealing and (b) dry oxide annealed in NO ( [151] reproduced with permission from Springer-Verlag).
6.3.5 Properties of the Oxide/SiC Interface and Their Improvement
6.3.5.1 Distribution of Interface States
In spite of the limited capability of characterization techniques described above, a rough picture of the interface state distribution inside the SiC bandgap has been revealed. Figure 6.54 shows schematic distributions of interface states inside the bandgaps of various SiC polytypes. It is known that the energy position of the valence band top is almost aligned for different SiC polytypes and that of the conduction band bottom is scaled according to the individual bandgaps [177].
Figure 6.54 Schematic distributions of interface states inside the bandgaps of various SiC polytypes. (a) Model for explaining a high density of interface state density in SiC and its polytype dependence ([150] reproduced with permission from Springer-Verlag), (b) Schematic distribution of interface states of SiC MOS structures formed by dry or wet oxidation.
When looking at the interface states in the lower half of the bandgap, most of these states are donor-like. These states are positively charged by trapped holes when the states are located above the Fermi level. These donor-like states, especially those located in the deep energy region, capture holes in p-type SiC and do not emit holes at room temperature. Thus, holes trapped at deep interface states behave as if they were “positive fixed charges”. The density of these donor-like states is extremely high 
in MOS structures formed by dry oxidation, and can be remarkably reduced by wet oxidation [230]. These donor-like states do contribute to the negative shift of 
curves for p-type SiC MOS capacitors (and p-channel mobility). However, the donor-like states do not directly affect n-channel mobility, because these states become neutral when the Fermi level moves up [230, 231]. This behavior is common for the various SiC polytypes.
The interface state distribution seems to be intrinsic and common for all SiC polytypes. Thus, the distribution near the conduction band edge is determined by the intrinsic distribution and the location of the conduction band bottom for each polytype, as shown in Figure 6.54. Most of these states near the conduction band edge are acceptor-like. These states are negatively charged by trapped electrons when the states are located below the Fermi level. Electrons trapped at deep acceptor levels act as if they were “negative fixed charges”. Note that the charge neutrality level in SiC MOS structures is not known at present. Furthermore, the existence of donor-like states near the conduction band edge in “nitrided” 4H-SiC MOS structures has been suggested. On 
, the interface state density increases almost exponentially toward the conduction band edge [232–234]. Because of this rapid increment with increasing energy level, the interface state density near the band edge is very high for 4H-SiC(0001) and relatively low for 3C-SiC(111). In n-channel MOSFETs, electrons in the inversion layer induced by the gate bias are trapped at these interface states and become almost immobile. The trapped electrons also act as Coulomb scattering centers. Therefore, the acceptor-like states near the conduction band edge are detrimental to n-channel mobility. This is why 4H-SiC(0001) MOSFETs usually exhibit poor channel mobility (
without appropriate annealing), while high channel mobility (over 
) can be obtained easily for 3C-SiC MOSFETs [235–237].
The exact origins of high interface state density for SiC are not very well understood. In the case of Si MOS structures, dangling bonds at the interface are dominant defects (for example, the 
center) [160, 175]. Since the interface state density of thermal oxide/Si structures is in the 
range, it is unlikely that the high interface state density 
of SiC MOS structures can be attributed simply to dangling bonds. Afanas'ev et al. suggested that the donor-like interface states in the lower half of the bandgap may originate from carbon clusters (carbon-cluster model), based on IPE spectroscopy studies of SiC MOS structures and graphite [147, 238]. Although the role of residual carbon near the interface has been argued, a direct link between the carbon density near the interface and the interface state density has not been proven. The abnormally high interface state density near the conduction band edge of 4H-SiC(0001) is also a mystery. To explain this phenomenon, “near-interface traps” (NITs) were proposed as the origin of the shallow states [147]. NITs are traps existing inside the oxide near the interface and, because of their nature, their response can be very slow. It is also claimed that NITs are intrinsic to 
rather than only to the thermal oxide/SiC system. It is, however, not very easy to explain the experimental facts that a high density of shallow states is not observed in thermal 
[239] and 
[233], and that such shallow states are observed even when other dielectric materials (
, and AlN) are employed. Systematic theoretical studies are required to clarify the origins of the interface states and NITs.
6.3.5.2 Post-Oxidation Annealing
POA and post-metallization annealing (PMA) are crucial to obtain high-quality MOS interfaces in any semiconductor materials. In Si technology, one major technique to reduce the interface state density is hydrogen passivation of dangling bonds near the interface; this can be achieved by PMA in a hydrogen-containing gas, like a 
mixture, at about 400–500 °C [8, 160, 175]. As a result, the interface state density can be reduced down to values as low as 
. In the case of SiC, however, impacts of hydrogen annealing at 400 °C on the interface state density are very small, which suggests that the essential problem in SiC MOS is totally different from that in Si. It has been reported that hydrogen annealing at much higher temperatures, 800–1000 °C, is beneficial to reduce the interface state density [240], but the exact mechanism is not clear.
To reduce deep interface states, especially those lying in the lower half of the bandgap, “re-oxidation” annealing is effective [241]. The key step of this technique is POA at relatively low temperature (typically 950 °C) in a wet ambient in which additional oxidation is negligibly small. After this re-oxidation annealing, the final interface state density seems to be similar irrespective of the oxidation process (dry or wet). The interface properties are also dependent on the 
content in the vapor during re-oxidation annealing. By re-oxidation annealing with a high 
vapor content, the n-channel mobility is improved to 
for 4H-SiC(0001) and 
for 6H-SiC(0001) [242]. As mentioned above, this process also reduces the deep interface state density near the valence band edge, leading to enhancement of p-channel mobility of SiC MOSFETs [243]. The physical reasons for this improvement, however, are still unknown.
Annealing oxides in an inert gas (Ar or 
) immediately after thermal oxidation is a popular process in SiC technology. So far, this inert POA is usually carried out at almost the same temperature as oxidation (1100–1200 °C). This step is believed to aid removal of excess carbon from the oxide or the interface, but no direct evidence for the out-diffusion of carbon has been given. Nevertheless, appropriate Ar POA improves the dielectric properties and reliability of oxides [216], and has been widely employed. In recent years, Ar POA at a very high temperature of 1300–1350 °C was tried to enhance diffusion of excess carbon interstitials based on a deep level study [244]. Although clear reduction in the interface state density, and enhancement of n-channel mobility are attained after high-temperature Ar POA, the improvement is still not satisfactory.
The oxidation condition itself has been investigated to improve the interface quality. As far as the SiC(0001) face is concerned, the oxidation atmosphere (dry versus wet) does not give striking differences in the interface state density near the conduction band edge and, thereby, the n-channel mobility. In general, wet oxidation results in a slightly lower interface state density near the conduction band edge, a significantly lower interface state density near the valence band edge, and improved p-channel mobility, as shown in Figure 6.54. Generation of negative charges near the interface in wet oxidation is also suggested. Note that the effects of wet oxidation become much greater when MOS structures are formed on 
[239] and non-basal planes like 
[233]. High-temperature dry oxidation of SiC(0001) at 1250–1300 °C is effective to reduce the interface state density near the conduction band edge and to improve the n-channel mobility [245, 246]. It has been reported that the interface quality is degraded once the thickness of the thermal oxide exceeds about 20 nm, as shown in Figure 6.55 [196]. In the figure, a sudden increase in interface state density and a change in the slope of the flatband-voltage are observed when the oxide thickness exceeds 20 nm. This degradation of the interface quality is correlated with an increase in the amount of intermediate (suboxide-like) structures, as determined by synchrotron XPS [196]. Despite the various studies described above, we do not at present understand the physical basis for the effects of oxidation.
Figure 6.55 Interface state density and flatband-voltage of n-type 4H-SiC MOS capacitors with dry oxides as a function of the oxide thickness ( [196] reproduced with permission from AIP Publishing LLC).
6.3.5.3 Interface Nitridation
One promising process is post-oxidation nitridation in a nitrogen-containing gas such as nitric oxide (NO) [247–261], nitrous oxide 
[262–264], or ammonia 
[265, 266], or in the presence of nitrogen radicals [267]. Direct oxidation in 
or NO is also proposed. In particular, interface nitridation by NO or 
is widely employed in academic research, as well as in mass production of SiC power MOSFETs. Figure 6.56 shows the distribution of interface state density near the conduction and valence band edges obtained from n- and p-type 4H-SiC(0001) MOS capacitors, respectively [154]. The interface state densities of MOS structures formed by dry oxidation, and dry oxidation followed by nitridation in NO or 
are plotted. In this figure, the interface state density was evaluated by a conventional high (1 MHz)–low method. It is very clear that reduction in the interface state density over the entire range of energies within the bandgap is achieved by nitridation. As a result, the effective mobility of n-channel 4H-SiC(0001) MOSFETs fabricated on lightly-doped p-type epilayers has been enhanced from a single digit 
for dry oxides to 
for 
oxides [262–264], and to 
for NO-nitrided oxides [250, 252, 253]. The effective mobility of p-channel MOSFETs is also improved from 1–
for dry oxides to 
for nitrided oxides [268].
Figure 6.56 Distribution of interface state density near the conduction and valence band edges obtained from n- and p-type 4H-SiC(0001) MOS capacitors, respectively [154].
Annealing in NO or 
naturally results in a pile-up of nitrogen at the 
interface. The nitrogen atom density at the interface depends strongly on the nitridation conditions, and can reach 
or even higher. Correlation between the increase in the nitrogen density at the interface and reduction in the interface state density has been presented by several groups [153, 260, 263]. Furthermore, it has been reported that the nitridation process causes not only reduction of the interface state density near the conduction band edge but also increase in the number of hole traps [269]. Thus, excessive nitridation is not desirable because of pronounced hole-trapping effects. Again, it is unclear how the interface defects are passivated by nitridation. Passivation of dangling bonds with nitrogen or a simple shift of defect levels by nitridation is unlikely, based on the considerations mentioned above. More efficient removal of carbon from the interface by the nitridation annealing has been suggested; there is some experimental evidence supporting this [151, 192, 263].
Comparison between nitridation by NO and that by 
is of interest. Historically, the first reported success in nitridation used NO [247, 249]. Because of the highly toxic nature of NO, 
nitridation, or direct oxidation in 
was proposed as an alternative technique [262]. It seems that nitridation by NO gives a slightly better result than that by 
after process optimization. This result can be qualitatively interpreted by considering the chemical reactions in the gas phase. 
molecules are stable at temperatures below 1100 °C, and start to be decomposed at about 1200 °C according to the following reactions [270]:
Since 
molecules are larger, the diffusion coefficient of 
inside 
must be much lower than those of NO or 
. Therefore, interface nitridation must proceed not by 
itself but by the NO which is created from 
in the gas phase above about 1200 °C. This is consistent with the observation that relatively high temperatures of 1250–1300 °C are required to achieve reasonable nitridation effects using 
. However, when the NO is generated from 
, atomic oxygen or oxygen molecules are also produced and thus must also be present in the gas phase. This means that simultaneous oxidation takes place during interface nitridation by 
. This is supported by the observation that noticeable increase in the oxide thickness is observed after nitridation in 
. On the other hand, NO molecules start to be decomposed at about 1300 °C, according to the following reaction (This decomposition is not desirable.) [271]:
Therefore, significant nitridation can be achieved at a lower temperature of 1150–1250 °C when NO is used, and additional oxidation (increase of oxide thickness) during nitridation in NO is minimal.
It has been found that a high density of very fast interface states is generated near the conduction band edge by nitridation annealing [215]. The very fast states can respond to a probe frequency of 100 MHz or even higher 
at room temperature. Such very fast states cannot be monitored by the conventional high–low method at room temperature, and were characterized by the 
method or conductance measurements at low temperature (40–150 K). Measurements confirmed that the density of such very fast states is low in MOS structures without nitridation annealing, and that the states are indeed created by nitridation in NO or 
. Figure 6.57 shows the density of interface states at 
versus the area density of nitrogen atoms near the interface [215]. These data were acquired from 4H-SiC(0001) MOS structures with dry oxides, that had been annealed in NO at various temperatures (1150–1350 °C). Here, the densities of relatively slow 
states, very fast states 
, and all the states are plotted. The density of slow states decreases with increasing nitrogen density at the interface. In contrast, the density of very fast states increases almost in proportion to the nitrogen area density. Therefore, the very fast states are linked to interface nitridation. As a result, the total interface state density exhibits a minimum at a nitrogen area density of 
, which was obtained by nitridation in NO at 1250 °C for 70 min. When n-channel MOSFETs were fabricated by the same process as that used for the samples characterized in Figure 6.57, the effective channel mobility showed a maximum when the sum of fast and slow interface state density takes a minimum (nitridation in NO at 1250 °C for 70 min). Thus, the very fast interface states are also responsible for limiting the channel mobility. More details are given in Section 6.3.7.
Figure 6.57 Density of interface states at 
versus the area density of nitrogen atoms near the interface ( [215] reproduced with permission from AIP Publishing LLC). These data were acquired from 4H-SiC(0001) MOS structures, with dry oxides, that had been annealed in NO at various temperatures (1150–1350 °C).
6.3.5.4 Other Approaches
Significant reduction of interface state density and improvement of n-channel mobility are achieved by POA in 
[272, 273]. By annealing in 
at 1000 °C for 10 min, a high channel mobility of 
is attained. The mobility can be further improved to 
by two-step annealing in 
at 1000 °C and forming gas at 700 °C [274]; this is one of the highest channel mobilities reported for 4H-SiC(0001) MOSFETs. The phosphorus atoms are almost uniformly distributed with a density in excess of 
inside the gate oxide after the 
annealing. The interface state density and the subthreshold swing of MOSFETs are also significantly improved by the 
annealing.
Another striking technique to enhance the channel mobility is “sodium-contaminated” oxidation [275, 276]. In the initial reports on high channel mobility of 
for 4H-SiC(0001) MOSFETs, an 
tube was used for gate oxidation. It turned out later that the furnace and oxides were highly contaminated with sodium (Na). An accelerated oxidation rate is reported for this Na-contaminated oxidation. Dipping SiC samples in Na-containing solutions prior to normal oxidation in a clean furnace gave very similar results (high oxidation rate and high channel mobility) [277]. This technique cannot be employed for device manufacturing because the processed MOSFETs exhibit clear instability in their threshold voltage, as is also well known in Si technology. It is, however, worth investigating this mechanism in detail to acquire important insights into mobility-limiting factors.
Deposited oxides, followed by appropriate processing, have been investigated with success. The oxide is typically formed by deposition of 
and subsequent annealing in NO or 
[185, 187, 278, 279]. The obtained interface state density is lower and the channel mobility is higher compared with those of thermal oxides annealed in NO or 
. Since the barrier height at the 
interface is smaller than that of a 
system, the tunneling current at high electric field and high temperature is inherently higher in the case of SiC MOS structures, which can limit the oxide reliability at high temperature. In this sense, high-κ dielectrics show definite promise [150]. The physical thickness of gate insulators can be increased while keeping the same gate capacitance, because the material itself has a higher relative dielectric constant. Figure 6.58 shows the relative dielectric constant and bandgap for major high-κ dielectrics. Although 
has been intensively studied in advanced Si MOS, it may not be a good choice for SiC because of the small barrier height at the 
interface. High-κ dielectrics which have relatively large bandgaps, such as 
, AlN, and AlON are attractive for SiC MOSFETs [280–284]. A high channel mobility of 
[281, 283] or a high breakdown electric field of 
has been reported [284].
Figure 6.58 Relative dielectric constant and bandgap for major high-κ dielectrics.
Buried channel structures have been investigated to alleviate the adverse influence of interface states. A thin 
n-type layer is formed by epitaxial growth [285, 286] or ion implantation [287–289] beneath the gate oxide. Since the buried channel is thicker than a normal inversion channel, high channel mobility is obtained, especially at low gate bias. The mobility significantly decreases at high gate bias because the energy band diagram of a MOSFET with a buried channel approaches that of a normal MOSFET at high gate bias, so once again the electron transport is severely affected by the interface states. The thickness and doping density of the channel must be carefully designed to ensure normally-off operation. Even though high peak mobilities of 
have been reported, it is not easy to retain a high threshold voltage at elevated temperature or with a short channel length.
So far, relatively high channel mobilities have been demonstrated for the peak mobility of MOSFETs on lightly-doped p-type SiC epitaxial layers. From a technological point of view, however, it is important to attain high channel mobility in MOSFETs fabricated on moderately-doped 
p-type bodies formed by aluminum implantation. Furthermore, high channel mobility should be obtained at high gate bias (oxide 
).
It should be noted that surface cleaning of SiC prior to thermal oxidation or oxide deposition has not been studied in great detail. A standard cleaning process employed in the SiC community is RCA cleaning followed by a dip in an HF-solution to remove the native oxide [290]. Ozone cleaning [291] and high-temperature hydrogen treatment [292] were also investigated. So far, the essential problems with SiC MOS interfaces are not solved by altering the cleaning process. Nevertheless, fundamental study on surface cleaning of SiC is required for full control of device fabrication.
6.3.5.5 Interface Instability
Though the channel mobility can be improved by several techniques, the instability of the threshold voltage remains a problem, as mentioned earlier. The instability is caused by, at least, two different phenomena; (i) charge injection into the oxide (or carrier trapping at slow states) and (ii) mobile ions. Since there exists a high density of interface states near the conduction band edge and oxide traps in SiC MOS structures, a large positive gate bias induces severe electron injection and trapping, leading to a large positive shift in threshold voltage (or flatband voltage) [212, 293]. Figure 6.59 shows the threshold voltage shift of various 4H-SiC MOSFETs when stressed with a gate oxide field of 
[294]. The threshold voltage shift increases with increasing the bias voltage during the stress. It is of interest that the 
gate ramp used to measure the gate characteristics gives a much larger threshold voltage instability than the measurements with a 1-s-long gate ramp. These results can be interpreted by electron tunneling in and out of near-interface oxide traps [294]. As shown in Figure 6.59, MOSFETs with nitrided gate oxides exhibit an improved instability. More recently, another type of instability was found. When a negative gate bias is applied, the threshold voltage exhibits a significant negative shift and a stretch-out of the gate characteristics [295]. This shift is pronounced at elevated temperature. This instability is attributed to hole trapping near the MOS interface under a negative gate bias. Since interface nitridation creates more hole traps [269], optimization of the nitridation process is crucial.
Figure 6.59 Threshold voltage shift of various 4H-SiC MOSFETs when stressed with a gate oxide field of 
( [294] reproduced with permission from IEEE). (a) Program of a bias-stress test, (b) threshold voltage shift as a function of bias-stress time for various MOSFETs.
Another instability is so-called bias-temperature instability, which is often observed in SiC MOS structures [296–298]. This phenomenon is caused by mobile ions; positive mobile ions accumulate at the 
interface under positive bias-temperature 
stress (PBTS), and result in a negative shift of the threshold voltage (or flatband voltage); conversely, positive mobile ions accumulate at the 
interface under negative bias-temperature stress (NBTS), leading to a positive shift in threshold voltage. Thus, 
curves exhibit an ion-drift-type hysteresis. Annealing in a hydrogen-containing gas, such as forming gas, at high temperature 
results in enhanced bias-temperature instability [298].
6.3.6 Interface Properties of Oxide/SiC on Various Faces
The densities and distributions of interface states are very different when different crystal faces (other than off-axis 4H-SiC(0001)) are employed. The major crystal faces described here are off-axis 
, on-axis 
, and 
.
In SiC 
, 
, and 
MOS structures, the atmosphere used for oxidation gives striking differences in the distribution of interface states near the conduction band edge. Figure 6.60 shows the interface state density distributions obtained from n-type 4H-SiC(0001), 
, 
, and 
MOS structures prepared by (a) dry and (b) wet oxidation. Here, the interface state density is evaluated by the conventional high(1 MHz)–low method. On 4H-SiC(0001), the interface state density near the conduction band edge is not very sensitive to the oxidation conditions (dry/wet). On the other faces, dry oxidation results in very high interface state density, while much lower interface state density can be obtained using wet oxidation (or by POA in the presence of water vapor) [239, 299]. It is reported that the effects of hydrogen annealing at 800–900 °C are much larger on 
[239] and 
[300]. Another important result in Figure 6.60 is the lack of sharp increase in interface state density toward the conduction band edge for these non-standard faces. In other words, the distributions of interface states are rather flat on 
, 
, and 
. High mobilities of 
on (000
) [239] and 
on 
[300–302] have been achieved.
Figure 6.60 Interface state density distributions obtained from n-type 4H-SiC(0001), 
, 
, and 
MOS structures prepared by (a) dry and (b) wet oxidation.
Post-oxidation nitridation or direct oxidation in a nitrogen-containing gas is also effective in reduction of interface state density on 
, 
, and 
[263, 303, 304]. Figure 6.61 shows the interface state density distributions obtained from n-type 4H-SiC(0001), 
, 
, and 
MOS structures prepared by dry oxidation and subsequent nitridation in NO. In spite of dry oxidation, the interface state density is drastically reduced by nitridation in NO (or 
). Again, the distributions of interface states are rather flat on 
, 
, and 
. Note that the interface state density near the valence band edge can be also decreased by nitridation of the interface [268].
Figure 6.61 Interface state density distributions obtained from n-type 4H-SiC(0001), 
, 
, and 
MOS structures prepared by dry oxidation and subsequent nitridation in NO.
Figure 6.62 shows the field-effect mobility as a function of the gate voltage of n-channel MOSFETs fabricated on 4H-SiC(0001), 
, 
, and 
[304]. About 40-nm-thick oxides were grown by dry oxidation, and subsequent nitridation was performed in a 
atmosphere at 1250 °C. The obtained channel mobility is reasonably high, 
, on 
, and very high, 
, on 
and 
. The latter result is promising for development of trench MOSFETs on SiC(0001) wafers [305, 306]. The effects of the tilt angle on the channel mobility of 4H-SiC MOSFETs with 
and 
sidewalls have also been investigated [307].
Figure 6.62 Field-effect mobility as a function of the gate voltage of n-channel MOSFETs fabricated on 4H-SiC(0001), 
, 
, and 
[304]. About 40-nm-thick oxides were grown by dry oxidation, and subsequent nitridation was performed in a 
atmosphere at 1250 °C.
6.3.7 Mobility-Limiting Factors
The physical reason for low channel mobility of SiC MOSFETs has been debated. In Si MOSFETs, the main factors limiting the channel mobility are the fixed charge and surface roughness [308], because the interface state density in Si MOS structures formed by adequate processes is low enough not to limit channel mobility. In SiC MOSFETs, Coulomb scattering had often been proposed as the main limiting factor. This is because the channel mobility of 4H-SiC(0001) MOSFETs usually shows a positive temperature coefficient (increases at elevated temperature). However, this is a misleading interpretation, and thermally activated transport or electron localization in inversion layers [148, 309, 310] are more likely to be responsible. In recent years, deeper insights have been provided based on a few careful investigations. One can also see a detailed description of channel mobility in Section 8.2.10.
The channel mobility (n-channel) in the linear region is usually estimated from the following equations [311]:
Here 
and 
are the drain current and drain voltage, respectively. 
and 
are the channel length and the channel width, respectively. In these estimates, it is assumed that all the electrons in the inversion layer are mobile, traveling in the conduction band from the source to the drain. In other words, the sheet electron density in the inversion layer, 
, is approximately given by 
, where 
is the oxide capacitance, 
the gate voltage, and 
the threshold voltage. However, the interface state density in SiC MOS structures is so high that the integrated density of interface states can be of the same order as the induced sheet electron density 
. Electrons trapped at the interface states must be almost immobile. If 90% of induced electrons are trapped, for example, only 10% of induced electrons can travel and contribute to the drain current. Even if the mobile electrons drift with a mobility of 
, the overall channel mobility is calculated as 
, according to Equation 6.20 or 6.21. In this circumstance, more and more electrons are excited to the conduction band and become mobile with increasing temperature. As a result, the calculated channel mobility exhibits a positive temperature coefficient. In this case “Coulomb scattering” is a misleading explanation for the mobility-limiting factor. A more correct term is “electron trapping effect”. Therefore, the temperature dependence of field-effect mobility or effective mobility calculated from Equation 6.20 or 6.21 does not give clear insight into the scattering mechanisms involved in carrier transport.
As described above, the total density of induced electrons 
is given by:
where 
and 
are the densities of mobile electrons and of electrons trapped at interface states, respectively. The real mobility of mobile electrons 
and the calculated mobility 
are linked by the following equation:
The real mobility of mobile electrons in the conduction band can be obtained by MOS-Hall effect measurements [152, 260, 312, 313]. Figure 6.63 shows the typical pattern configuration for Hall effect measurements of a MOSFET. A long channel region is formed and three or four additional terminals are made for Hall effect measurements. In MOS-Hall effect measurements, not only the real mobility, but also the real mobile electron density 
, can be determined. Since the total density of induced electrons 
is calculated as 
, the degree of electron trapping 
can be estimated. In a different manner, the field-effect mobility 
can be expressed as [313]:
Here 
is the trapped charge density, 
the total charge in the inversion layer, 
the interface state density at a Fermi level 
, and 
the differential capacitance of the inversion layer. Thus, the estimated channel mobility is much smaller than the real value when 
because of electron trapping. If the interface state density increases rapidly near the band edge, as is the case for SiC(0001), this trapping effect applies for almost the whole range of gate bias. It is reported, however, that the trapping effect is not very significant after recent optimization of the nitridation process [260].
Figure 6.63 Typical pattern configuration for Hall effect measurements of a MOSFET.
Figure 6.64 shows examples of real mobility (as a function of gate bias) determined by MOS-Hall effect measurements on an n-channel (a) 6H- and (b) 4H-SiC(0001) MOSFETs [152, 312]. There exists a certain discrepancy between the Hall mobility and the calculated effective channel mobility, and the degree of electron trapping can be estimated to be about 30–50% for 6H-SiC and 70–85% for 4H-SiC MOSFETs. By MOS-Hall effect measurements, the sheet density of mobile carriers can be directly determined as a function of gate bias. Therefore, this is a powerful technique to investigate carrier transport in SiC MOSFETs.
Figure 6.64 Examples of real mobility (as a function of gate bias) determined by MOS-Hall effect measurements on an n-channel (a) 6H- and (b) 4H-SiC(0001) MOSFETs ( [152, 312] reproduced with permission from Springer Verlag). The effective mobility is also shown.
In SiC MOSFETs, one often observes a negative correlation between the channel mobility and the threshold voltage determined by linear extrapolation of the transfer characteristics. The channel mobility decreases when the threshold voltage increases in MOSFETs, the oxides of which were formed by the same process but under slightly different conditions (e.g., nitridation at different temperatures or for different periods). This phenomenon is partly attributable to a problem in determining the threshold voltage and can be interpreted by considering the electron trapping, as shown schematically in Figure 6.65. As the interface state density near the conduction band increases, more and more of the electrons induced by the gate bias are trapped at the interface. This leads to a decrease in drain current as well as the gradual (not abrupt) increase near the threshold. Thus, the threshold voltage becomes artificially high when determined by linear extrapolation.
Figure 6.65 Schematic illustration of a problem of electron trapping in determining the threshold voltage of n-channel SiC MOSFETs. (a) Degradation of gate characteristics due to a high density of interface states, (b) major limiting factors of channel mobility in SiC MOSFETs.
When the interface state density is very high, one can see a clear correlation between the n-channel mobility and the interface state density near the conduction band edge [151–154, 229, 314]. However, there is still debate about what the main mobility-limiting factor is once the interface state density has been reduced by nitridation or wet re-oxidation. For example, on SiC(0001), the interface state density at 
can be reduced from mid 
to low 
(as evaluated by the high–low method) by appropriate nitridation, but the resulting n-channel mobility is 
, which corresponds to only 3–5% of the bulk mobility. Figure 6.66 shows the n-channel mobility versus the interface state density at 
determined by (a) the high (1 MHz)–low method and (b) the 
method. The data were obtained from 4H-SiC MOSFETs and MOS capacitors processed under various conditions. In Figure 6.66a, there exists large scatter, though a correlation is observed to some extent. For example, at an interface state density of about 
, the channel mobility of one MOSFET on (0001) is 
and the other is 
. Furthermore, the MOSFET on 
with a similar interface state density is as high as 
. It is hard to explain this mobility difference simply by the difference in surface roughness between two crystal faces. In addition, the improvement of channel mobility in MOSFETs on (0001) is not very significant (only a factor of 10), in spite of the remarkable reduction of interface state density by process optimization (a factor of 100). On the other hand, a very clear trend can be seen in Figure 6.66b, where the slope of the plot is nearly 
. This result indicates the following:
- The n-channel mobility is still limited mainly by very high interface state density, even after recent process optimization.
- Very fast interface states, which can be detected by the
method (not detectable by the high(1 MHz)–low method) affect the channel mobility.
Figure 6.66 n-channel mobility versus the interface state density at 
determined by (a) the high (1 MHz)–low method and (b) the 
method.
In general, SiC MOSFETs exhibit poor subthreshold slopes, 200–500 mV/decade, much larger than the ideal value, approximately 60 mV/decade at room temperature. The poor subthreshold slope can be reproduced well using the distribution of interface state density determined by the 
method. Figure 6.67 depicts the correlation between the interface state densities determined from 
data of MOS capacitors and those from the subthreshold slope of MOSFETs. The interface state densities determined from the subthreshold slope are much higher than those determined by the high(1 MHz)–low method (Figure 6.67a), which was a mystery in this field. However, the interface state densities determined by the 
method show good agreement with those obtained from the subthreshold slope, as shown in Figure 6.67b. This result indicates that fast interface states indeed affect the performance of MOSFETs.
Figure 6.67 Interface state density estimated from the subthreshold slope of MOSFET versus The density at 
determined by (a) the high (1 MHz)–low method and (b) the 
method.
However, the mechanism of channel conduction in SiC MOSFETs must be much more complicated. In SiC, the surface roughness is much larger compared with that of Si because of the use of off-axis 
wafers and immature surface preparation technology. The roughness scattering may be prominent when the interface state density is further reduced. This is especially important at high gate bias, where real MOS devices operate. The influence of real (not effective) fixed charge on the channel mobility has not yet been clarified.
Another possible problem is the large fluctuation of surface potential, as indicated by the conductance measurements [216]. Since the interface structure of SiC MOS structures can be highly inhomogeneous, the surface potential can fluctuate inside the MOS channel. Thus the total conduction in the inversion layer may be limited by microscopic regions where the conductivity is greatly suppressed by the fluctuation. Furthermore, recent defect studies indicate that excess carbon atoms are emitted from the oxidation interface into the SiC bulk region during thermal oxidation [157] and form defect levels near the conduction and valence band edges [315, 316]. Ab initio calculation has predicted that interstitial carbon dimers are formed in the presence of carbon interstitials in SiC, and that these carbon dimers form a shallow acceptor level at 
[317]. Thus, the bulk mobility just near the interface may be severely affected by such defects. Figure 6.68 shows the charge transition levels of various possible defects near the 
interface predicted by a hybrid-density function theory [318]. According to this study, 
and 
defects may be responsible for the levels near the conduction band edge of 4H-SiC. However, more fundamental studies are required to reveal the nature of interface defects and carrier transport properties in the inversion layers.
Figure 6.68 Charge transition levels of various possible defects near the 
interface predicted by a hybrid-density function theory ([318] reproduced with permission from American Physical Society).