After epitaxial growth of SiC several processing steps are performed to fabricate electronic devices. Such processing steps include doping by ion implantation, etching, oxidation, and metallization. Figure 6.1 shows a schematic of a trench-type vertical metal-oxide-semiconductor field-effect transistor (MOSFET). The contribution of each individual process to the complete structure can be seen. The process flow in SiC device fabrication is similar to that in Si technology, but several unique technologies, with particular requirements, are also needed because of the unique physical and chemical properties of SiC.
Ion implantation is a key process in fabrication of almost all kinds of SiC devices. Wide-range doping control of both n- and p-type conductivity can be achieved by ion implantation. The major differences between ion implantation technologies for SiC and for Si are summarized as follows:
One can find review papers and books on ion implantation into SiC [1–6]. In this section, common features observed in ion implantation of SiC are described.
In Si and most III–V semiconductors both diffusion and ion implantation techniques are employed for selective doping. In general, a diffusion process introduces less lattice damage than ion implantation, in which bombardment with high-energy ions creates a variety of point and extended defects in the host material. Formation of deep junctions is easier in a diffusion process when the diffusion constant of a dopant is relatively large. On the other hand, a more flexible and accurate doping profile can be formed by ion implantation. The thermal budget is generally smaller in ion implantation because post-implantation annealing can be conducted in a rapid thermal process (RTP) [7].
Examples of selective doping in the fabrication of SiC devices are summarized in Table 6.1, where the typical doping densities and junction depths are indicated. In SiC, because of its very strong chemical bonding, diffusion constants of dopant impurities are extremely small, even above 1600 °C. Figure 6.2 shows the Arrhenius plot of diffusion constants for major dopants in SiC and Si [8, 9]. Diffusion constants for atoms other than boron are very small in SiC, ranging from to at temperatures as high as 1800 °C. Extremely high temperature, above 2000 °C, is required to obtain reasonable diffusion constants. This fact makes diffusion processing of SiC unrealistic because such a high-temperature process causes generation of a high density of deep levels [10] and glide of basal-plane dislocations [11]. There exist no appropriate masking materials for a diffusion process at such high temperature. Therefore, selective doping of SiC has almost exclusively been performed using ion implantation. However, diffusion mechanisms of small impurities like hydrogen should be investigated [12] because SiC epitaxial layers grown by chemical vapor deposition (CVD) contain some hydrogen atoms. Furthermore, it is known that several transition metals, such as chromium (Cr) and nickel (Ni), exhibit significant diffusion above 1500 °C [13]. Although boron diffusion for p-type doping has been investigated to some extent [14, 15], a high density of boron-related deep levels (D center [16]) is generated, which hampers good electrical activation of boron acceptors. In fact, the tail of the boron-diffused region is highly resistive, which is not suitable for pn junctions of real devices. Abnormal diffusion of boron atoms, which is also encountered in boron ion implantation [6], is another problem.
Table 6.1 Examples of selective doping in fabrication of SiC devices.
Region | ||
Source/drain | 0.2–0.3 | |
p-body of FET | 0.4–0.7 | |
contact | 0.2–0.3 | |
Junction termination | 0.4–0.8 | |
Channel doping (optional) | 0.1–0.2 |
Nitrogen or phosphorus ions are implanted to selectively form n-type regions in SiC. The implant profiles can be predicted well by Monte Carlo simulations, such as SRIM (stopping and range of ions in matter) [17]. Figure 6.3 shows depth profiles of the density of nitrogen atoms implanted into SiC(0001) with various implant angle [18]. In this particular case, the implant energy and dose are 100 keV and , respectively. The open circles denote the nitrogen depth profile simulated by a SRIM code, assuming a mass density of for SiC. The dashed and dotted lines represent the depth profiles determined by secondary ion mass spectrometry (SIMS) in samples implanted at various angles (with respect to <0001>). Here, a channeling effect can be suppressed by increasing the implantation angle to 7°. Ideally, the implantation angle should be larger than 5° from the axis (not normal to the wafer surface). Note that SRIM does not simulate channeling of the implanted ions accurately, leading to deviation in the implant-tail region. Implant profiles can also be designed using the Pearson distribution [19]. In the Pearson distribution an asymmetric Gaussian distribution is considered, and characterized by the projected range (mean), the straggle (standard deviation), the skewness, and kurtosis [19]. Figure 6.4 shows the projected mean range and straggle versus the implant energy in nitrogen and phosphorus ion implantation into SiC [20–23]. Because of the higher atom density of SiC ([Si]: , [C]: , total: ), a higher implant energy is required to obtain a given depth or peak position compared with the energy required for ion implantation into Si.
Figure 6.5 shows the depth profiles of phosphorus atoms which were implanted with multistep energies to form a 200-nm-deep box profile. The depth profiles before (as-implanted) and after annealing in Ar at 1600 °C for 30 min are presented. The dopant profile exhibits very little diffusion during such high-temperature annealing, retaining the as-implanted profile. This is expected from the very small diffusion constants of phosphorus (also for nitrogen as shown in Figure 6.2), and any enhancement of impurity diffusion via implantation-induced defects is negligible. The lack of dopant diffusion makes it relatively easy to form a shallow junction, but difficult to form a very deep junction, in SiC.
Figure 6.6 shows typical sample structures employed for electrical characterization of implanted regions. In Figure 6.6a, the cross-section of a sample for van der Pauw and Hall effect measurements is illustrated. The implanted n-type layer is electrically isolated from the substrate by the np junction (n-type implanted layer/lightly-doped p-type epitaxial layer). The implanted region is processed into a clover-leaf pattern to improve the accuracy. By using this kind of sample the sheet resistance, the carrier density, and the mobility can be determined. In another type of test sample, a Schottky barrier is formed on the top of the implanted n-type layer, as shown in Figure 6.6b. In this case, electrical isolation is not necessary, and the implantation is conducted into a lightly-doped n-type epitaxial layer grown on an n-type substrate. From the capacitance–voltage characteristics, the depth profile of the net doping density (not the carrier density) is determined. This method is powerful when the doping density is relatively low because analysis of the deep levels can be performed on the same samples. For characterization of high-dose implanted samples, however, this technique is not very useful because formation of good Schottky barriers becomes difficult. For characterization of aluminum- or boron-implanted samples, the n- and p-type regions in Figure 6.6 should be inverted.
Figure 6.7 shows the annealing-temperature dependence of the electrical activation ratio in nitrogen- or phosphorus-implanted SiC. In this case, a box profile with a depth of about 400 nm was formed by multi-step ion implantation, and the total implant dose was , which corresponds to a dopant atom density of inside the box profile. The implantation was conducted into lightly-doped n-type epitaxial layers without intentional sample heating, and the samples were annealed at various temperatures in Ar for 30 min to promote electrical activation. The active donor density was determined by capacitance–voltage characteristics of Ni/SiC Schottky structures. It should be noted that the measurements do not give the carrier density but rather the net doping density, as further described in Section 6.4.1. As shown in Figure 6.7, the activation ratio is very low after annealing at 1400 °C, and a high-temperature annealing at 1600 °C or higher is required to obtain nearly perfect activation ratios. Note that the annealing temperature cannot be reduced very much, even if the implantation is performed at elevated temperatures (300–800 °C). In other words, hot implantation is not very effective to reduce the temperature required for post-implantation annealing. This can be understood by considering the thermal stability of the compensating deep levels generated by ion implantation, as described in Section 6.1.6.
When the implant dose becomes high , the situation is significantly changed. Striking differences are observed between room-temperature implantation and hot implantation, and also between nitrogen implantation and phosphorus implantation. This is especially true when, to improve contact characteristics, heavily-doped are formed by ion implantation, as described below.
Figure 6.8 shows the value determined by Rutherford backscattering spectrometry (RBS) channeling measurements as a function of the implant dose. The results are obtained from SiC(0001) samples implanted with nitrogen ions at (a) room temperature and (b) 500 °C. The values for both as-implanted and 1600 °C-annealed samples are shown (200-nm-deep box profile) [5]. In these RBS measurements, a beam was employed with a backscattering angle of 170°. The lattice damage is monitored by the so-called value, which is the integrated scattering yield in the damaged region of a channeling spectrum divided by the integrated yield of a random spectrum. In the case of implantation at room temperature, the value from the implanted region reaches almost 100%, indicating complete amorphization by implantation-induced damage, when the implant dose is higher than (this is called the critical implant dose for amorphization). The high value is not decreased very much after annealing at 1600 °C ( in Figure 6.8a). In contrast, the value remains rather low for an as-grown sample implanted at elevated temperature, owing to the in situ annealing effect, and it decreases significantly with further annealing ( in Figure 6.8b). Transmission electron microscope (TEM) observations and other structural analyses demonstrate that the surface region is indeed amorphous for as-implanted samples after room-temperature implantation, and the implanted region contains polycrystalline 3C-SiC grains after annealing [24–28].
The damage accumulation during ion implantation is approximately proportional to the implant dose until complete amorphization occurs [29]. When the implant dose is low, disordering of the carbon sub-lattice proceeds at a higher rate than for the silicon sub-lattice, as a result of the lower threshold-displacement energies for carbon atoms. However, amorphization of the carbon and silicon sub-lattices occurs at almost the same implant dose [30]. In the case of hot implantation, the implanted region can retain the original polytype structure and can be easily recovered. Very similar results are obtained for phosphorus, aluminum, and boron ion implantation. Therefore, this is a consistent and unique feature of ion implantation into hexagonal SiC polytypes. Because of the complicated polytypism and low stacking-fault energy in SiC, it is important to maintain the original crystalline structure during ion implantation [5, 6, 31–34]. Once the implanted region becomes completely amorphous, as a result of high-dose implantation, lattice recovery to the original polytype is not guaranteed. This is the main reason why hot implantation of SiC is employed, especially when the implant dose is high. The critical implant dose, above which the implanted region becomes amorphous, is approximately low to mid for room-temperature implantation, though it depends on the implanted species and implant energy. It should be noted that the benefits of hot implantation are small when the implant dose is relatively low and thus the implanted region is not severely damaged. For example, hot implantation is not always necessary when the implant dose is in the range of (and below), which is further supported by the data on electrical properties.
Figure 6.9 shows the sheet resistance versus the total implant dose for nitrogen- or phosphorus-implanted 4H-SiC(0001) annealed at 1700 °C for 30 min [35]. Multistep implantation at room temperature or 500 °C was performed to form a 200-nm-deep box profile. Here, high-dose implantation to form an is considered. The sheet resistance is usually measured by the van der Pauw method. When the implant dose is relatively low , there exist no striking differences in sheet resistances, irrespective of implant species or implantation temperature (RT or 500 °C). In the case of room temperature implantation, the sheet resistance exhibits a minimum value at an implant dose of approximately , and increases when the implant dose is further increased. In this high-dose region, the lattice damage caused by room temperature implantation is so severe that the implanted region contains a high density of stacking faults and 3C-SiC grains after activation annealing, as described above. On the other hand, a continuous decrease in the sheet resistance is observed for hot implantation. The sheet resistance of the nitrogen-implanted region is almost saturated at , which may be limited by the relatively low solubility limit of nitrogen atoms in SiC. A much lower sheet resistance of can be obtained by hot implantation of phosphorus owing to its higher solubility limit [35–37]. It is reported that high-dose arsenic ion implantation also gives a low sheet resistance, below [38]. Systematic data on nitrogen or phosphorus implantation into SiC are found in a number of papers [39–46]. The obtained sheet resistance is low enough for most device fabrication. It is noteworthy that very good lattice recovery and high activation ratio are obtained, even in high-dose implantation at room temperature, when is employed [47]. To increase the process throughput and to minimize formation of extended defects, rapid thermal annealing using a high-power infrared lamp [48] or microwave heating [49] has been investigated.
Based on these results, phosphorus implantation at elevated temperature is preferred when a heavily-doped must be formed. For formation of a moderately-doped n-region, selection of the implant species and implantation temperature is not critical.
Aluminum is the main acceptor used in SiC, and the situation is the same in ion implantation. As described below, boron implantation can cause several unwanted phenomena and is not usually employed for device fabrication in industry. As in the case of n-type doping, the implant profiles (apart from the tail region) can be predicted well by a SRIM code. Figure 6.10 presents (a) the implant profiles of aluminum ion implantation and (b) the projected range and straggle versus the implant energy for aluminum and boron ion implantation into SiC [20–23]. As was found for nitrogen or phosphorus ion implantation, implanted aluminum atoms exhibit very little diffusion, even after high-temperature annealing at 1600–1700 °C. Implanted boron atoms, however, show significant out-diffusion and in-diffusion during the activation annealing [6, 50]. As a result of the out-diffusion, some portion of the implanted boron atoms is lost; the in-diffusion makes the junction depth extremely large compared with the designed depth. It has been accepted that diffusion of boron atoms is enhanced by implantation-induced damage via a kick-out mechanism [51, 52]. Boron interstitials created by implantation have a large diffusion constant, and can diffuse already at 1400–1500 °C. Damage-enhanced diffusion is also observed in boron-doped epitaxial layers. When any kind of ion is implanted into boron-doped epilayers, the boron atoms show abnormal diffusion during subsequent annealing at 1600–1800 °C [53], this diffusion means that the designed depth profile of acceptor density is completely destroyed. Thus, boron is not a good choice, even when producing p-type epitaxial layers for device development.
Figure 6.11 depicts the annealing-temperature dependence of the electrical activation ratio in aluminum- or boron-implanted SiC [54]. A 400-nm-deep box profile was formed by multistep ion implantation, and the total implant dose was , which corresponds to a dopant atom density of inside the box profile. The implantation was conducted into lightly-doped p-type epitaxial layers at room temperature, followed by activation annealing at various temperatures in Ar for 30 min. The electrically active acceptor density was determined from the characteristics of Ti/SiC Schottky structures. The implanted region is highly resistive after annealing at temperatures lower than 1400 °C. High-temperature annealing at 1600 °C or higher is required to obtain nearly perfect activation ratios, in agreement with the results of nitrogen or phosphorus ion implantation (Figure 6.7). Rapid thermal annealing has also been investigated [55].
High-temperature annealing is indeed required, not only for high electrical activation, but also for good junction characteristics in device fabrication [56–58]. Figure 6.12 shows the histograms of leakage current density in 4H-SiC pn junction diodes annealed at various temperatures. Lightly-doped n-type epitaxial layers, thick, were prepared, and pn junctions were formed by implantation. The leakage current was monitored at a reverse voltage of 500 V. Though the breakdown voltage of these diodes was about 1400 V, exhibiting very little dependence on the annealing temperature, the distribution of leakage current is clearly dependent on the annealing temperature, as shown in Figure 6.12. The leakage current is rather high for the diodes annealed at 1550 °C, and it is significantly reduced in diodes which were formed by activation annealing at 1700 °C or higher.
Figure 6.13 shows the depth profiles of (a) aluminum and (b) boron atoms, which were implanted with multistep energies to form a 200-nm-deep box profile [59]. The depth profiles before (as-implanted) and after annealing in Ar at 1700 °C for 1 or 30 min are presented in both cases. In the figure, the depth profile of electrically active acceptor density is also plotted (the symbols). The depth profile of acceptor density was determined from the characteristics of the Ti/SiC Schottky structure measured at different bias voltages. In this experiment, lightly-doped p-type epilayers were employed to investigate the activation ratio in the implant tail region [59]. In aluminum ion implantation (Figure 6.13a), the implanted aluminum profile does not change during annealing (that is, the aluminum atoms exhibit very little diffusion) and the depth profile of acceptor density completely matches that of implanted atom density determined by SIMS. This result indicates that the electrical activation of implanted aluminum atoms is nearly perfect inside the box-profile region as well as in the tail region. In boron ion implantation (Figure 6.13b), however, substantial out- and in-diffusion are observed, as mentioned above. The depth profile of active acceptor density shows a clear dip near the implant tail region , though the activation ratio is relatively high in the deeper region. Analysis of the defects using deep level transient spectroscopy (DLTS) measurements revealed that a high density of D centers is generated near the tail region [59]. Although carbon co-implantation is effective to reduce the abnormal diffusion of boron atoms and generation of D centers [6, 50, 60], the suppression is not complete. Furthermore, the high ionization energy of boron acceptors hampers the formation of low-resistance p-type SiC by boron implantation [6, 60, 61].
Figure 6.14 shows the sheet resistance versus the total implant dose for aluminum-implanted 4H-SiC(0001) annealed at 1800 °C for 30 min [62]. Multistep implantation at room temperature or 500 °C was performed to form a 200-nm-deep box profile. Here, high-dose implantation to form a is considered. As in the case of nitrogen or phosphorus implantation, effects of hot implantation become remarkable when the implant dose is higher than . For hot implantation, the sheet resistance of the aluminum-implanted region is almost saturated at approximately . Carbon co-implantation gives a slightly lower sheet resistance, probably because carbon enrichment may enhance substitution of implanted aluminum atoms at the Si sites. The relatively high sheet resistance can be partly ascribed to the low hole mobility in SiC. The intrinsic mobility is further decreased by implantation-induced defects. Detailed characterization is found in the literature [63–67]. Although ion implantation of gallium [68] and beryllium [69] into SiC has been investigated for obtaining p-type conductivity, the obtained sheet resistances are relatively high because of the high ionization energy of the dopants.
Thus, aluminum implantation at elevated temperature is required when a heavily-doped must be formed. However, the resistivity of aluminum-implanted regions is still relatively high, and this must be carefully considered in design and characterization of SiC devices. To form a moderately-doped p-region, aluminum implantation at room temperature followed by high-temperature annealing is sufficient.
There are two different approaches to form semi-insulating regions by ion implantation. The first approach is creation of intrinsic defects, which form a very deep level in the bandgap, by ion bombardment. The second approach is implantation of a special impurity which forms a very deep level. In the former case, either protons [70, 71] or inert atoms, such as helium, neon, or argon [72], or the host element (silicon or carbon) [73] ions have been investigated. When a high enough density of deep levels has been created, the dopants are completely compensated and the Fermi level is pinned near a dominant deep level. A high resistivity of over is obtained when these ions are implanted into n-type 4H- or 6H-SiC. The semi-insulating property is maintained after high-temperature annealing when the implant dose is high. The dominant deep level(s) generated by ion implantation are described in Section 6.1.6.
It is known that a few metallic impurities form very deep levels in SiC and the most widely-used impurity for this purpose is vanadium [74]. Vanadium doping is also effective in producing semi-insulating SiC wafers in sublimation growth [75], as described in Section 3.4.4. Therefore, vanadium ion implantation is another approach to obtain semi-insulating SiC. Figure 6.15 shows the current density–voltage characteristics of vanadium-implanted (a) and (b) 6H-SiC structures [76]. In either case, vanadium ions were implanted into lightly-doped epitaxial layers to form a 300-nm-deep box profile. The vanadium density in the box profile is approximately , which is higher than the doping density of the epitaxial layers and lower than the solubility limit of vanadium . After post-implantation annealing at 1500 °C for 30 min, implanted vanadium atoms were electrically activated, and the resistivity of the implanted region increased to for n-type and over for p-type SiC. Vanadium creates an acceptor-like level at in n-type and a donor-like level at in p-type 6H-SiC [74]. Because of the deeper energy level of vanadium in p-type SiC, the Fermi level is pinned near the midgap in vanadium-implanted p-type SiC, leading to the higher resistivity.
Though ion implantation is useful to selectively form semi-insulating regions, the depth of the semi-insulating region formed in this way is restricted to less than about . If a very thick semi-insulating region is required then electron irradiation is a more powerful technique. 200–400 keV electron irradiation can create semi-insulating regions that are several tens of microns thick [77]. The semi-insulating property is stable even after high-temperature annealing at 1700 °C when the electron fluence is high enough.
As described in previous subsections, post-implantation annealing must be carried out at very high temperatures of 1600–1700 °C to achieve reasonable lattice recovery and high electrical activation. The annealing temperature cannot be reduced, even if the implantation is conducted at elevated temperatures of 500–1000 °C. One of the main reasons for this is the thermal stability of several deep levels which are generated by ion implantation and cause compensation of dopants.
During high-temperature annealing one can usually observe surface degradation of SiC. Without special precautions the mirror-like surface is completely lost during annealing [78]. There are at least two mechanisms which cause surface degradation:
Si desorption leads to surface graphitization as well as severe roughening. This is naturally enhanced when SiC is annealed in vacuum (significant Si desorption in vacuum can already start at 900–1000 °C, even for unimplanted SiC surfaces). In the early stage, supply of Si overpressure was investigated with some success. For example, addition of flow into pure Ar ambient or introduction of Si pieces near the SiC samples during annealing was tried, and improvement of surface roughness was demonstrated [79, 80]. It is, however, difficult to suppress the second mechanism mentioned below with this technique.
Migration of surface atoms at high temperature can take place in Si [81] and any other materials. The main driving force for surface migration is minimization of the surface energy of the crystal. In the case of hexagonal SiC polytypes, a several-degree off-angle is chosen for the SiC(0001) wafers to enable high-quality homoepitaxy. Since the SiC(0001) has a relatively high surface energy, significant migration of surface atoms occurs at high temperature and results in formation of macrosteps to minimize the total surface energy. Capping the surface with an appropriate material effectively suppresses this phenomenon because the surface atoms lose the freedom to migrate. Proper capping is also useful to minimize Si desorption from the SiC surface. So far, several capping materials have been investigated, such as , , AlN [82], and carbon [35]. A SiC face-to-face configuration was also investigated. Among these materials, a carbon cap gives the most successful results [35] and is employed for production of SiC devices in most industries.
Figure 6.16 shows the atomic force microscopy (AFM) images of off-axis 4H SiC(0001) annealed at 1800 °C for 5 min (a) with and (b) without a carbon cap. The total implant dose is . The surface roughness, as defined by the root mean square value of height deviation, is 1.0 nm in a area for the sample capped with carbon, while the unprotected sample exhibits a much higher surface roughness , because of macrostep formation. Figure 6.17 depicts the implant-dose dependence of the surface roughness for SiC(0001) annealed at 1700 °C for 20 min with and without a carbon cap. When the surface is not protected, the roughness increases significantly with increasing implant dose. Higher-dose implantation creates more broken bonds and more atoms can migrate at lower temperature (that is, the migration barrier is reduced by implantation-induced damage). In contrast, the surface roughness can be minimized by using a carbon cap, even for high-dose implantation. The carbon cap can be formed by RF sputtering or graphitization of a photoresist. During high-temperature annealing, no chemical reactions are observed at the carbon/SiC interface. After annealing, the carbon cap can be easily removed by plasma (ashing) or low-temperature (700–800 °C) oxidation; in these processes, the SiC is only minimally oxidized (less than a few nanometers).
High-energy ion bombardment during ion implantation causes considerable displacement of Si and C atoms. Si and C atoms are kicked out from their lattice positions, and the kicked-out atoms reside to a large extent on interstitial sites, leaving vacancies behind. In SiC, C displacement occurs more easily than Si displacement. Created vacancies and interstitials become mobile during post-implantation annealing and can form complex point defects, such as vacancy clusters, interstitial clusters, antisite-vacancy pairs, and so forth. The profile of interstitial and vacancy densities generated by ion implantation can be estimated by an SRIM code. The vacancies, interstitials and antisites can also combine with implanted impurities or dopant atoms in the host material. All these point defects can create localized levels (shallow or deep levels) in the bandgap. Furthermore, the density of generated point defects is so high that they often segregate inside the implanted region during annealing, leading to formation of extended defects, such as dislocation loops and stacking faults. Since the activation annealing is carried out at high temperature, additional stress can be introduced in the material, leading to generation of new dislocations and/or movement of pre-existing dislocations.
The shallow and deep levels generated by ion-implantation processes have been investigated in detail [83–86]. Figure 6.18 shows the DLTS spectra obtained from (a) n-type and (b) p-type 4H-SiC epitaxial layers [86]. Here, implantation was conducted at room temperature, followed by annealing at 1700 °C for 20 min. The total implant dose is low, , which corresponds to an impurity density of about . Therefore, the samples retain their original conduction type (n or p) after implantation. The major deep levels generated by the implantation are [83], EH6/7 center [87], and HK4 center [88]. It should be noted that these deep levels are commonly observed in 4H-SiC samples implanted with any kinds of ions, such as , , , , and . Furthermore, the density of generated deep levels can exceed that of implanted ions. These results indicate that these major deep levels generated by low-dose ion implantation originate from intrinsic defects, which do not contain a specific impurity.
Figure 6.19 shows the depth profiles of the density of centers in , , , and 4H-SiC [86]. In the ion implantation, an 800-nm-deep box profile, indicated by a dashed line in the figure, was formed by multistep implantation of all ion species. The center density inside the box profile is higher than the density of implanted ions and the depth profile extends much further into the sample than the implantation tail. Since the center works as a carrier lifetime killer, as described in Section 5.3.2, this is one of the main reasons why pn junctions formed by ion implantation exhibit higher on-resistance and faster switching speed than epitaxial pn junctions [89, 90]. The high density of centers can be reduced by a factor of 10–30 if appropriate thermal oxidation is performed after activation annealing [91].
Figure 6.20 depicts the DLTS spectra obtained from (a) n-type and (b) p-type 4H-SiC epitaxial layers [86]. The total implant dose is relatively high in this case, , which corresponds to an impurity density of about . The implantation was carried out at room temperature, and subsequent annealing was done at 1700 °C for 20 min. DLTS spectra consist of several overlapping peaks, indicating that various deep levels with similar energies exist. The total density of observed deep levels reaches low , which corresponds to about 3–10% of the implanted atom density. Thus, these levels work as carrier-trapping centers, increasing the resistance of the implanted regions. Thermal oxidation can also substantially reduce these deep levels, indicating that these defects contain a carbon vacancy [91].
Extended defects in implanted SiC have been investigated by TEM and X-ray topography [92–95]. Figure 6.21 shows a typical cross-sectional TEM image taken from implanted 4H-SiC [93]. implantation (total implant dose: ) was performed at room temperature, followed by annealing at 1700 °C for 30 min. Inside the implanted region, one can observe a high density of small dark areas. Although the density and size of dark areas depend on the implant dose, annealing temperature, and also implanted species, these are common features of TEM observations of implanted SiC.
Figure 6.22 shows the high-resolution cross-sectional TEM image of 6H-SiC [93]. Note that a similar structure is always observed when the dark areas shown in Figure 6.21 are magnified. There exists an extrinsic stacking fault (extra plane) in a basal plane, and a Frank-type partial dislocation is observed at the edge of the stacking fault. Furthermore, basal planes are distorted around both ends of the stacking fault. Figure 6.23 shows the implant-dose dependence of the number of atoms existing in the extra planes generated by ion implantation and annealing [93]. It is striking that the total number of atoms in the extra planes is proportional to the implant dose, and the absolute number is almost identical to that of the number of implanted ions. This result suggests that Si and C atoms kicked out by ion bombardment become mobile and segregate in the basal planes during annealing, leading to formation of extra planes. Furthermore, high-dose implanted regions exhibit a lattice tilt with respect to the original c-axis [96]. Figure 6.24 shows the reciprocal space mapping (RSM) images for the (0008) reflection of 4H-SiC with a phosphorus density of (a) , (b) , and (c) atoms . Post-implantation annealing is performed at 1800 °C for 10 min. In the RSM images taken from high-dose implanted samples, two distinct reflection peaks, originating from the implanted layer and the epitaxial layer, respectively, are observed. These images reveal an increase in the c-lattice constant (decrease in ) of the implanted layers. Furthermore, the peaks from the implanted layers are located at slightly different values , indicating the lattice tilt. The tilt angle increases with increasing implant dose, and the tilt direction is always along the upstream side of the off-direction, irrespective of the implanted species [96]. These kinds of extended defects, of course, affect the carrier transport in the implanted regions [97, 98].
During high-temperature activation annealing, new dislocations can be generated from the surface, and glide motion of pre-existing dislocations is also observed in SiC. Figure 6.25 shows a schematic illustration of typical phenomena observed in implanted SiC annealed at 1600–1800 °C [11, 99]. (i) A new dislocation half-loop is introduced in a basal plane from the surface. The bottom of this dislocation half-loop is often located at the implanted region/epilayer interface. (ii) Pre-existing basal-plane dislocations can migrate (glide motion) near the surface as well as near the epilayer/substrate interface, which results in formation of interface dislocations. Furthermore, (iii) Shockley-type stacking faults can be formed near the surface (not shown). Regarding (i) and (ii), misfit stress (caused by a large difference in dopant density) and thermal stress may be driving forces for dislocation nucleation or glide motion [100]. By improving the temperature gradient inside the annealing furnace, the glide of pre-existing basal-plane dislocations can be suppressed [101].
SiC is an extremely inert material against chemical solvents and wet etching of SiC is very difficult. SiC single crystals are attacked by neither acids nor alkali solutions at room temperature. Reactive ion etching (RIE) is widely employed to form mesa structures and trenches in SiC. A few review papers on dry etching of SiC have been published [102, 103]. Gas etching at high temperature can be useful for some applications.
RIE of SiC is relatively easy, and commercial RIE systems developed for Si and other semiconductors can be used for etching SiC. Neither a very special etching gas nor high temperature is required for RIE of SiC, though the etching rates are relatively low compared with those of Si. In RIE, active radicals generated in a plasma diffuse toward the SiC surface and induce chemical etching. Positive ions are accelerated in a plasma sheath and ion bombardment onto the SiC surface induces physical etching. Capacitively-coupled plasma reactive ion etching (CCP-RIE) [104–111], inductively-coupled plasma reactive ion etching (ICP-RIE) [112–116], and electron cyclotron resonance (ECR) plasma [117–120] etching of SiC have been investigated.
Etching gas systems can be categorized into (i) fluorine-based, (ii) chlorine-based, and (iii) bromine-based gases as follows:
or Ar is often added to enhance removal of carbon atoms or to increase active species, especially in fluorine-based chemistry. The control of carbon removal is the main difference between the RIE of SiC and that of Si. Regarding the etching rate, fluorine-based chemistries generally give higher rates. In dry etching of SiC, the dominant mechanism is determined by the volatility of the reaction by-products and the energy of the ionized species. In practice, this translates into choices of the etching gases, the plasma pressure, and the bias voltage (or power) of the sample electrode [121]. Table 6.2 shows the boiling points of potential etch products in SiC RIE using fluorine- or chlorine-based chemistries. The fluorinated products are more volatile than the chlorinated ones, which may be one reason why higher etching rates are obtained with fluorine-based chemistries. Figure 6.26 shows the etching rate versus the gas composition in CCP-RIE with various fluorinated gas mixtures (a) without and (b) with additive [110]. Etching of SiC by gives a high etching rate, though is a toxic gas. Addition of promotes the etching, while the presence of results in decreased etching rate. Note that almost the same etching rates are obtained on (0001) and faces.
Table 6.2 Boiling points of potential etch products in SiC RIE using fluorine- or chlorine-based chemistries.
Etching product | CO | |||||
Boiling point ( °C) | 58 | 77 |
The etching rate of SiC can usually be increased with high-density plasma sources, such as ICP, helicon plasma, or ECR plasma. In particular, ICP-RIE offers an attractive etching technique, because the generation of high-density plasma and the RF bias to the samples (ion energy) can be independently controlled [121]. Figure 6.27 shows the etching rate of SiC as a function of self-bias power in ICP-RIE with a system. The self-bias is a critical parameter, which determines the etching rate. By increasing the self-bias power, the etching is significantly enhanced, although it causes more surface damage. It has been reported that several deep levels are generated by RIE processes in n- and p-type SiC [122]. These defects can be generated at depths up to a few microns and affect the doping concentration, especially in p-type SiC. The densities of most of these deep levels can be reduced by more than 1 order of magnitude via thermal oxidation [122]. Exact surface reactions during RIE of SiC are not known and basic study of the etching mechanism is strongly desired.
Although dry etching of SiC itself is easy, obtaining high selectivity against a masking material is a challenge. Table 6.3 summarizes typical selectivities of SiC etching against that of various masking materials. Photoresist, which is often employed in RIE of Si, is not a good choice, because of very low selectivity. This is inevitable, because the etching gases and conditions for RIE of SiC have been adjusted to promote carbon etching. A high selectivity (over 10) is easily obtained by using metals, such as Al, Ni, or Cr, as the mask. However, nonvolatile by-products such as are formed during RIE, and small particles of these materials can be adsorbed on the surface. These particles work as a “micromask” and pillar-like hillocks are formed, leading to considerable surface roughening. This phenomenon is well known in the RIE of Si and other semiconductors [121]. By using a graphite plate on the cathode electrode, the micromasking effect can be greatly reduced [106]. The micromasking effect can also be reduced by adding a flow, because the supply promotes formation of volatile , which effectively removes Al particles sputtered from the Al mask or the reactor walls [108, 110, 115]. One drawback of this process is degradation of the etching selectivity. In real device fabrication in industry, metallic contamination should be minimized throughout device processing. Therefore, metal masks are not usually employed in the fabrication of SiC devices. A common masking material in the RIE of SiC is deposited by CVD. By using slightly oxygen-rich conditions, or by increasing the self-bias, the selectivity of SiC against can be increased to 5–10 or even higher.
Table 6.3 Typical selectivity of SiC etching against various masking materials.
Mask | ITO | Al | Ni | Photoresist | |
F-based RIE | 0.8–3 | 10–20 | 5–30 | ||
Cl-based RIE | 4–15 | 3–10 | 2–10 | — |
Control of etching profiles is as important as etching rates and selectivity. Figure 6.28 shows examples of etched SiC, as observed by a scanning electron microscope (SEM). In Figure 6.28a, a trench with an aspect ratio of 3 was formed by ICP-RIE with a mask [123], where the angle of the side walls is about 85°. In Figure 6.28b, a mesa structure with a rounded bottom was formed by CCP-RIE [124]. This structure was formed by using a mask, which was etched by a wet process. The rounded shape formed by the wet etching was transferred to SiC by RIE with a relatively low-selectivity condition. This mesa structure can be applied to an edge termination combined with implanted junction termination extension [124]. Furthermore, mesa structures with a very shallow bevel angle, which are also useful as termination structures, can be formed by using a thick photoresist baked at high temperature as an etching mask [125]. Dry etching is widely employed to fabricate SiC microelectromechanical systems (MEMSs) [126–128].
Thus, RIE processes of SiC have been developed to some extent but the etching mechanism is still not fully understood. The improvement of etching selectivity and reduction of surface roughness (of both the etched SiC surface and trench/mesa sidewalls) are remaining issues.
Gas etching of SiC at high temperature has been investigated since the 1960s. Typical gases employed for etching are [129–131], [132–134] and [135, 136]. Figure 6.29 shows Arrhenius plots of the etching rate of SiC by [131], [134], and [136]. It is reported that is effective to obtain a very high etching rate [137]. Etching with or is routinely employed as in situ etching of substrates prior to epitaxial growth. At 1500 °C, the etching rate is about for and for , though the etching rate also depends on the process pressure. These etching processes give very flat surfaces, with periodic step-terrace structures formed on off-axis [130, 134]. On the other hand, the etching rate by is about on (0001) and on at 1000 °C. However, this etching process leads to relatively large etch pits at dislocation sites on the (0001) face. Although high-temperature gas etching will not be employed as a main etching process (for formation of mesa or trench structures) in SiC device fabrication, it may be very effective in obtaining smooth side-walls of trenches [123, 136].
SiC can be etched by molten KOH, NaOH, or at 450–600 °C. In these melts, SiC is oxidized and the formed oxide is subsequently removed by the melt [138]. However, this etching process usually creates dislocation pits or hillocks on the surface, as described in Section 5.1.5. Severe contamination from K or Na must be avoided in subsequent device processing, especially in oxidation.
SiC can be etched by electrochemical (or photoelectrochemical) etching. In these etching processes, holes must be supplied to the surface to induce oxidation. Therefore, p-type SiC can be selectively etched in electrochemical etching, when the sample is correctly biased, but etching of n-type SiC is suppressed because of the lack of holes [139, 140]. On the other hand, selective etching of n-type SiC is possible under illumination of above-bandgap photons. Under this illumination, photo-generated holes are accumulated at the electrolyte/n-type SiC interface as a result of surface band bending, leading to oxidation and subsequent etching of the oxide by the solution [141–145]. Since holes are depleted at the electrolyte/p-type SiC interface, p-type SiC is not etched in this process. Although this etching selectivity (n-type versus p-type) is of interest, these etching processes are not very suitable for fabrication of electronic devices. Major disadvantages include a fairly rough etched surface, the inability to pattern small-dimension features, and poor etching uniformity across entire wafers.