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25.1 Introduction and Overview
25.6 Line-Commutated Inverters
25.1 Introduction and Overview
Inverters are used to create single or poly-phase AC voltages from a DC supply. The DC supply is typically created by rectification of AC voltage from the utility power grid with due consideration of harmonics and input power factor. In the class of poly-phase inverters, three-phase inverters are by far the largest group. A very large number of inverters are used for adjustable speed motor drives for motors ranging from fractional hp (horsepower) to several 100 hp. Considering that more than 50% of all the electricity generated in the United States is used to drive electric motors [25, Figure 8.3], the importance of this application cannot be overstated. The typical inverter for motor drives is a “hard-switched” voltage source inverter producing pulse-width modulated (PWM) signals with a sinusoidal fundamental [11]. For large motors, multilevel inverters [19,24] are used, which are described in more detail later. Recently, research has confirmed and explained several detrimental effects such as electrical breakdown and excessive mechanical wear on motor windings and bearings respectively, resulting from unfiltered PWM waveforms from voltage source inverters. To avoid these detrimental effects, especially in the case of long cable runs between the inverter and the motor, voltage filters on the inverter outputs [8,21] can be used. Multilevel inverters besides their larger voltage and power ratings also inherently avoid this problem.
A very common application for single-phase inverters is a so-called uninterruptible power supply (UPS) for computers and other critical loads. Here the output waveforms range from square waves to almost ideal sinusoids. UPS designs are classified as either “off-line” or “online.” An off-line UPS will connect the load to the utility for most of the time and quickly switch over to the inverter if the utility fails. An online UPS will always feed the load from the inverter and switch the supply of the DC bus instead. Since the DC bus is heavily buffered with capacitors, the load sees virtually no disturbance if the power fails.
In addition to the very common hard-switched inverters, active research is being conducted on “softswitching” techniques [26]. Hard-switched inverters use controllable power semiconductors to connect an output terminal to a stable DC bus. On the other hand, soft-switching inverters have an oscillating intermediate circuit and attempt to open and close the power switches under zero-voltage and or zero-current conditions.
A separate class of inverters are the line-commutated inverters for multimegawatt power ratings that use thyristors (also called silicon controlled rectifiers [SCRs]). SCRs can only be turned “on” on command. After being turned on, the current in the device must approach zero in order for the device to turn off. All other inverters are self commutated, meaning that the power control devices can be turned on and off on command. Line-commutated inverters need the presence of a stable utility voltage to function. They are used for DC links between utilities, ultra-long distance energy transport, and very large motor drives including drives for large ships [1,2,14,16,18]. However, the technology for very large motor drives is more and more shifting to modern hard-switched inverters including multilevel inverters [7,19].
Modern inverters use isolated gate bipolar transistors (IGBTs) as the main power control devices [14]. Besides IGBTs, power MOSFETs are also used especially for lower voltages and power ratings and applications that require high efficiency and high switching frequency. In recent years, IGBTs, MOSFETs and their control and protection circuitry have made remarkable progress. IGBTs are now available with voltage ratings of 6500 V and current ratings up to 2400 A. MOSFETs have achieved on-state resistances approaching a few milliohms. In addition to the devices, manufacturers today offer customized control circuitry that provides for electrical isolation, proper operation of the devices under normal operating conditions and protection from a variety of fault conditions [14]. In addition, the industry provides good support for specialized passive devices such as capacitors and mechanical components such as low inductance bus-bar assemblies to facilitate the design of reliable inverters. In addition to the aforementioned inverters, a large number of special topologies are used. A good overview is given in Ref. [10].
Inverters fall in the class of power electronics circuits. The most widely accepted definition of a power electronics circuit is that the circuit is actually processing electric energy rather than information. The actual power level is not very important for the classification of a circuit as a power electronics circuit. One of the most important performance considerations of power electronics circuits like inverters is their energy conversion efficiency. The most important reason for demanding high efficiency is the problem of removing large amounts of heat from the power devices. Of course, the judicious use of energy is also paramount, especially if the inverter is fed from batteries such as in electric cars. For these reasons, inverters operate the power devices, which control the flow of energy, as switches. In the case of an ideal switching event, there would be no power loss in the switch since either the current in the switch is zero (switch open) or the voltage across the switch is zero (switch closed) and the power loss is computed as the product of both. In reality, there are two mechanisms that do create some losses, however, which are on-state losses and switching losses [3,12,14,16]. On-state losses are due to the fact that the voltage across the switch in the on state is not zero, but typically in the range of 1–3 V for IGBTs. For power MOSFETs, the on-state voltage is often in the same range, but it can be substantially below 0.5 V due to the fact that these devices have a purely resistive conduction channel and no fixed minimum saturation voltage like bipolar junction devices (IGBTs). The switching losses are the second major loss mechanism and are due to the fact that, during the turn on and turn off transition, current is flowing while voltage is present across the device. In order to minimize the switching losses, the individual transitions have to be rapid (tens to hundreds of nanoseconds) and the maximum switching frequency (determining the frequency of transitions) needs to be carefully considered.
In order to avoid audible noise being radiated from motor windings or transformers, many modern inverters operate at switching frequencies substantially above 10 kHz [4,6].
Figure 25.1 shows the basic topology of a full bridge inverter with single-phase output. This configuration is often called an H-bridge due to the arrangement of the power switches and the load. The inverter can deliver and accept both real and reactive power. The inverter has two legs, left and right. Each leg consists of two power control devices (here IGBTs) connected in series. The load is connected between the mid-points of the two-phase legs. Each power control device has a diode connected in anti-parallel to it. The diodes provide an alternate path for the load current if the power switches are turned off. For example, if the lower IGBT in the left leg is conducting and carrying current toward the negative DC bus, this current would “commutate” into the diode across the upper IGBT of the left leg, if the lower IGBT is turned off. Control of the circuit is accomplished by varying the turn on time of the upper and lower IGBT of each inverter leg, with the provision of never turning on both at the same time, to avoid a short circuit of the DC bus. In fact, modern drivers will not allow this to happen, even if the controller would erroneously command both devices to be turned on. The controller will therefore alternate the turn on commands for the upper and lower switch, that is, turn the upper switch on and the lower switch off and vice versa. The driver circuit will typically add some additional blanking time (typically 500–1000 ns) during the switch transitions to avoid any overlap in the conduction intervals.
FIGURE 25.1 Topology of a single-phase, full bridge inverter.
The controller will hereby control the duty cycle of the conduction phase of the switches. The average potential of the center-point of each leg will be given by the DC bus voltage multiplied by the duty cycle of the upper switch, if the negative side of the DC bus is used as a reference. If this duty cycle is modulated with a sinusoidal signal with a frequency that is much smaller than the switching frequency, the short-term average of the center-point potential will follow the modulation signal. “Short-term” in this context means a small fraction of the period of the fundamental output frequency to be produced by the inverter. For the single-phase inverter, the modulation of the two legs is inverse of each other such that if the left leg has a large duty cycle for the upper switch, the right leg has a small one, etc. The output voltage is then given by Equation 25.1 in which ma is the modulation factor. The boundaries for ma are for linear modulation—values greater than 1 cause over-modulation and a noticeable increase in output voltage distortion:
(25.1) |
This voltage can be filtered using an LC low-pass filter. The voltage on the output of the filter will closely resemble the shape and frequency of the modulation signal. This means that the frequency, wave-shape, and amplitude of the inverter output voltage can all be controlled as long as the switching frequency is at least 25–100 times higher than the fundamental output frequency of the inverter [11]. The actual generation of the PWM signals is mostly done using micro-controllers and digital signal processors (DSPs) [5].
Figure 25.2 shows a three-phase inverter, the most widely used topology in today’s motor drives. The circuit is basically an extension of the H-bridge style single-phase inverter by an additional leg. The control strategy is similar to the control of the single-phase inverter, except that the reference signals for the different legs have a phase shift of 120° instead of 180° for the single-phase inverter. Due to this phase shift, the odd triplen harmonics (3rd, 9th, 15th, etc.) of the reference waveform for each leg are eliminated from the line-to-line output voltage [14,17]. The even-numbered harmonics are canceled as well if the output voltages are purely AC, which is usually the case. For linear modulation, the amplitude of the AC output voltage is reduced with respect to the AC input voltage of a three-phase rectifier feeding the DC bus by a factor given by the following equation:
(25.2) |
FIGURE 25.2 Topology of a three-phase inverter.
To compensate for this voltage reduction, the amplitudes of the output voltages are sometimes boosted by intentionally injecting a third harmonic component into the reference waveform of each phase leg [14]. These third harmonic components cancel in the line-to-line output voltage that is applied to the motor.
Figure 25.3 shows the typical output of a three-phase inverter during a startup transient into a typical motor load. This figure was created using circuit simulation. The upper graph shows the PWM waveform between phases A and B whereas the lower graph shows the currents in all three phases. It is obvious that the motor acts a low-pass filter for the applied PWM voltage and the current assumes the wave-shape of the fundamental modulation signal with very small amounts of switching ripple.
Like the single-phase inverter based on the H-bridge topology, the inverter can deliver and accept both real and reactive power. In many cases the DC bus is fed by a diode rectifier from the utility, which cannot pass power back to the AC input. The topology of such a three-phase rectifier would be the same as shown in Figure 25.2 with all IGBTs deleted.
A reversal of power flow in an inverter with a rectifier front end would lead to a steady rise of the DC bus voltage beyond permissible levels. If the power flow to the load is only reversing for brief periods of time, such as to brake a motor occasionally, the DC bus voltage could be limited by dissipating the power in a so-called brake resistor. To accommodate a brake resistor, inverter modules with an additional seventh IGBT (called “brake chopper”) are offered. This is shown in Figure 25.4. For long-term regeneration, the rectifier can be replaced by an additional three-phase inverter [14]. This additional inverter is often called a controlled synchronous rectifier. The additional inverter including its controller is of course much more expensive than a simple rectifier, but with this arrangement bidirectional power flow can be achieved. In addition, the interface toward the utility system can be managed such that the real and reactive power that is drawn from or delivered to the utility can be independently controlled. Also the harmonics content of the current in the utility link can be reduced to almost zero. The topology for an arrangement like this is shown in Figure 25.5.
FIGURE 25.3 Typical waveforms of inverter voltages and currents.
FIGURE 25.4 Topology of a three-phase inverter with brake chopper IGBT.
The inverter shown in Figure 25.2 provides a three-phase voltage without a neutral point. A fourth leg can be added to provide a four-wire system with a neutral point. Likewise 4-, 5-, or n-phase inverters can be realized by simply adding the appropriate number of phase legs.
Like in single-phase inverters, the generation of the PWM control signals is done using modern micro-controllers and DSPs. These digital controllers are typically not only controlling just the inverter, but through the controlled synthesis of the appropriate voltages, motors and attached loads are also controlled for high performance dynamic response. The most commonly used control principle for superior dynamic response is called field-oriented or vector control [5,6,9,13,20].
FIGURE 25.5 Topology of a three-phase inverter system for bidirectional power flow.
Multilevel inverters are a class of inverters where a DC source with several tabs between the positive and negative terminal or multiple isolated DC sources are present. The two main advantages of multilevel inverters are the much higher voltage and power capability and the reduced harmonics content of the output waveform due to the multiple DC levels. The higher voltage capability is due to the fact that clamping diodes are used to limit the nominal voltage stress on the IGBTs to the voltage differential between two tabs on the DC bus. In the case of cascaded H-Bridge converters, the voltage stress on each H-Bridge is limited to the level of the isolated DC source, which makes the topology completely modular with no theoretical voltage (and power) limit.
Figure 25.6 shows the topology of a three-level, three-phase inverter, which is also called “neutral point clamped” inverter. Here each phase leg consists of four IGBTs in series with additional anti-parallel and clamping diodes. The output is at the center-point of the phase leg. By switching on IGBT pairs 1 and 2, 2 and 3, or 3 and 4, respectively, the output of each phase can be connected to the top DC bus, the center connection of the DC supply, or the negative DC bus. This amounts to three distinct voltage levels for the voltage of each phase, which explains the name of the circuit. It turns out that the resulting line-to-line voltage has five distinct levels in a three-phase inverter. In each case, the nominal voltage stress on the IGBTs in the off state amounts to half the voltage between the positive and the negative rail.
Another inverter topology which inherently limits the voltage stress on the IGBTs to the DC-bus voltages of the individual H-Bridges is shown in Figure 25.7. Inverters that are based on this basic principle of cascaded H-bridges enable the synthesis of very high-quality output voltage waveforms with large numbers of individual voltage levels. Shown in the following are two possible examples of an almost limitless number of possible variations.
The schematic shown in Figure 25.7 represents one phase of a multiphase topology. The hardware configuration of the additional phases is identical. This inverter is called an asymmetric cascaded H-bridge inverter because the individual H-bridges have unequal DC bus voltages [22]. Symmetric cascaded inverters with identical DC bus voltages are also being used. The specific advantage of asymmetric inverters is the large number of voltage levels relative to the number of modules. For this example, the DC bus voltages of the stages have a ratio of 1:2:4 starting from the top stage. The output of each H-bridge can have three distinct values:
FIGURE 25.6 Topology of a three-level inverter.
FIGURE 25.7 Topology of a three-stage, asymmetric cascaded H-bridge inverter.
• Positive DC bus voltage
• Negative DC bus voltage
• Zero
Therefore, with the topology shown in Figure 25.7, the maximum positive and negative output voltage of the entire cascade 1 + 2 + 4 = 7 times the DC bus voltage of the upper stage. Furthermore, by appropriate selection of the switching states of the individual stages, all intermediate voltage levels including zero can be synthesized. Therefore, the total number of output levels is 2 * (1 + 2 + 4) + 1 = 15 for this inverter [22].
Figure 25.8 shows the reference waveforms and PWM output voltages for all three stages as well as the total output voltage of the entire cascade. The waveforms for the H-bridge with 4 p.u. DC bus voltage are shown in the uppermost diagram of Figure 25.8. It is apparent that this stage is only switching at the fundamental frequency which is appropriate for the high-voltage IGBTs that have to be used in this stage. The reference waveform of the H-bridge with 2 p.u. DC bus voltage is derived from the overall sinusoidal reference waveform by subtracting the output voltage of the 4 p.u. stage. In the same manner, the reference voltage for the 1 p.u. stage is obtained by subtracting the combined output of the lower stages from the sinusoidal reference. This last stage is essentially compensating for the difference between the reference and the output of the lower two stages, which provide the bulk of the voltage and power. As shown in Figure 25.8, each successive stage with lower DC bus voltage has a higher switching frequency. More details about the possible ratios of the DC bus voltages can be found in Ref. [22]. In Ref. [23] the value of multilevel inverters for utility applications is discussed in detail. The advantages of the cascaded H-bridge inverter in this field are its modularity, expandability, and superb output waveform quality.
FIGURE 25.8 Switching waveforms for the cascaded three-stage H-bridge inverter.
FIGURE 25.9 Topology of a five-stage, asymmetric cascaded H-bridge inverter.
While the inverter shown in Figure 25.7 illustrates an example that maximizes the number of output levels with a limited number of stages, the topology represented by Figure 25.9 (again for one phase) shows a more commonly used configuration that has only two different module elements. The inverter has three high-voltage modules which have a DC voltage that is three times higher than the DC bus voltage of the low-voltage stages. All the high-voltage stages are switched at the fundamental frequency, while the low-voltage stages are switched at 10 times the fundamental frequency. The total number of output levels is 2 ⋆ (1 + 1 + 3 + 3 + 3) + 1 = 23 for this inverter [22]. The upper graph in Figure 25.10 shows the typical stair-step output voltage of the three lower stages at 90% modulation level switched at the fundamental frequency. In order to equalize the heat load on the inverter stages, the modulation patterns are typically cyclically rotated between modules of the same DC voltage level. The lower graph in Figure 25.10 shows the combined output waveform of the high- and low-voltage stages of the inverter phase leg along with an ideal sinusoidal reference for 90% modulation.
FIGURE 25.10 Switching waveforms for the cascaded five-stage H-bridge inverter.
25.6 Line-Commutated Inverters
Figure 25.11 shows the topology of a line-commutated inverter. In Figure 25.11, the SCRs are numbered according to their firing sequence. The circuit can operate both as a rectifier and an inverter. The mode of operation is controlled by the firing angle of the SCRs in the circuit [1,2,14]. The reference value for the firing angle α is the instant when the voltage across each SCR becomes positive, that is, when an uncontrolled diode would turn on. This time corresponds to 30° past the positive going zero crossing of each phase. By delaying the turn-on angle α more than 90° past this instant, the polarity of the average DC bus voltage reverses and the circuit enters the inverter mode. The DC source in Figure 25.11 shows the polarity of the DC voltage for inverter operation. The firing delay angle corresponds to the phase of the utility voltage. The maximum delay angle must be limited to less than 180°, to provide enough time for the next SCR in the sequence to acquire the load current. Equation 25.3 gives the value of the DC output voltage of the converter as a function of the delay angle α and the DC current IDC, which is considered constant:
(25.3) |
FIGURE 25.11 Line-commutated converter in inverter mode.
where
VLL is the rms value of the AC line-to-line voltage
ω is the radian frequency of the AC voltage
Ls is the value of the source impedance represented by inductors La, Lb, and Lc in Figure 25.11. Line-commutated inverters have a negative impact on the utility voltage and a relatively low total power factor. Equation 25.4 gives an estimate of the total power factor of the circuit shown in Figure 25.11 for constant DC current and negligible AC line reactors:
(25.4) |
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