Figure 8.23 Doping profile and band diagram for MOSFETs with an n-type surface layer. The surface electric field is proportional to the slope of the bands at the surface, and is reduced in this structure.
8.2.10 Inversion Layer Electron Mobility
8.2.10.1 Mechanisms Affecting Inversion Layer Mobility
In the development of the current–voltage characteristics of the MOSFET in Section 8.2.3, we denoted the mobility of electrons in the inversion layer by the symbol 
. At inversion biases, electrons are confined to the oxide/semiconductor interface by the strong band bending in the semiconductor. The mobility of electrons in the inversion layer is lower than in the bulk semiconductor due to increased scattering at the oxide/semiconductor interface. Moreover, the mobility decreases with increasing gate voltage, since higher gate voltages increase the electric field confining electrons to the interface, resulting in increased scattering. The gate voltage dependence can be described by the empirical equation
where 
is the peak mobility at threshold and 
is a parameter characterizing the rate of decrease with field.
In silicon MOSFETs, the inversion layer mobility near threshold is about half the bulk mobility, but in 4H-SiC the inversion layer mobility on the silicon face is only about 5–10% of the bulk mobility. This impacts the performance of power MOSFETs by increasing the specific on-resistance, as shown by Equation 8.52. The low inversion layer mobility is a major limitation for MOSFETs and IGBTs in 4H-SiC, and inversion layer transport is the subject of intensive research.
Electron mobility in the inversion layer is limited by several scattering mechanisms, including surface phonon scattering, Coulomb scattering by fixed charges and charged interface states, and surface roughness scattering due to the structural and stoichiometric disorder at the interface. In addition, inversion electrons are also subject to the same scattering mechanisms as electrons in the bulk semiconductor. Mobility is inversely proportional to the total scattering rate, and assuming that scattering rates from the different processes add, the resultant mobility can be expressed using Matthiesson's rule as
where 
is the mobility of electrons in the bulk semiconductor, 
is the mobility due to surface phonon scattering, 
is the mobility due to Coulomb scattering, and 
is the mobility due to surface roughness scattering. The inversion layer mobility is therefore determined by the interplay of several scattering mechanisms whose magnitudes are affected by device processing and operating conditions. Many of these dependences can be related to the effective normal field, defined as the electric field in the semiconductor normal to the surface, evaluated at the centroid of the inversion layer [5]. Before considering the scattering mechanisms individually, we will examine how the effective normal field depends on parameters such as gate voltage, doping, and temperature.
In silicon, inversion layer mobility follows a universal curve when plotted against the effective normal field 
, which can be written [5]
Here 
is the sheet charge density in the inversion layer and 
is the charge per unit area in the semiconductor depletion region. In an operating transistor, both 
and 
are functions of position 
along the channel. Using Equations 8.29, and 8.34, the depletion charge can be written
where 
is given by Equation 8.21 and 
by Equation 8.28. The quasi-Fermi level splitting 
is a function of position along the channel, going from 
at the source to 
at the drain. Under delta-depletion electrostatics, the charge in the semiconductor depletion region does not depend on gate voltage in inversion, as shown by Equation 8.64. A more exact analysis would reveal a weak dependence that we will neglect in the present discussion.
The inversion charge 
can be obtained from the gate voltage/surface potential relation of Equation 8.27 after appropriate modifications. Equation 8.27 is derived assuming depletion-region biasing with no inversion layer present. To apply Equation 8.27 in inversion, we must replace 
with an “effective” gate voltage that includes the screening effect of the inversion charge. Performing this modification and setting the surface potential in inversion 
, we obtain
Solving for 
, and expanding the 
term to include charge in interface states 
, we can write
We can apply Equations 8.64 and 8.66 at the source by setting 
. Then using Equation 8.59, the inversion charge at the source reduces to the simple expression 
, showing that the inversion charge increases linearly with gate voltage once 
exceeds 
.
and 
depend on temperature through two effects. As shown in Figure A.3, the Fermi potential 
decreases with temperature, that is, the Fermi level moves closer to midgap as the temperature is raised. This means that less band bending is required to reach inversion, and this is represented in Equations 8.59 and 8.66 by the 
terms. The 
term in these equations is the charge in interface states, which depends on the position of the Fermi level at the surface. For an n-channel MOSFET in inversion, the Fermi level lies above midgap at the surface by an amount equal to 
. As the temperature is raised and the Fermi level moves closer to midgap, the negative charge in interface states decreases and 
becomes less negative. For an n-channel MOSFET, both these effects make 
more negative and 
less positive as the temperature is raised. In contrast, 
becomes less negative with temperature, since 
decreases with temperature (Figure A.3). Since 
and 
change in opposite directions as the temperature is raised, it often turns out that the effective normal field at a fixed gate voltage is only a weak function of temperature, as can be verified using the above equations.
Equations 8.63 and 8.64 indicate that samples with heavier substrate doping (larger 
and 
) have a higher normal field at the same inversion charge density, and this is expected to increase scattering and reduce mobility by confining electrons closer to the interface. In addition, in heavier-doped samples the Fermi level lies closer to the conduction band in inversion, so there is more negative charge in interface states, and this can increase Coulomb scattering.
We will now consider each of the four scattering mechanisms in Equation 8.62. The mobility due to scattering in the bulk semiconductor depends on doping and temperature, and can be described by an equation of the form [6]
where 
is the peak mobility at 300 K, 
is absolute temperature, 
and 
are the ionized dopant concentrations (which depend upon temperature), and 
and 
are constants. Values for these parameters in 4H-SiC are given in Table 8.1, and Appendix A gives equations for 
and 
as a function of temperature and doping. For normal operating conditions, the bulk mobility term is not the limiting factor in SiC inversion layer mobility.
Table 8.1 Parameters of the inversion layer mobility model, Equations 8.70.
| Parameter | Value | Units | References |
 |
1141 |  |
[8, 9] |
 |
 |
 |
|
 |
2.8 | — | |
 |
0.61 | — | |
 |
 |
 |
[7] |
 |
 |
 |
|
 |
 |
 |
[6] |
 |
 |
 |
|
 |
0.8 | — | |
 |
 |
 |
[10] |
Surface phonon scattering is the deflection of electrons by acoustic phonons at the surface. The phonon-limited mobility can be written [7]
where 
and 
are parameters evaluated by fitting theory to experiment and have typical values given in Table 8.1. The phonon-limited mobility decreases with increasing normal field (increasing gate voltage) and decreases with increasing temperature, since higher temperatures are associated with larger lattice vibrations. Although acoustic phonon scattering is important in silicon samples, this term is typically not the limiting factor in SiC MOSFETs fabricated to date.
Coulomb scattering is the deflection of electrons by charged centers at the interface, such as fixed charges 
and charged interface states 
. The scattering effect is independent of the charge polarity, and depends on the total density of charged centers rather than on the net charge density. A number of different formulations have been proposed for Coulomb scattering, but a commonly accepted form that captures the essential physics is [6]
where 
is the total density of fixed charges (sum of positive and negative charges), 
is the total density of charged interface states (both positive and negative), 
is the electron density per unit volume at the surface, and 
, and 
are parameters with typical values given in Table 8.1. Coulomb scattering limits inversion layer mobility at gate voltages near threshold where 
is small, but drops rapidly at higher gate voltages (higher 
values) due to carrier screening by inversion electrons. In samples with high fixed charge 
or high interface state density 
, Coulomb scattering can limit 
to single digits, but improvements in oxidation and anneal processes have reduced both 
and 
to the point that Coulomb scattering is comparable to surface roughness scattering in limiting inversion layer mobility.
Surface roughness scattering is the deflection of electrons by structural defects at the interface. In silicon, surface roughness scattering is attributed to surface steps and residual unoxidized silicon particles at the interface. However, in SiC the situation is more complex, and there is evidence for a transition layer at the interface where the chemical composition changes gradually from pure SiC to pure 
over a distance of several nanometers. The transition layer can be seen in high-resolution transmission electron microscope (TEM) images, where it has an apparent width of several nm [11]. Spatially-resolved electron energy loss spectroscopy (EELS) shows a gradual transition of the C/Si ratio, beginning about 3 nm inside the SiC and extending about 5 nm into the 
. The surface layer of the SiC also exhibits some structural disorder resulting from the oxidation process, and the first monolayers of 
contain excess carbon [11]. The width of the transition layer is influenced by oxidation and anneal procedures, and samples with thinner transition layers have higher peak inversion mobilities [12].
Surface roughness scattering can be characterized by an expression borrowed from the silicon literature, having the general form [13]
where 
is a parameter that depends on the correlation length and mean height of the assumed roughness. This equation has been applied to 4H-SiC by several authors [7, 14], although the more complex nature of the SiC interface suggests the need for further studies. Nevertheless, the general form of Equation 8.70 indicates the strong dependence of surface roughness scattering on normal field. Roughness scattering limits the mobility of SiC MOSFETs at high normal fields and accounts for the decrease in mobility with gate voltage above threshold. This scattering is essentially independent of temperature, provided the normal field is held constant.
Figure 8.24 illustrates how the four scattering mechanisms vary with inversion charge density (or gate voltage) and temperature. Results are shown for two temperatures, 23 and 344 °C. The arrows indicate the trend of the particular scattering mechanism as temperature is increased. At room temperature, Coulomb scattering limits the mobility in most samples at low electron densities (gate voltages close to threshold) and surface roughness scattering limits at high electron densities (strong inversion). Bulk and surface phonon scattering do not play a significant role at room temperature. As temperature increases, Coulomb and surface roughness scattering decrease, while surface and bulk phonon scattering increase. The overall mobility decreases slightly with temperature, mainly due to the strong increase in bulk phonon scattering. This figure illustrates general trends in a way that is consistent with a broad range of reports in the literature, but it does not describe any particular device. As technology advances, interface state density and surface roughness scattering should continue to decrease, leading to higher mobilities and better MOSFET performance.
Figure 8.24 General dependence of surface scattering mechanisms on inversion charge density and temperature. The parameters used to generate these plots were modified slightly from those of Table 8.1 to produce results that are generally consistent with a broad range of reports in the literature.
8.2.10.2 Device-Related Definitions of Inversion Layer Mobility
Having discussed the physical mechanisms governing electron transport in inversion layers, we now wish to consider three different device-related definitions of inversion mobility: effective (or conductivity) mobility 
, field-effect mobility 
, and Hall mobility 
. While closely related, each definition provides a slightly different perspective on conditions and processes within the device.
Equation 8.47 gives the MOSFET current using the “square law” approximation with the source grounded (the effect of a non-zero source voltage is included in Equation 8.44). The effective (or conductivity) mobility is the value deduced by measuring the drain conductance 
at small drain voltages where the 
term in Equation 8.47 can be neglected. Neglecting the 
term, we can write
Thus,
In practice, 
is calculated as a function of gate voltage from the slope of the 
relation at the origin, 
. This mobility should be used for 
in Equations 8.44 and/or 8.47 to calculate the current. Since the mobility varies with gate voltage, 
is usually approximated using the empirical expression in Equation 8.61.
The mobility most often quoted in the literature is the field-effect mobility, obtained from the transconductance measured at a small drain voltage. From Equation 8.47 evaluated at low 
with 
, the transconductance may be written
Thus,
From Equation 8.73, the field-effect mobility is related to the effective mobility by
Since 
decreases with 
, the partial derivative is negative and 
at any gate voltage. Figure 8.25 illustrates how 
and 
vary with gate voltage. Near threshold the effective and field-effect mobilities are equal, but 
decreases more rapidly than 
as gate voltage is increased.
Figure 8.25 Relationship of effective mobility and field-effect mobility, with values typical of 4H-SiC MOSFETs on the (0001) face after thermal oxidation and post-oxidation anneal in nitric oxide.
It is important to note that using 
instead of 
in Equation 8.44 or 8.47 would underestimate the current. Since 
is a differential mobility, calculating the current based on 
would require integration of the 
versus 
relation. From Equation 8.73, we can write
Thus the current at a given gate voltage is proportional to the integral of 
up to that gate voltage, and not to the value of 
at that gate voltage. For this reason, any process that increases the peak field-effect mobility in the region just above threshold will increase the current at all gate voltages, even if 
at high gate voltages is not improved.
Finally, we turn to the Hall mobility 
. Hall mobility is of interest because it allows us to account for the effect of charge sequestration by interface states. In deriving the current Equations 8.44 and 8.47 we assumed all the additional positive charge placed on the gate beyond threshold is balanced by an equal negative charge induced into the inversion layer, as evident from Equation 8.41. However, if interface states are present, some of the charge placed on the gate beyond threshold is balanced by additional charge in interface states, and this reduces the charge density in the inversion layer. Without knowing the distribution of interface states across the bandgap, it is not possible to calculate how much charge is trapped in interface states and how much remains in the inversion layer. If the actual inversion charge density is less than given by Equation 8.41, measurements of 
and 
using Equations 8.72 and 8.74 will underestimate the true carrier mobility. The effective mobility is the correct mobility to use in the current Equations 8.44 and 8.47, since 
includes the combined effects of inversion layer mobility and charge sequestration by interface states, but the Hall mobility is the correct mobility to use if we are concerned with the true carrier mobility in the inversion layer.
The Hall technique is discussed extensively in the literature, and only an outline will be presented here. When used to study the inversion layer in an MOS transistor, the Hall technique imposes a magnetic field 
perpendicular to the surface with a constant drain current 
flowing along the channel. The magnetic field exerts a Lorentz force on the moving electrons given by
where 
is the force directed across the width of the channel (
direction) and 
is the velocity of electrons along the channel in the 
direction. The Lorentz force deflects electrons to one side of the channel, creating a lateral electric field 
perpendicular to the current flow. In steady state the 
-directed force due to the lateral electric field exactly balances the oppositely-directed 
-directed Lorentz force, so 
. The electric field 
produces a lateral potential drop called the Hall voltage, given by
Here, 
is the width of the channel, and we have used the fact that 
. The Hall voltage can be measured by high-impedance probes that contact the inversion layer on opposite sides of the channel. Since we know the current density and magnetic field, we can determine the mobile electron density 
using Equation 8.78. The mobility can then be deduced from the measured current, given knowledge of the true carrier density in the channel. The mobility thus determined is known at the Hall mobility 
.
A more careful analysis that includes momentum relaxation effects would lead to a slightly modified form for Equation 8.78, namely
Here 
is the Hall factor given by 
, where 
is the mean time between electron scattering events. In 4H-SiC the Hall factor at room temperature typically lies in the range 0.96–0.99 [15], and in experimental work it is common to simply set 
.
Since Hall measurements are based on the actual mobile carrier density, the Hall mobility represents the true mobility of electrons in the inversion layer, and 
is invariably higher than 
.
8.2.10.3 Experimental Results on Inversion Layer Mobility in 4H-SiC
Figure 8.26 shows field-effect mobility measured as a function of temperature for a 4H-SiC MOSFET on a 
p-type epilayer doped 
with aluminum [16]. The 
(0001) substrate is grown 8° off-axis. A 54 nm gate oxide was formed by pyrogenic oxidation at 1150 °C, followed by 30 min in situ argon anneal, a 950 °C re-oxidation anneal for 2 h, and a nitric oxide (NO) post-oxidation anneal at 1175 °C for 2 h. The final NO anneal is used to reduce the interface state density in the upper half of the bandgap [17]. Polysilicon gates were deposited at 625 °C and doped at 900 °C. At room temperature, the peak mobility is about 
, decreasing to about 
at 15 V. As temperature is increased, the peak low-field mobility increases to approximately 
at 167 °C, consistent with Coulomb scattering, then decreases to about 
at 344 °C. At higher fields the mobility decreases monotonically with temperature. The decrease in mobility with temperature is suggestive of bulk phonon scattering, as can be inferred from the curves in Figure 8.24. At 344 °C the field-effect mobility has dropped to about 80% of its room temperature value over much of the gate voltage range.
Figure 8.26 Field-effect mobility as a function of temperature for a 4H-SiC MOSFET on a p-type epilayer ([16] reproduced with permission from IEEE).
Figure 8.27 shows Hall mobility as a function of sheet carrier density for an n-channel MOSFET on a p-type epilayer doped 
with aluminum [18]. The substrate is (0001) 4H-SiC, cut 4° off-axis. The oxidation was performed in dry oxygen at 1175 °C, followed by a wet re-oxidation anneal at 950 °C and an 1175 °C post-oxidation anneal in NO for 2 h, resulting in a 53 nm oxide. This is a similar oxidation process to the MOSFET of Figure 8.26, but with a slightly lower epilayer doping. Hall mobility increases with temperature below 20 °C, suggesting that transport at these temperatures is limited by Coulomb scattering. Above room temperature the mobility increases only slightly with temperature, suggesting that transport here is dominated by surface roughness scattering. These conclusions are consistent with the trends illustrated in Figure 8.24.
Figure 8.27 Hall mobility of inversion electrons as a function of effective normal field at several temperatures. The sample was prepared by a similar oxidation process to the MOSFET in Figure 8.26 ([18] reproduced with permission from Trans Tech Publications).
The MOSFET process described above has been investigated by several groups, all of which report increased mobilities as a result of the NO anneal. Recently, however, a number of alternative oxidation processes have been explored, some of which have produced even greater improvements in mobility. We will briefly discuss two of these processes next.
Post-oxidation annealing in phosphorus has been shown to reduce the interface state density and increase the mobility, even compared to the standard NO process. Figure 8.28 shows measured interface state density and field-effect mobility for several 4H-SiC MOSFETs [19]. The MOSFETs were formed on p-type epilayers doped 
with aluminum, and interface state density was measured on MOS capacitors on n-type epilayers doped 
with nitrogen. The substrate is 
(0001), grown 4° off-axis. A 56 nm gate oxide was formed by dry oxidation at 1000 °C, followed by a post-oxidation anneal in 
at 900, 950, or 1000 °C for 10 min and a 30 min nitrogen anneal at the same temperature. Aluminum was evaporated to form the gate electrodes. Other samples were fabricated by dry oxidation at 1000 °C followed by a 1250 °C nitric oxide (NO) anneal for 90 min. As seen in the figure, the 900 °C phosphorus anneal did not reduce the interface state density, but anneals at 950 and 1000 °C decreased the interface state density below that of the NO sample in the upper half of the bandgap. The field-effect mobility of the 1000 °C 
sample is much higher than the 1250 °C NO sample, reaching a peak value of 
before dropping to 
at 20 V. If this result is compared to the MOSFET of Figure 8.26, the mobility improvement is not as great, but is still about a factor of 2.
Figure 8.28 (a) Interface state density and (b) field-effect mobility for dry oxidized samples with no post-oxidation anneal, with a post-oxidation anneal in nitric oxide, and with a post-oxidation anneal in 
. The large increase in mobility for the 
sample is correlated with a reduction in interface state density ([19] reproduced with permission from IEEE).
The improved mobility is explained as a reduction in Coulomb scattering by charged interface states, but the phosphorus process may also introduce a shallow n-type layer at the surface of the SiC. This seems plausible, since phosphorus can be activated as a dopant in 4H-SiC at normal oxidation temperatures. This would produce a situation similar to the doped-channel FET discussed in Section 8.2.9. As shown in Figure 8.23, surface doping reduces the surface normal field at a given inversion electron density, which would lead to higher mobility. However, phosphorus annealing also converts the oxide to phosphosilicate glass (PSG), a polar material having piezoelectric properties that introduce an instability in the threshold voltage [20]. Phosphorus atoms are distributed throughout the gate insulator, and they act as electron traps that introduce a positive threshold shift at high electric fields [21]. Instabilities of this type would make it difficult to use this process in a production environment.
Several groups have explored inversion layer transport on alternative crystal faces such as the 
a-face, where mobilities are typically higher than on the (0001) silicon face. These results are important for devices such as the UMOSFET (or UMOS IGBT) whose inversion layers are on the a-face. Figure 8.29 shows measured interface state density and field-effect mobility for 4H-SiC MOSFETs on both the silicon face and the 
a-face [22]. Planar MOSFETs were formed on p-type epilayers doped 
with aluminum, and interface state density was measured on MOS capacitors on n-type epilayers doped 
with nitrogen. All samples were oxidized in dry oxygen at 1150 °C. Some samples received a post-oxidation anneal in NO at 1175 °C for 2 h, and others received a phosphorus post-oxidation anneal at 1000 °C for 4 h using a planar diffusion source. On a given crystal face, the field-effect mobility is 
higher with the phosphorus anneal compared to the NO anneal. For the same post-oxidation process, the mobility is also 
higher on the 
face than on the silicon face. The highest mobility is obtained with the phosphorus anneal on the 
face.
Figure 8.29 (a) Interface state density and (b) field-effect mobility for dry oxidized samples on two crystal orientations, the (0001) silicon face and the 
a-face. Mobility is shown for both nitrogen and phosphorus post-oxidation anneals, and interface state density is shown for unannealed, nitrogen-annealed, and phosphorus-annealed samples ([22] reproduced with permission from IEEE).
With the phosphorus anneal on the silicon face, the higher mobility is correlated with a lower interface state density, suggesting the mobility is limited by Coulomb scattering, at least at biases near threshold. However, on the 
face the opposite is true: higher mobilities are obtained with the phosphorus anneal, but the interface state density is similar on both faces. Comparing phosphorus anneals on the two faces, a higher mobility is obtained on the 
face even though that face has a higher interface state density. Two possibilities present themselves. Yoshioka et al. [23] have reported that certain annealing procedures create interface states with large capture cross sections whose frequency response is so fast that they are not detected with conventional CV methods, so the conclusion that the silicon face has lower total interface state density may be incorrect. On the other hand, if phosphorus achieves high mobility by creating a thin n-doped layer at the surface, this doping process could be more effective on the 
face than on the silicon face. These issues can only be resolved by further experiments and the reader is advised to consult the literature for the latest information.
An intriguing result is the high mobility observed in samples oxidized in an alumina furnace tube [24], as shown in Figure 8.30 [25]. The high mobility is correlated with the presence and position of sodium ions in the oxide, introduced from impurities in the alumina tube. These ions are mobile in 
at elevated temperatures, and can be drifted toward the interface or toward the gate by application of a positive or negative gate voltage. The highest mobilities are observed when the sodium ions are close to the interface, the “initial” and “recovered” curves in Figure 8.30. When the sodium ions are drifted to the gate by negative bias-temperature stress, the threshold voltage increases, and the mobility decreases. Measurements of interface state density on n-type MOS capacitors indicate that the position of the sodium ions has no effect on interface state density [25], suggesting that a reduction of Coulomb scattering is not the mechanism responsible for the mobility improvement. It is also significant that the mobility at high gate fields is not affected by the ions. In other words, sodium enhances the mobility at low gate fields but not at high fields. The physical mechanism responsible for these observations is not understood. As might be expected, the instability in threshold voltage associated with sodium precludes the use of this process in practical devices.
Figure 8.30 Field-effect mobility of a MOSFET whose oxide is contaminated with sodium ions. Negative bias-temperature stress (BTS) draws the positive sodium ions to the gate, where they have no effect on the electrostatics. This shifts the threshold positive and reduces the mobility. After the stress is removed, the threshold and mobility gradually recover to their pre-stress values ([25] reproduced with permission from Trans Tech Publications).
Even though both phosphorus and sodium processes introduce threshold instabilities, the results are still encouraging because they show that significantly higher mobilities are possible in 4H-SiC MOS devices. The goal now is to understand the mechanisms for the mobility improvement and develop processes that deliver the improvement without introducing instabilities.
8.2.11 Oxide Reliability
Two of the main advantages of SiC compared to silicon are its higher bandgap energy and higher critical field for avalanche breakdown. The critical field in 4H-SiC is 6–7 times higher than in silicon (Figure 10.5) and, as discussed in Chapter 7, the on-resistance of SiC unipolar devices is about 400 times lower than silicon devices of the same blocking voltage. However, the higher critical field means that gate oxides in SiC MOS devices may be subjected to higher fields than oxides in silicon devices. The oxide field is related to the surface field in the semiconductor by Gauss' law, so we can write
where 
is the perpendicular component of the semiconductor field at the surface. In SiC, 
(and therefore 
) can be 6–7 times higher than in silicon. The oxide field may be increased even further by fixed charges 
and interface trapped charges 
. In addition, the barrier heights for electron and hole injection into 
are lower for SiC, as shown in Figure 8.21. The higher oxide field and lower barrier height raise concerns for the long term reliability of SiC MOS devices, particularly at high temperatures.
The literature contains very few careful studies of SiC MOS reliability. One reason is the large number of samples (20–50) and long measurement times (weeks to months) needed to obtain an adequate data set. Most studies make use of constant-voltage stress at elevated temperatures. The procedure is to subject a number of identical devices, either MOS capacitors or MOSFETs, to accelerated stress conditions (high oxide fields and high temperatures) and monitor the leakage currents through the gate oxides. A certain current density is chosen as indicative of oxide failure, and a set of devices is stressed simultaneously while the gate currents are monitored. As devices fail, their failure times are recorded and the test continues until the entire set of devices has failed. The failure times are plotted on a Weibull plot, where it is possible to distinguish between extrinsic and intrinsic failures. In this context, “extrinsic” refers to early failures due to oxide defects, and “intrinsic” refers to failure of an intrinsically good oxide. Since the extrinsic failures do not represent the fundamental properties of the oxide, they are eliminated from the distribution and the mean-time-before-failure 
or the 63% failure time 
of the remaining intrinsic set is determined. Constant-voltage stress is considered fairly representative of actual operating conditions. A quicker procedure, known as constant-current stress, forces a constant current through the oxide and measures the total charge-to-breakdown, or 
. The discussion below deals only with constant-voltage stress.
Figure 8.31 shows 63% failure times as a function of oxide field for 4H-SiC MOS capacitors on n-type epilayers from two vendors [26]. As is the case in silicon [27], the time-to-failure increases exponentially as the oxide field is reduced, and a constant field acceleration factor 
is observed. At 225 °C, extrapolation to lower fields predicts a 
of 100 years if the oxide field is kept below 
. The oxide field must be kept below 
if a 
of 100 years is to be obtained at 375 °C. Although 100 year lifetimes may seem excessive, this is the time for 63% of the samples to fail. Failure times for lower failure percentages, say 10%, can be determined by examining the failure distributions in the Weibull plots at each field.
Figure 8.31 63% failure time as a function of oxide field for 4H-SiC MOS capacitors on n-type epilayers at two temperatures ([26] reproduced with permission from IEEE).
Figure 8.32 shows 
failure time versus oxide field for 4H-SiC power DMOSFETs at three temperatures [28]. The n-channel DMOSFETs are formed on implanted p-type base regions, and a portion of the gate extends over implanted 
source regions. Oxides over heavily-implanted regions are not as robust as those over epitaxial layers, and the 
times for the DMOSFET are shorter than the MOS capacitors of Figure 8.31. Extrapolation of the high-field data indicates that a 
of 100 years can be realized at 175 °C by keeping the oxide field below 
. The same lifetime can be obtained at 275 °C by keeping the oxide field below 
, and at 300 °C by keeping the oxide field below 
.
Figure 8.32 63% failure time as a function of oxide field for 4H-SiC power DMOSFETs at three temperatures ([28] reproduced with permission from Trans Tech Publications).
The data in Figure 8.32 also illustrate the danger in extrapolating high-field data to lower fields. At 275 and 300 °C the field acceleration factor 
is not independent of field, but exhibits a break at an oxide field around 
. If extrapolations were made using only data above 
, unrealistically long lifetimes would be predicted at normal operating fields. This brings into question the practice of predicting low-field reliability by extrapolation from high-field data. However, it seems safe to assume that the low-field reliability will not be better than predicted by extrapolating from high-field data. The severity of the change in field acceleration factor in Figure 8.32 decreases as temperature is reduced, and at 175 °C it appears that extrapolation using the high-field acceleration factor is reasonable.
Finally, we should point out that the operational lifetime of the MOSFET may be limited not by catastrophic oxide failure, but by a gradual drift in parameters such as threshold voltage or on-resistance. Unfortunately, no studies of long-term parameter drift have been published for SiC devices, leaving the question of parameter stability largely unanswered.
8.2.12 MOSFET Transient Response
One of the motivations for using MOSFETs in power switching systems is their high switching frequency and low switching loss. This allows the entire system to operate at a high frequency, leading to significant reductions in the volume and weight of passive components, such as transformers and filter capacitors, that often dominate system cost. In this section we will consider the transient response of the power MOSFET in some detail.
The switching transients of the power MOSFET can be analyzed using the clamped inductive load circuit of Figure 8.33. The inductor is representative of the windings of an electric motor, and its inductance is assumed large enough that the current 
cannot change appreciably during the switching transient. 
represents the internal resistance of the bond wires and the distributed gate resistance of the MOSFET. 
and 
are the gate-source and gate-drain capacitances of the MOSFET, 
is the source resistance, and 
is the lumped drain resistance of the MOSFET.
Figure 8.33 Equivalent circuit used for the transient analysis of a MOSFET driving a clamped inductive load. The dashed box encloses the MOSFET and its internal parasitic elements.
Since the p-type body regions of power MOSFETs are not lightly doped, the 
terms in Equations 8.44 and 8.48 cannot be ignored, and the simplified Equations 8.47 and 8.49 will overestimate the current and underestimate the switching time. However, retaining all the 
terms would make the mathematics very cumbersome. Therefore, to illustrate the main features of the switching transient, we will utilize the approximate Equations 8.47 and 8.49 and assume the source resistance 
is negligible. This will not provide numerically precise answers, but will capture the qualitative features of the transient. A more quantitative analysis can be performed using the full MOSFET equations and a nonlinear circuit simulator such as 
.
The turn-on transient will be considered first. Prior to 
the MOSFET is off, and the inductor current circulates through the clamping diode. If we neglect the forward drop of the diode, which is likely to be a SiC junction-barrier Schottky (JBS) or merged pin-Schottky (MPS) diode, the drain voltage of the MOSFET is the supply voltage 
. The turn-on process can be divided into four phases, as illustrated in Figure 8.34.
Figure 8.34 Drain characteristics of the MOSFET to be analyzed, with 
, and 
. In these calculations, 
, and 
switches between 0 and 20 V.
8.2.12.1 Turn-On, 0 < t < t1
At 
the voltage at the gate terminal is stepped to 
, but the MOSFET does not turn on until 
has charged to 
through the RC input circuit. The gate voltage during the charging process can be written
where 
is given by
Setting 
allows us to calculate 
,
The gate current during this phase is of interest, and can be written
8.2.12.2 Turn-On, t1 < t < t2
At time 
the MOSFET turns on and its drain current increases, but the clamping diode remains forward biased until the drain current through the MOSFET equals the inductive load current 
. As long as the diode is forward biased, the drain-source voltage of the MOSFET remains at 
and the gate-source voltage continues to increase according to Equation 8.81. Since 
, the MOSFET is in its saturation region and the drain current can be described by Equation 8.47 with 
set equal to 
, namely
The drain current will increase according to Equations 8.85 and 8.81 until time 
when 
, at which point the MOSFET is carrying all the load current and the diode becomes reverse biased. The trajectory between times 
and 
is illustrated on the 
characteristics of the MOSFET in Figure 8.34. Time 
can be calculated by setting 
in Equation 8.85 to obtain 
, and inserting this into Equation 8.81 to solve for 
. The result is
8.2.12.3 Turn-On, t2 < t < t3
When the diode becomes reverse biased, the drain voltage of the MOSFET is no longer clamped at 
, and is free to decrease. However, the drain current is now held fixed at 
by the inductor. With the drain current constant, the gate-source voltage cannot change, as shown by Equation 8.85. Since 
has not yet reached 
, gate current continues to flow through 
and passes as displacement current through 
. (Although 
is constant, 
is now falling, and this draws displacement current through 
. In claiming that 
is constant, we are assuming this displacement current is small compared to 
.) The gate current can now be written
Writing 
and setting 
yields
Since 
and 
are constant during this period, Equation 8.88 tells us that the drain voltage decreases linearly with time. The drain voltage transient can be calculated by integrating Equation 8.88,
The above analysis holds so long as the MOSFET remains in its saturation region, where the drain current is given by Equation 8.85. When 
falls below 
, the MOSFET enters its quasi-linear region and 
must be calculated using Equation 8.47. This marks the end of the third portion of the transient, and the time 
can be found by setting 
equal to 
,
8.2.12.4 Turn-On, t > t3
For 
the MOSFET is in its quasi-linear region. The gate current can be written
Since 
is now 
, we can set 
, so
Cross-multiplying,
Integrating Equation 8.93 from 
to 
yields
where we are reminded that 
. During the period 
the drain voltage decreases toward the steady-state drain–source voltage of the MOSFET. Setting 
in Equation 8.47 equal to 
and solving for 
yields
As the device approaches steady state, 
approaches 
. Inserting 
into Equation 8.95 yields
The total gate charge during turn-on is found by setting 
. 
goes from zero to 
during the transient, while 
goes from 
at 
to 
at 
. Using Equation 8.96 for 
yields
Figure 8.35a–c show gate voltage, drain current, and drain voltage for the MOSFET of Figure 8.34 as calculated using the above equations with parameters typical of a modern commercial power DMOSFET. In these calculations, the supply voltage 
, the terminal gate voltage 
, and the inductive load current 
A. The time 
for 
to reach threshold is short, only 0.52 ns. The MOSFET drain current then rises according to Equation 8.85 until reaching the 20 A load current at time 
ns. At this point the diode becomes reverse biased and the MOSFET drain voltage decreases linearly according to Equation 8.89 until time 
ns. During this period 
remains constant at 11.8 V, 
is constant at 1.78 A, and 
is constant at 20 A. At time 
the drain voltage has reached 
and the MOSFET enters its quasi-linear region. From this point, 
declines according to Equation 8.95 to a final value of 
.
Figure 8.35 Transient waveforms during the turn-on transient, assuming 
. (a) Internal gate-source voltage 
, (b) drain current 
, (c) drain-source voltage 
, and (d) instantaneous power dissipation within the MOSFET.
The instantaneous power dissipated during the turn-on transient is given by
The instantaneous power dissipation is plotted in Figure 8.35d, and the integral of this waveform gives the turn-on energy, 
in this example. From Equation 8.97, the gate charge during the turn-on transient is 36.6 nC.
The turn-off transient follows the same trajectory as the turn-on transient, but in the opposite direction, as illustrated in Figure 8.36. Prior to the start of the transient at 
, the MOSFET is in its conducting state with a very low forward voltage drop. The clamping diode is reverse biased, and all the load current flows through the MOSFET.
Figure 8.36 Idealized switching trajectory of the MOSFET during turn-off.
8.2.12.5 Turn-Off, 0 < t < t4
At 
the voltage at the gate terminal is switched to zero, but the MOSFET does not turn off immediately because the RC input circuit must discharge. As 
decreases, 
must increase to keep the drain current at a constant value equal to 
, but the change in 
during this period is small compared to the change in 
, so we can write the gate voltage as
where 
is the time constant of the gate circuit, given by Equation 8.82. However, as 
increases, it eventually reaches 
and the MOSFET enters saturation. At this point we can write
Defining this point as 
and solving for 
,
Inserting Equation 8.101 into Equation 8.99 gives
While the MOSFET is in its quasi-linear region, the drain current is given by
Solving for 
, we can write
with 
given by Equation 8.99.
8.2.12.6 Turn-Off, t4 < t < t5
Between times 
and 
the MOSFET is in saturation and the drain current is fixed at 
. Since the drain current remains constant, the gate voltage cannot change, and remains at the value given by Equation 8.101. The gate current can be written
Writing 
and setting 
yields
Equation 8.106 tells us that the drain voltage increases linearly with time,
At 
, so from Equation 8.107 we have
where we have made use of the fact that 
.
8.2.12.7 Turn-Off, t5 < t < t6
As 
tries to rise above 
, the clamping diode becomes forward biased and holds 
at 
plus a diode drop (which we will neglect). The diode carries an increasing fraction of the load current, and the MOSFET drain current decreases toward zero. Since 
decreases with 
held constant, 
must also decrease. Writing the equation for the gate current,
Solving Equation 8.109 for 
,
At 
reaches 
and the MOSFET turns off. Setting 
in Equation 8.110, we find that
During the period from 
to 
, the MOSFET is in its saturation region and 
is given by Equation 8.85, with 
given by Equation 8.110.
8.2.12.8 Turn-Off, t > t6
For times 
the MOSFET is off, and the gate voltage 
decreases toward zero according to Equation 8.110.
The gate charge 
removed by the input circuit during the turn-off transient is precisely the same as the charge supplied during the turn-on transient, since at the end of the turn-off process both 
and 
have returned to their original charge states.
Figure 8.37a–c show gate voltage, drain current, and drain voltage for the MOSFET of Figure 8.36. The time 
for 
to rise to 
is 2.33 ns. During this time the change in 
, 9.63 V, is almost imperceptible on the scale of Figure 8.37c. The MOSFET enters saturation at 
and the drain current remains fixed at the load current, 20 A. According to Equation 8.85, 
must also remain constant. However, 
can rise because 
is independent of 
in saturation. The increase in 
is just sufficient to create the displacement current in 
required to satisfy Equation 8.106. The drain voltage reaches the supply voltage at time 
ns. At this point the clamping diode becomes forward biased and holds 
constant at 
. After 
the diode carries an increasing fraction of the load current, and 
decreases. The drain current reaches zero at 
ns, when 
has fallen to 
. The gate voltage continues to decrease as the input circuit completes its discharge. Figure 8.37d shows the instantaneous power during the turn-off transient, and the integral of this waveform is the turn-off energy, 
.
Figure 8.37 Transient waveforms during the turn-off transient. (a) Internal gate-source voltage 
, (b) drain current 
, (c) drain-source voltage 
, and (d) instantaneous power dissipation within the MOSFET.
References
- [1] Palmour, J.W., Edmond, J.A., Kong, H.S., and Carter, C. (1993) 6H-SiC power devices for aerospace applications. Proceedings of the 28th Intersociety Energy Conversion Conference, pp. 1.249–1.254.
- [2] Shenoy, J.N., Melloch, M.R., and Cooper, J.A. (1996) High-voltage double-implanted power MOS transistors in 6H-SiC. IEEE Device Research Conference, Santa Barbara, CA.
- [3] Saha, A. and Cooper, J.A. (2007) A 1200 V 4H-SiC power DMOSFET optimized for low on-resistance. IEEE Trans. Electron. Devices, 54 (10), 2786–2791.
- [4] Tan, J., Cooper, J.A. and Melloch, M.R. (1998) High-voltage accumulation-layer UMOSFETs on 4H-SiC. IEEE Electron. Device Lett., 19 (12), 487–489.
- [5] Sabnis, A.G. and Clemens, J.T. (1979) Characterization of the electron mobility in the inverted <100> Si surface. IEEE International Electron Devices Meeting Technical Digest, pp. 18–21.
- [6] Powell, S.K., Goldsman, N., McGarrity, J.M. et al. (2002) Physics-based numerical modeling and characterization of 6H-silicon carbide metal-oxide-semiconductor field-effect transistors. J. Appl. Phys., 92 (7), 4053–4061.
- [7] Potbhare, S., Goldsman, N., Pennington, G. et al. (2006) Numerical and experimental characterization of 4H-silicon carbide lateral metal-oxide-semiconductor field-effect transistor. J. Appl. Phys., 100 (4), 044515.1–044515.8.
- [8] Schaffer, W.J., Negley, G.H., Irvine, K.J. and Palmour, J.W. (1994) Conductivity anisotropy in epitaxial 6H and 4H-SiC, in Diamond, SiC, and Nitride Wide-Bandgap Semiconductors, Materials Research Society Proceedings, (eds C.H. Carter Jr., G. Gildenblatt, S. Nakamura and R.J. Nemanich), MRS, vol. 399, pp. 595–600.
- [9] Ruff, M., Mitlehner, H. and Helbig, R. (1994) SiC devices: physics and numerical simulaton. IEEE Trans. Electron. Devices, 41 (6), 1040–1054.
- [10] Tilak, V. and Matocha, K. (2007) Electron-scattering mechanisms in heavily doped silicon carbide MOSFET inversion layers. IEEE Trans. Electron. Devices, 54 (11), 2823–2829.
- [11] Taillon, J. A., Yang, J. H., Ahyi, C. A. et al. (2013) Systematic structural and chemical characterization of the transition layer at the interface of NO-annealed
metal-oxide-semiconductor field-effect transistors. J. Appl. Phys., 113 (4) 044517.1–044517.6. - [12] Biggerstaff, T.L., Reynolds, C.L. Jr., Zheleva, T. et al. (2009) Relationship between
transition layer thickness and mobility. Appl. Phys. Lett., 95 (3), 032108.1–032108.3. - [13] Zeng, Y.A., White, M.H. and Das, M.K. (2005) Electron transport modeling in the inversion layers of 4H and 6H-SiC MOSFETs on implanted regions. Solid-State Electron., 49 (6), 1017–1028.
- [14] Dhar, S., Haney, S., Cheng, L. et al. (2010) Inversion layer carrier concentration and mobility in 4H-SiC metal-oxide-semiconductor field-effect transistors. J. Appl. Phys., 108 (5), 054509.1–054509.5.
- [15] Schmid, F., Krieger, M., Laube, M. et al. (2004) Hall scattering factor of electrons and holes in SiC, in Silicon Carbide—Recent Major Advances (eds W.J. Choyke, H. Matsunami and G. Pensl), Springer, Berlin, pp. 517–536.
- [16] Lu, C.Y., Cooper, J.A., Tsuji, T. et al. (2003) Effect of processing variations and ambient temperature on electron mobility at the
interface. IEEE Trans. Electron. Devices, 50 (7), 1582–1588. - [17] Chung, G.Y., Tin, C.C., Williams, J.R. et al. (2000) Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4H polytype of silicon carbide. Appl. Phys. Lett., 76 (13), 1713–1715.
- [18] Dhar, S., Ahyi, A.C., Williams, J.R. et al. (2012) Temperature dependence of inversion layer carrier concentration and Hall mobility in 4H-SiC MOSFETs, in Mater. Sci. Forum, vol. 717–720, pp. 713–716.
- [19] Okamoto, D., Yano, H., Harita, K. et al. (2010) Improved inversion channel mobility in 4H-SiC MOSFETs on Si face utilizing phosphorus-doped gate oxide. IEEE Electron. Device Lett., 31 (7), 710–712.
- [20] Sharma, Y.K., Ahyi, A.C., Isaacs–Smith, T. et al. (2013) High-mobility stable 4H-SiC MOSFETs using a thin PSG interfacial passivation layer. IEEE Electron. Device Lett., 34 (2), 175–177.
- [21] Yano, H., Hatayama, T. and Fuyuki, T. (2012)
annealing as a new method for improving 4H-SiC MOS device performance. Trans. Electrochem. Soc., 50 (3), 257–265. - [22] Liu, G., Ahyi, A.C., Xu, Y. et al. (2013) Enhanced inversion mobility on
using phosphorus and nitrogen interface passivation. IEEE Electron. Device Lett., 34 (2), 181–183. - [23] Yoshioka, H., Nakamura, T. and Kimoto, T. (2012) Generation of very fast states by nitridation of the
interface. J. Appl. Phys., 112 (1), 024520 (6 pages). - [24] Gudjonsson, G., Olafsson, O., Allerstam, F. et al. (2005) High field-effect mobility in n-channel Si-face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material. IEEE Electron. Device Lett., 26 (2), 96–98.
- [25] Sveinbjörnsson, E.O., Gudjonsson, G., Allerstam, F. et al. (2006) High channel mobility 4H-SiC MOSFETs, in Mater. Sci. Forum, vol. 527–529, pp. 961–966.
- [26] Yu, L., Cheung, K.P., Campbell, J. et al. (2008) Oxide reliability of SiC MOS devices. 2008 IEEE International Integrated Reliability Workshop Final Report, S. Lake Tahoe, CA, October 12–16, pp. 141–144.
- [27] Prendergast, J., Suehle, J., Chaparala, P. et al. (1995) TDDB characterization of thin
films with bimodal failure populations. IEEE Reliability Physics Symposium, pp. 124–130. - [28] Das, M.K., Haney, S., Richmond, J. et al. (2012) SiC MOSFET reliability update, in Mater. Sci. Forum, vol. 717–720, pp. 1073–1076.