7.1 Introduction to SiC Power Switching Devices

The majority of silicon carbide devices developed to date can be grouped into three general classes: power switching devices, microwave devices, and specialty devices (sensors, high-temperature integrated circuits, etc.). Of these, by far the most important and most fully developed are the power switching devices. Accordingly, Chapters 7–11 will be devoted to SiC power devices, and other SiC device applications will be considered in Chapter 12.

Power switching devices attempt to emulate an ideal switch. An ideal switch carries infinite current in the on state with zero voltage drop, and hence zero power dissipation. In the off state it blocks infinite voltage with zero leakage current, and it switches instantly between states using zero switching energy. Of course, real semiconductor switches only approach these ideals, and the degree to which they achieve these goals is indicated by the performance specifications of the device. Most critical of these are blocking voltage, maximum on-state current, on-state and off-state power dissipation, and switching loss. Since maximizing performance involves trade-offs between parameters, researchers have developed figures of merit (FOMs) that define the theoretical envelope of maximum performance and quantify the degree to which actual devices approach these theoretical limits. Device performance depends on fundamental material parameters, as well as on device parameters such as dopings, physical dimensions, and so on. SiC is of interest because its fundamental material parameters, especially its high breakdown field, result in theoretical performance that is orders of magnitude higher than silicon.

To begin, let us consider blocking voltage, and the relationship between blocking voltage and on-state power dissipation. Since all power devices support their terminal voltage in the off-state by means of a reverse-biased pn junction (or a reverse-biased metal–semiconductor junction), we will first consider the voltage limits of reverse-biased pn junctions.

7.1.1 Blocking Voltage

Consider a one-sided step junction under reverse bias. If the doping is highly asymmetrical, we can assume all the depletion occurs on the side, and the electric field profile is as shown in Figure 7.1. The reverse voltage can be increased until the maximum field equals the critical field for avalanche breakdown , at which point breakdown occurs. The blocking voltage is the integral of the electric field at this point, or

7.1

where is the depletion width at breakdown. If the blocking voltage is large compared to the built-in potential, the depletion width of a one-sided step junction at breakdown can be written

7.2

where is the semiconductor dielectric constant and is the doping on the lightly-doped side. Using Equation 7.1 to eliminate in Equation 7.2 allows us to solve for ,

7.3

Equation 7.3 tells us that the blocking voltage of a junction of a given doping is proportional to the square of the critical field. The critical field in SiC is almost an order-of-magnitude higher than in silicon, so the blocking voltage for a given doping will be almost two orders-of-magnitude higher than in silicon.

Suppose the region is designed with a finite thickness . Using Equation 7.3 we can get a relationship between blocking voltage and doping as a function of . To see the basic features, let's first assume that the critical field is independent of doping, that is, a known constant. In this case, Equation 7.3 tells us that blocking voltage is inversely proportional to doping, that is, we can double the blocking voltage by halving the doping. However, each time we do this, Equation 7.2 tells us we also double the depletion width at breakdown . Eventually will exceed , at which point our simple picture has to be revised. If the region is terminated in a heavily-doped region, the depletion region will not extend very far into the region, and the field profile will go from triangular to trapezoidal, as shown in Figure 7.2. As we further reduce the doping, the field trapezoid will approach a rectangle of height and width , whereupon the blocking voltage will become

7.4

Figure 7.3 shows a plot of versus doping in 4H-SiC for several fixed values of . These curves are calculated using the ionization integral (to be discussed in Section 10.1), and include the actual doping dependence of . The maximum possible blocking voltage for a fixed is achieved by making the doping small. However, this has an undesirable effect on the on-state power dissipation, as explained next.

For a unipolar device, where current flow is due solely to majority carriers, the analysis is particularly simple. Assuming negligible contribution from the junction voltage drop, the on-state power dissipation per unit area within the device can be written

7.5

where is the on-state current density and is the specific on-resistance, defined as the resistance-area product, in units of . For the one-sided step-junction, the on-resistance arises primarily from the resistance of the lightly-doped region, and we can write

7.6

where is the resistivity, the electron mobility in the direction of current flow, and the ionized dopant concentration in the region. Clearly, reducing to achieve the maximum blocking voltage increases the specific on-resistance and the on-state power dissipation. As designers, how do we decide where the optimum lies? The answer is to maximize the unipolar power device figure of merit (FOM).

7.1.2 Unipolar Power Device Figure of Merit

A useful figure of merit for all power devices is the product of blocking voltage and on-state current, since an “ideal” power switch would maximize both. Thus we can write

7.7

where is the area of the device and is the on-state current density. The maximum allowable power dissipation is determined by the thermal capability of the package, the heat sink temperature, and the maximum allowable junction temperature of the device. For a unipolar device we can attribute the majority of power dissipation to the on-state power . In this case, the maximum is obtained from Equation 7.5 as

7.8

and our FOM can be written

7.9

There are three factors in this FOM. The device area is limited by material quality and fabrication technology, and ultimately by manufacturing yield. The maximum power dissipation is limited by the thermal capability of the package and the maximum junction temperature of the device; using a package with a lower thermal resistance would increase the FOM. The remaining factor, , represents the unipolar device FOM, and it is the goal of the designer to maximize this ratio.

The device FOM for a unipolar device can be calculated as follows. From Equation 7.3 we can write

7.10

We assume a non-punch-through design, such as shown in Figure 7.1, where the electric field profile is triangular. To minimize on-resistance, we reduce the region thickness so that it just equals . In this case, Equation 7.1 yields

7.11

Now inserting Equations 7.10 and 7.11 into Equation 7.6, and assuming complete ionization of the donor impurities, we have

7.12

Equation 7.12 tells us that the specific on-resistance of an optimally designed non-punch-through unipolar device increases as the square of the desired blocking voltage, and is inversely proportional to the cube of the critical field. Since the critical field in 4H-SiC is almost an order-of-magnitude higher than in silicon, the on-resistance for a given blocking voltage will be almost 1000 times lower. This accounts for the great interest in developing power devices in this material (although the actual reduction in is closer to due to the lower in SiC.) Finally, to write the desired unipolar device FOM, we can rearrange Equation 7.12 to yield

7.13

Equation 7.13 represents the maximum possible FOM for an optimally designed non-punch-through unipolar device [for a punch-through design, replace the 4 by (3/2)³]. Real devices can only approach this theoretical limit, and comparing the actual measured to the theoretical limit given by Equation 7.13 is a useful indication of design and processing optimization. Note that the theoretical FOM depends on fundamental material constants, and not on specific device parameters. We will discuss how to achieve an optimal design in Section 10.2.

7.1.3 Bipolar Power Device Figure of Merit

The above discussion provides guidelines for optimizing the performance of unipolar devices, but how do we modify our thinking when dealing with bipolar devices, and how do we compare unipolar and bipolar devices for the same application? In bipolar devices, current flow involves both majority and minority carriers. A simple example is a diode. If the region is very lightly doped, we can think of this as a or “pin” diode. In the previous discussion we assumed the current in the region consisted only of majority carrier electrons, but in a pin diode the current in the middle region includes both holes injected from the region and electrons injected from the region. The presence of both types of carriers in this region significantly reduces the resistivity given by

7.14

This “conductivity modulation” can lead to a large reduction in the on-state power dissipation, as shown by inserting Equation 7.14 into Equation 7.6, and Equation 7.6 into Equation 7.5. However, in a bipolar device we also have to consider power dissipation due to switching transients. This is because the minority carriers stored in the lightly-doped region need to be removed when the device turns off. This removal process involves recombination, drift, and diffusion, and as long as the carrier density remains high, the resistivity remains low. The low resistivity allows a significant reverse current to flow until all carriers have been removed. This reverse current, in turn, leads to a significant transient power dissipation. A quantitative analysis typically requires transient computer simulations that include the power dissipation in the external circuit elements, but the main point here is that power is dissipated during each switching event. It is convenient to consider the integral of the transient power over the switching event, or the switching energy . It is important to include both turn-on and turn-off events, although the turn-off energy is usually much larger than the turn-on energy. The switching power dissipation is then proportional to switching frequency ,

7.15

We can now generalize our power device FOM given by Equation 7.7. The switching energy is a function of the carrier densities in the region established during the on state, and these densities depend on the on-state current , so we can write

7.16

where the exact dependence of and on the on-state current is best established by transient computer simulations. The total power dissipation is the sum of the on-state power, off-state power, and switching power, so we can write

7.17

where is the duty cycle. In the case of a unipolar device, is given by Equation 7.5, is usually negligible, and is established by computer simulations. In the case of a bipolar device, may be a nonlinear function of (such as in a pn diode), and is established by computer simulations. Again, is usually negligible. In any event, setting in Equation 7.17 equal to the power dissipation limit of the package establishes an upper limit for at a given switching frequency and duty cycle . At very low frequencies the switching loss can be ignored, but at high frequencies the switching loss can become the dominant loss.

Although the analysis for a bipolar device is more complicated than for a unipolar device, the basic procedure is similar. For a given desired blocking voltage, the bipolar device that meets that blocking voltage is evaluated to determine how and depend on . Given the switching frequency, we can calculate using Equation 7.17 and adjust so that equals the power dissipation limit of the package. The resulting current density then becomes our FOM; the device with the highest current density at the required switching frequency and blocking voltage wins. This technique can be used to compare bipolar devices to other bipolar devices, or to make a fair comparison between bipolar and unipolar devices for the same intended application.

A critical aspect of device design is to achieve a blocking voltage as close as possible to the theoretical plane-junction blocking voltage in Figure 7.3. Every real device has edges, and field crowding at the edges can reduce the actual blocking voltage to a small fraction of the value in Figure 7.3. This problem is mitigated by various types of edge terminations, as will be discussed in Section 10.1.

Having presented the general considerations in the design and optimization of unipolar and bipolar devices, we now turn to a discussion of specific devices, beginning with the Schottky diode.

7.2 Schottky Barrier Diodes (SBDs)

The Schottky barrier diode (SBD) is a rectifying metal–semiconductor contact whose band diagram is illustrated in Figure 7.4. The main features that distinguish a Schottky diode from an ohmic contact are the work function of the metal and the doping of the semiconductor. In a Schottky contact, the work function places the metal Fermi level near the middle of the semiconductor bandgap. This creates a barrier to carrier injection from the metal into either band of the semiconductor, so current can only flow by the injection of majority carriers from the semiconductor into the metal. This insures unidirectionality of current and produces a rectifying current–voltage relationship. Likewise, the doping of the semiconductor must not be too high. If the doping is high, the depletion width in the semiconductor will be very small, and electrons can tunnel between the majority carrier band of the semiconductor and states at the same energy in the metal, leading to ohmic, or non-rectifying, behavior.

The theory of current flow in the SBD is developed in many textbooks, and the derivation will not be repeated here. The current density can be written

7.18

where is the modified Richardson's constant for the semiconductor given by

7.19

Here is the metal–semiconductor barrier height shown in Figure 7.4, is Boltzmann's constant, is absolute temperature, (or ) is the majority carrier effective mass, is Planck's constant, and is the voltage drop (or the offset in Fermi levels) across the junction. is usually determined by experiment, and for 4H-SiC is approximately [2]. The factors preceding the term in square brackets in Equation 7.18 constitute the saturation current, and it is notable that the current scales exponentially with barrier height . Clearly, reducing the barrier height increases both forward and reverse current dramatically.

An important correction needs to be made to Equation 7.18 to account for Schottky barrier lowering, in which the effective barrier height is reduced by the electric field at the surface of the semiconductor. This is especially important when the electric field is high, as under reverse-bias conditions. The effective barrier height can be written as

7.20

where is the barrier height at zero field, is the electric field in the semiconductor at the surface, and is the dielectric constant of the semiconductor. With this correction, the reverse current in the SBD does not saturate, but continues to increase gradually until breakdown. Since the second term in Equation 7.20 is independent of barrier height, the effect is more pronounced when the zero-field barrier height is low. For this reason it is important to ensure adequate . Table 7.1 lists the barrier height of various metals on 4H-SiC as measured by both and techniques.

Metal	Face			References
Ni	Si	1.70	1.60	[3]
Ni	Si	—	1.30	[1]
Ni	Si	—	1.4–1.5	[4]
Au	Si	1.80	1.73	[3]
Ti	Si	1.15	1.10	[3]
Ti	Si	—	0.80	[1]
Ni	C	—	1.55	[5]
Au	C	—	1.88	[5]
Ti	C	—	1.20	[5]

The on-state voltage drop of a Schottky diode consists of the junction drop plus the voltage drop across the lightly-doped drift region and the heavily-doped substrate. for a given is given by Equation 7.18, and the voltage drop across the drift region and substrate is

7.21

where is given by Equation 7.6. Figure 7.5 shows measured forward current–voltage characteristics of Ni and Ti Schottky diodes as a function of temperature [1]. The higher current of the Ti diode is due to its lower barrier height, and the current increases with temperature, as predicted by Equation 7.18. The current saturation at high forward currents is due to the resistance of the drift region. This occurs because in Equation 7.21 increases linearly with current, while the junction voltage in Equation 7.18 increases as the logarithm of current. At sufficiently high current the drift region voltage dominates, and the current–voltage characteristic becomes linear. In this region the specific on-resistance becomes the limiting factor, and must be minimized. Minimization of in unipolar devices for a given blocking voltage will be discussed in Section 10.2.

A major advantage of the Schottky diode over the pin diode is the lower at a given . Roughly speaking, the junction voltage drop in a SiC pin diode at high currents is close to the bandgap energy, or about 3 V, whereas in a Schottky diode it is close to the barrier height, or around 0.5–1 V. Figure 7.6 shows the current–voltage characteristics of a SiC SBD and a SiC pin diode for a designed blocking voltage of 2400 V. The bend-over in the SBD characteristics at high currents is due to the resistance of the lightly-doped drift region. In the case of the pin diode, the drift region resistance is reduced by conductivity modulation, as will be discussed in the next section. We see that for currents below , the SBD has a lower voltage drop, and hence a lower on-state power dissipation at a given current.

The most important advantage of the SBD over the pin diode, and the main reason for using the Schottky diode, is the lack of minority carrier injection, leading to a very fast turn-off and low switching energy . For this reason, SiC SBDs are now being used in place of silicon pin diodes in high-frequency applications such as switched-mode power supplies, where switching loss is an issue. This is illustrated in Figure 7.7, which shows reverse recovery transients for a silicon pin diode and a Ni/4H-SiC Schottky diode at 150 °C in an inductively-loaded test circuit driven by a silicon IGBT (insulated gate bipolar transistor) [6]. The recovery transient of the Schottky diode is very short due to its lack of stored charge.

The very small switching loss of the SBD has to be balanced against the larger reverse leakage current that can lead to non-negligible off-state power dissipation. Reverse leakage in a Schottky diode is primarily due to thermionic field emission of carriers from the metal into the semiconductor, and is exacerbated by the barrier-lowering effect. The reverse currents of Ni and Ti Schottky diodes on 4H-SiC are shown in Figure 7.8 at several temperatures [1]. The reverse current is higher for the Ti diode due to its lower barrier height , and the current increases with temperature, as predicted by Equation 7.18. By comparison, the reverse leakage in a pin diode is due primarily to thermal generation, and is extremely small in SiC due to the wide bandgap.

Taking all these factors into account, the performance of SiC SBDs can be quantitatively compared to SiC pin diodes as follows: First select a blocking voltage , and design both SBD and pin diode to meet this specification. Then calculate the on-state power dissipation as a function of on-state current density . Next calculate the switching energy as a function of using computer simulations. Then use Equation 7.17 to calculate the maximum current density at each frequency such that the total power dissipation equals the specified package limit, for example, . At any given switching frequency and blocking voltage, the device with the higher current density is the preferred device. Using this procedure we can construct a map of relative performance of the SiC SBD and SiC pin diode in a two-dimensional parameter space of blocking voltage and switching frequency. Such a comparison is shown in Figure 7.9 [7]. Here we compare 4H-SiC Schottky diodes and pin diodes at several package thermal limits, assuming a 50% duty cycle and a 50% derating factor on blocking voltage. In regions above the lines, the SBD meets the blocking voltage and switching frequency specifications with a higher than the pin diode, and hence is the preferred device. The SBD is the better device at low blocking voltages and high switching frequencies, whereas the pin diode is better at high blocking voltages and low frequencies. For a package thermal limit of 200 W/cm², the SBD is preferred at any blocking voltage if the switching frequency is above about 8 kHz.

It is reasonable to ask, “If Schottky diodes are preferred over pin diodes at high switching frequencies, why not simply use silicon Schottky diodes?” It turns out that silicon SBDs are not suitable for high-voltage applications because of their high reverse leakage currents. SiC Schottky diodes have a significant advantage over silicon SBDs in terms of reverse leakage current due to the higher barrier heights in SiC. In 4H-SiC, can theoretically be as large as half the bandgap, or 1.6 V, whereas in silicon is limited to 0.56 V. Since reverse leakage scales exponentially with , the additional of barrier height in SiC reduces the reverse current by 17 orders of magnitude at room temperature. The limited barrier height effectively restricts silicon SBDs to applications where the required blocking voltage is very low.

7.3 pn and pin Junction Diodes

PN and pin diodes are junction diodes whose doping profiles and band diagrams are shown in Figure 7.10. PN diode theory is covered in elementary semiconductor device textbooks and the equations will not be derived here. Because of their importance in power switching applications, our discussion will concentrate on pin diodes. PiN diodes are used for power switching because a thick, lightly-doped region is needed to produce a high blocking voltage, as can be seen in Figure 7.3. As an illustrative example, Figure 7.3 shows that to achieve a plane-junction breakdown of 3.5 kV requires a thick drift region doped below . In practical terms, we will refer to such a lightly-doped region as an “i” region, even though it is not truly intrinsic.

In a pn diode under forward bias, the applied terminal voltage lowers the potential barriers confining electrons to the n region and holes to the p region. As a result, electrons from the n region flow into the p region where they are minority carriers, while holes from the p region flow into the n region where they are minority carriers. The current is determined by the rate at which electrons injected into the p region and holes injected into the n region can diffuse away from the junction. Assuming the minority carrier densities are low compared to the majority carrier densities (“low-level injection”), these diffusion rates are calculated by solving the minority carrier diffusion equations in the respective n and p neutral regions. To do this, it is convenient to express the electron and hole densities in terms of their equilibrium values plus their deviations from equilibrium,

7.22

where are the total carrier densities, are the carrier densities in equilibrium, and are the excess carrier densities, that is, the deviations from equilibrium. The minority carrier diffusion equations in one dimension can then be written

7.23

where are the diffusion coefficients for electrons and holes, are the lifetimes of electrons and holes as minority carriers, and is the generation rate due to light, if the sample is illuminated. The first term on the right-hand side is the rate of change of the carrier density due to diffusion, the second term is the rate of change due to recombination/generation, and the third term is the rate of change due to photogeneration. In steady-state, the time derivatives on the left-hand side are zero, and the general solutions can be written:

7.24

where are defined as the minority carrier diffusion lengths. The constants and are chosen so that the solutions satisfy the boundary condition imposed by the “law of the junction”, namely that the product within the depletion region be given by

7.25

where is the intrinsic carrier concentration and is the applied voltage, or equivalently, the splitting of the quasi-Fermi levels across the junction. Solution of the minority carrier diffusion equations subject to these boundary conditions in the dark leads directly to the Shockley diode equation

7.26

Here, and are the ionized doping concentrations of the p- and n-sides of the junction, respectively. In 4H-SiC, the p-type dopants have relatively high ionization energies, and are not fully ionized at room temperature. The n-type dopants are shallow levels, and are nearly 100% ionized at room temperature and above. Incomplete ionization in 4H-SiC is discussed more fully in Appendix A. The diffusion lengths in Equation 7.26 are given by

7.27

where are the electron and hole minority carrier lifetimes. Equation 7.26 accounts for diffusion currents under both forward- and reverse-bias conditions, provided low-level injection can be assumed, that is, the forward voltage is not too large. An additional term needs to be added to account for generation–recombination in the depletion region, but this term is only important at low currents and will not be needed for this discussion.

Similarly, in a pin diode, forward current consists of electrons that flow from the region into the “i” layer and holes that flow from the region into the “i” layer. Here the similarity to the pn diode ends, because the minority carrier densities in the “i” layer immediately exceed the doping density, resulting in high-level injection conditions that preclude the use of the minority carrier diffusion equations. Instead, we must solve the electron and hole continuity equations in a self-consistent manner. Fortunately, by making some simple assumptions we can arrive at the high-level equivalent of the minority carrier diffusion equations, namely, the ambipolar diffusion equation. This equation can then be solved in the “i” region to obtain information on carrier densities, electrostatic potential, and current. The development is straightforward, but the reader who is more interested in the “bottom line” can skip ahead to Equation 7.39 without loss of understanding.

7.3.1 High-Level Injection and the Ambipolar Diffusion Equation

Assuming uniform doping and one-dimensional current flow, the continuity equations for electrons and holes can be written

7.28

where is the local electron-hole net generation rate (or recombination rate, if negative), and are the electron and hole current densities given by

7.29

Inserting Equation 7.29 into Equation 7.28 yields

7.30

We now assume that charge neutrality holds at every point, that is, that the electron and hole densities adjust so that at every point . This is equivalent to assuming the electric field is uniform with position. For simplicity, we also assume the sample is in the dark, so only consists of thermal generation/recombination. We then multiply Equations 7.30 by and respectively, add the two equations, and use the Einstein relation: . The result is the desired ambipolar diffusion equation,

7.31

Here, is the ambipolar diffusion coefficient given by

7.32

and is the ambipolar lifetime given by

7.33

Equation 7.31 is written in terms of , but since we have assumed , it applies to as well.

To apply Equation 7.31 to the “i” region of a pin diode under forward bias in the dark, we assume high-level injection exists so that the excess carrier densities are much larger than their equilibrium values, that is, and . This allows us to set and . Assuming charge neutrality, , and we can write

7.34

The Shockley–Read–Hall thermal generation/recombination rate is given by

7.35

where

7.36

for R–G centers at energy in the bandgap. Under high-level injection conditions, Equation 7.35 can be simplified to

7.37

where the ambipolar lifetime defined by Equation 7.33 becomes

7.38

The ambipolar diffusion equation given by Equation 7.31 can now be written

7.39

Equation 7.39 has the same form as the familiar minority-carrier diffusion equations used under low-level injection conditions, Equation 7.23, with the coefficients replaced by , the coefficients replaced by , and set to zero. and are computable constants given by Equations 7.34 and 7.38, respectively.

7.3.2 Carrier Densities in the “i” Region

Having derived the ambipolar diffusion equation in a form to describe the “i” region of the pin diode under high-level injection conditions, we now wish to solve Equation 7.39 subject to the appropriate boundary conditions. The situation is illustrated in Figure 7.11, where an coordinate system is defined. Assuming steady-state conditions so that , the general solution to Equation 7.39 can be written

7.40

where is the ambipolar diffusion length given by

7.41

and and are constants to be determined by the boundary conditions. Equation 7.40 and many of the equations to be developed below are written using hyperbolic functions. These functions are a convenient shorthand for the sum or difference of two exponential terms. Properties of hyperbolic functions and identities involving hyperbolic functions can be found in Appendix B. That Equation 7.40 is a solution to Equation 7.39 can be confirmed by direct substitution. We now assume unity injection efficiency at the boundaries . This allows us to set . With this insight, we can set and note that is uniform throughout the “i” region in steady state.

To establish the boundary condition at , we note that

7.42

Making use of the fact that in the “i” region due to charge neutrality, we can solve the second equation for the electric field at :

7.43

Substituting Equation 7.43 into the first Equation 7.42 and solving for at yields the desired boundary condition at ,

7.44

Using a similar approach at , we obtain the second boundary condition as

7.45

Returning to the general solution, Equation 7.40, we apply the boundary conditions in Equations 7.44 and 7.45 to eliminate the constants and , and after some algebra we find that

7.46

where

7.47

represents the fractional asymmetry in electron and hole mobilities. Figure 7.12 shows the carrier densities in the “i” region normalized to the pre-factor in Equation 7.46, for several ratios of _. The carrier distributions become asymmetrical when due to the second term in brackets in Equation 7.46.

7.3.3 Potential Drop across the “i” Region

Having solved for the carrier densities in the “i” region as a function of current, we now wish to determine the total electrostatic potential drop across the “i” region. To do this, we first solve for the electric field in the “i” region. Let's rewrite the current Equation 7.29 in the form

7.48

Adding the two equations to get the total current,

7.49

Solving Equation 7.49 for the electric field yields

7.50

The first term in Equation 7.50 is the ohmic voltage drop due to the resistivity of the “i” region with carrier densities , and the second term represents the asymmetry due to unequal electron and hole mobilities. Note that since is proportional to current , as shown by Equation 7.46, the electric field is independent of current so long as high-level injection conditions prevail. This is remarkable, because it suggests that in high-level injection the voltage drop across the “i” region is independent of current. The total electrostatic potential drop across the “i” region can be obtained by integrating Equation 7.50 with respect to distance from to . Inserting Equation 7.46 into Equation 7.50 and integrating, we arrive at the desired result:

7.51

We use for electrostatic potentials (or band banding) and for voltages (electrochemical potentials, or equivalently, Fermi levels). Equation 7.51 is unwieldy, but it depends only upon device parameters and material constants, and is clearly independent of current. Figure 7.13 is a plot of Equation 7.51 for several values of the mobility ratio . For lightly-doped 4H-SiC, .

Figure 7.14 is a plot of electric field and electrostatic potential versus position for , using Equation 7.50 and material parameters typical of lightly-doped 4H-SiC at room temperature. The asymmetry in is due to the difference in electron and hole mobilities. Under high-level injection, the electric field in the “i” region is independent of current, and the magnitude is small . It is also positive, indicating the electric field sends electrons toward the region and holes toward the region. This is opposite to the field polarity under low-level injection. The total potential drop across the “i” layer is about 172 mV, as can be verified using Equation 7.51.

7.3.4 Current–Voltage Relationship

To complete our analysis of the forward-bias current in the pin diode, we need to add to the potential drops across the and junctions. To aid in this analysis, we refer to the schematic band diagram of Figure 7.15 showing the electron and hole quasi-Fermi levels throughout the structure. The total voltage drop across the junctions is the offset between on the left side and on the right side. The electrostatic potential drop across the “i” region given by Equation 7.51 is the total band bending across the “i” region. We designate as the difference between and at , and as the difference between and at . These are known as the chemical potentials for holes and electrons, respectively. We can obtain the total voltage drop by adding , and . Working first on the junction, we note that

7.52

which can be rearranged to yield

7.53

Similarly, at the junction we find that

7.54

Clearly

7.55

where and can be obtained from Equation 7.46. When evaluated in equilibrium, Equation 7.55 represents the built-in potential of the junction. Equation 7.55 can be rearranged to yield

7.56

where is the applied terminal voltage, and we have made use of the fact that . Obtaining expressions for and from Equation 7.46 and inserting into Equation 7.56, we find that the left side of Equation 7.56 is proportional to ². Taking the square root and solving for yields

7.57

where is given by

7.58

and is given by

7.59

Equation 7.59 evaluates to a constant that depends only on device and material parameters. Likewise, evaluates to a constant, using Equation 7.51 for . The current–voltage relationship is then given by Equation 7.57 (to which must be added the voltage drop across the substrate). Note the ideality factor of 2 in the exponent of Equation 7.57. This is typical of conduction under high-level injection conditions.

Figure 7.16 shows electron current, hole current, and total current as a function of position for at a total current density of . The electron and hole currents are computed using Equation 7.48, with given by Equation 7.46. Note that the electron current goes to zero at the end of the “i” region, , where the total current is carried by holes. Similarly, the hole current goes to zero at the end of the “i” region, , where the total current is carried by electrons.

All our results depend on carrier lifetimes and mobilities in different regions of the device. In general, lifetimes increase and mobilities decrease with temperature. Mobility also decreases with doping concentration. Table 9.1 gives empirical equations for hole and electron mobilities and ambipolar lifetime as a function of doping and temperature in 4H-SiC.

7.4 Junction-Barrier Schottky (JBS) and Merged pin-Schottky (MPS) Diodes

The junction-barrier-controlled Schottky (JBS) diode and merged pin-Schottky (MPS) diode are structures that combine pin and Schottky diodes in a way that takes advantage of the best characteristics of both. At moderate forward currents the Schottky diode has a lower forward voltage drop than the pin diode, as shown in Figure 7.6. Since the SBD is a unipolar device, there is essentially no minority carrier charge storage, and the turn-off transient is very fast, as seen in Figure 7.7. These are desirable qualities, and make SBD the preferred device for blocking voltages below 2–3 kV or switching frequencies above 8–10 kHz, as shown in Figure 7.9. The main disadvantage of the SBD is the relatively large reverse leakage current caused by Schottky barrier lowering at high reverse biases, as seen in Figure 7.8. Even a small leakage current can lead to a large power dissipation in the off state, due to the high reverse voltage across the diode. This is not an issue in the pin diode, which has very low reverse leakage. With this in mind, the JBS diode is designed to behave like a Schottky diode under forward bias (to minimize on-state and switching losses) and like a pin diode under reverse bias (to minimize off-state losses). The MPS diode operates in a different mode under forward bias. We will discuss the JBS mode of operation first, then consider the MPS mode.

The structure of the JBS/MPS diode is illustrated in Figure 7.17. The metal layer on top forms ohmic contacts to the regions and Schottky contacts to the regions, so the overall device consists of interdigitated Schottky and pin diodes connected in parallel. The anode regions are spaced far enough apart that their depletion regions do not touch under zero or forward bias. This leaves a conductive path through the drift region between each Schottky contact and the substrate. As forward bias is applied, the Schottky regions conduct first since, as shown in Figure 7.6, the current density of the SBD is orders of magnitude higher than the pin diode at the same forward voltage. The Schottky regions therefore effectively clamp the voltage drop across the pin regions, and the pin regions do not conduct. As a result, virtually all the forward current is due to electrons injected from the drift region through the Schottky contact into the metal. Since the regions do not inject holes into the drift region, no minority carrier charge is stored and the turn-off transient is fast, minimizing switching loss. With no conductivity modulation, the series resistance of the drift region is determined by its thickness and doping, as given by Equation 7.6. This relatively high resistance leads to a voltage drop that dominates the total voltage drop at high currents, as illustrated by the SBD characteristics in Figure 7.6.

Before proceeding further, it is important to note that unlike the Schottky and pin diodes considered in the previous sections, the JBS/MPS diode has an interdigitated (or cellular) structure in which the lateral dimensions of the surface features are comparable to (or less than) the vertical thickness of the drift region. By comparison, Schottky and pin diodes are large-area devices, and within the interior of the diodes the current flow and electric field lines can be considered one-dimensional. Indeed, Figures 7.1 and 7.10 illustrate one-dimensional structures, and all our previous analyses were one-dimensional. The JBS/MPS diode is the first device we have considered where the one-dimensional assumption is not valid. This will also be true of the remaining power devices covered in later chapters, including the JFET (junction field-effect transistor), MOSFET (metal-oxide-semiconductor field-effect transistor), BJT (bipolar junction transistor), IGBT, and thyristor. Like the JBS/MPS diode, all these devices have interdigitated or cellular structures that require two-dimensional analysis, usually performed by computer simulation. As we study these devices, we will use one-dimensional approximations to obtain qualitative understanding, keeping in mind that a quantitative analysis must include the two-dimensional effects within the device.

With this in mind, let us now consider forward conduction in the JBS/MPS diode. Figure 7.18 illustrates the current flow lines and equipotential lines in the JBS/MPS diode under forward bias. As seen, the current spreads laterally under the anodes and the flow is decidedly two-dimensional in this region. The true specific on-resistance is higher than Equation 7.6 because the surface area that conducts is less than the total area, but the area ratio cannot be used directly because of the current spreading under the anodes. In practice, the on-resistance is best determined by computer analysis, but we can obtain a qualitative understanding by imagining (for the moment) that current flow in the pin and Schottky sections is one-dimensional in the vertical direction, and no carriers cross the dashed lines in Figure 7.17.

Proceeding under this assumption, for a given current density we can use Equations 7.53, and 7.54 to calculate the voltage drop across the pin diode, assuming full conductivity modulation in the pin section and no hole flow into the Schottky section. Likewise, we can calculate the voltage drop across the Schottky contact using Equation 7.18, and across the (unmodulated) drift region of the SBD using Equation 7.21. These voltage drops are plotted as a function of forward current in Figure 7.19. In the pin diode, the potential drop is independent of current, and is negligible. The voltage drops and across the and junctions are almost equal, and have logarithmic slopes of . The total voltage is the sum of , and , and has a logarithmic slope of . In the SBD, the potential drop across the Schottky junction has slope , and is smaller in magnitude than either or . The voltage drop across the un-modulated drift region is linear with current, and causes the total drop (dashed line) to deviate from for currents above about .

If we think now about the real two-dimensional JBS/MPS structure in Figure 7.18, we note that the potential across the junction (points C to A) and the potential across the Schottky junction (points C to B) are the same, provided there is no potential drop in the drift region between points A and B. This will certainly be true when the current is very low. From Figure 7.19, assuming and are the same, the current crossing the junction will be orders of magnitude lower than that crossing the Schottky junction. Thus there will be very little hole injection into the drift region, and negligible conductivity modulation. However, as the current increases, a lateral voltage drop will develop between points A and B. This is illustrated in Figure 7.18, where it is apparent by counting equipotential lines that the potential at point A is closer to ground (the substrate potential) than the potential at point B. Thus, the potential drop across the junction (points C and A) is greater than across the Schottky junction (points C and B). This causes the junction to begin injecting holes into the drift region, and these holes spread laterally throughout the drift region, modulating its conductivity. As current is increased, the junction accounts for an increasing fraction of the total current, and the terminal current follows the heavy shaded line in Figure 7.19.

It is important to remember that the potentials shown in Figure 7.19 are calculated ignoring the two-dimensional nature of the device, and are not quantitatively correct. However, this description helps illustrate the processes occurring in the real device. Figure 7.19 is calculated for a device with a plane-junction blocking voltage of 2.4 kV, and for currents below about most of the current flows through the SBD section and negligible minority charge is injected into the drift region. At higher currents, the lateral voltage drops under the regions are large enough that the junction turns on, injecting holes into the drift region. This reduces and allows the current to follow the characteristics of a pin diode. The regime below the cross-over point is the JBS regime, where negligible minority charge storage takes place. The regime above the cross-over point is the MPS regime, where significant minority charge storage occurs. Operation in the MPS regime reduces the on-state loss at high current densities, but the stored charge increases the switching loss.

The transition between JBS and MPS regimes depends on the design blocking voltage, and can be understood as follows. When the drift region is unmodulated, increases as the square of the designed blocking voltage, as given by Equation 7.12. This happens because, to achieve a higher blocking voltage, the drift region must be thicker and more lightly doped, both of which increase the on-resistance. For diodes with low blocking voltages, Equation 7.12 shows that is small, so a much higher current is needed before the diode turns on. Therefore, the cross-over between JBS and MPS regimes occurs at high currents (say, above ). On the other hand, when the blocking voltage is high, Equation 7.12 shows that is large, and the cross-over between JBS and MPS regimes occurs at lower currents . For this reason, low-voltage JBS/MPS diodes typically operate in the JBS regime, whereas high-voltage JBS/MPS diodes operate in the MPS regime. This is illustrated in Figure 7.20, where the characteristics of a 1.2 and a 12 kV JBS/MPS diode are compared. At a current density of for example, the 1.2 kV diode is in the JBS regime, whereas the 12 kV diode is in the MPS regime.

As reverse bias is applied to the JBS/MPS structure, the depletion regions of the anodes quickly merge under the M–S contacts, then spread downward toward the substrate. If the field lines were one-dimensional, the electric field would vary linearly with depth, as in Figure 7.1 or 7.2. In this case, the high surface field under the Schottky contact would lead to significant barrier lowering, as given by Equation 7.20. In the JBS/MPS structure, however, the electric field near the surface is two-dimensional, with many field lines terminating on the anodes, as illustrated in Figure 7.21. This reduces the surface field under the Schottky contacts, minimizing barrier lowering, and reducing the reverse leakage to levels approaching a pure pin diode. As a result, the JBS/MPS structure exhibits the desirable low reverse leakage current of a pin diode.

As with all diodes, proper edge terminations are critical to achieve a blocking voltage close to the theoretical plane-junction value. Techniques for edge terminations will be discussed in Section 10.1.

References

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