Index
Page numbers in italics indicate figures, tables and text boxes.
0-9, and Symbols
32-bit microprocessor,
454
4004 microprocessor chip,
458,
459
parts,
counter (74161, 74163),
586
tristate buffer (74244),
586
80386 microprocessor chip,
459,
460
80486 microprocessor chip,
460,
461
A
Address. see also Memory
Addressing modes
Advanced microarchitecture,
444–458
American Standard Code for Information Interchange (ASCII),
322,
323,
630,
649–650
Pulse-width modulation (PWM),
536–537
Analog-to-digital converters (ADCs),
531–533
Analytical engine, ,
chips (7408, 7411, 7421),
585
using CMOS transistors,
32–33
Application-specific integrated circuits (ASICs),
591
MIPS
Arithmetic
comparison or assignment of,
650
Assembler directives,
338
Assembler temporary register (
$at),
342
translating high-level code into,
300
translating machine language to,
309
translating to machine language,
306–307
Associativity
in Boolean algebra,
62,
63
Asynchronous resettable flip-flops definition,
116
Average memory access time (AMAT),
479,
492
B
Babbage, Charles,
Baud rate register (BRG),
518
Binary coded decimal (BCD),
258
Binary numbers
Binary to decimal conversion,
10,
10–11
Binary to hexadecimal conversion,
12
Bipolar junction transistors,
26
direct drive current,
556
Bit,
least significant,
13,
14
BlueSMiRF silver module,
548,
548
Bluetooth wireless communication,
547–548
BlueSMiRF silver module,
548
Boole, George,
equation simplification,
65–66
product-of-sums (POS) form,
60
sum-of-products (SOP) form,
58–60
Branch equal (beq)
Branch misprediction penalty,
421–422
Branch target buffer,
446
Branching
C
address fields
evolution of, in MIPS,
495
parameters
degree of associativity (
N),
486
performance of
miss rate
vs. cache parameters,
493–494
status bits
Callee-saved registers,
329
Casez, case?, in HDL,
205
horizontal blanking interval,
542
vertical blanking interval,
542
Chopper constant current drive,
556
Circuits
application-specific integrated (ASICs),
591
with two-stage pipeline,
160
Clock cycles per instruction (CPI),
444,
446
Clustered multiprocessing,
456
Combinational composition,
56
Karnaugh maps (K-maps),
75–83
Comments
Comparison
Complementary Metal-Oxide-Semiconductor Logic (CMOS),
26–34
Complex instruction set computer (CISC),
298,
347
Complexity management,
4–7
Computer Architecture (Hennessy & Patterson),
444
Computer-aided design (CAD),
71,
129
Conditional signal assignments,
181–182
Conditional statements
Consensus theorem,
62,
64
Constants
Control unit. See also ALU decoder, Main decoder
of multicycle MIPS processor,
396–408
of pipelined MIPS processor,
413–414
of single-cycle MIPS processor,
382–387
Control-flow statements
Core Duo microprocessor chip,
464
Core i7 microprocessor chip,
465
Cross-coupled inverters,
109,
110
bistable operation of,
110
Cycles per instruction (CPI),
375
D
Data Acquisition Systems (DAQs),
562–563
Datapath
single-cycle MIPS processor,
376–382
Decimal numbers,
Decimal to binary conversion,
11
Decimal to hexadecimal conversion,
13
Decoders
HDL for
Delay generation using counters,
528–529
Delaymicros function,
528
Delays, logic gates. See Propagation delay
De Morgan’s theorem,
63–64
Device under test (DUT),
220
Digital circuits,
See Logic
Digital signal processor (DSP),
457
Digital system implementation,
583–617
application-specific integrated circuits (ASICs),
591
Digital-to-analog converters (DACs),
531
Direct current (DC) transfer characteristics,
24,
25
Direct voltage drive,
554
Discipline
Discrete-valued variables,
Distributivity theorem,
63
Divide-by-3 counter
Division
MIPS signed and unsigned instructions,
345
Double-data rate memory (DDR),
266,
561
Dual inline memory module (DIMM),
561
Dual-inline packages (DIPs),
28,
583,
599
Dynamic branch predictors,
446
Dynamic data segment,
337
Dynamic memory allocation
(malloc,
free),
654–655
E
Electrically erasable programmable read only memory (EEPROM),
269
Embedded I/O (input/output) systems,
508–558
general-purpose I/O (GPIO),
513–515
microcontroller peripherals,
537–558
Equation minimization
using Boolean algebra,
65–66
Erasable programmable read only memory (EPROM),
269,
588
Exception program counter (
EPC),
343–344
Extended instruction pointer (EIP),
348
F
state transition diagram,
124,
125
comparison with latches,
118
Floating output node,
117
Floating point division (FDIV) bug,
175
Floating-point coprocessors,
457
Floating-point division (FDIV),
259
Floating-point instructions, MIPS,
346–347
formats, single- and double-precision,
256–258
special cases
Floating-point unit (FPU),
259,
461
Format conversion (
atoi,
atol,
atof),
663–664
Frequency shift keying (FSK),
548
using always/process statement,
200
preserved and non-preserved registers,
329–332
with no inputs or outputs,
325,
637
Fuse-programmable ROM,
269
G
Gated time accumulation,
529
Gates
General-purpose I/O (GPIO),
513
PIC32 ports (pins) of,
515
Global pointer (
$gp),
337
Graphics accelerators,
464
Graphics processing unit (GPU),
457
H
blocking and nonblocking assignments,
205–209
single-cycle MIPS processor,
429–440
Hardware handshaking,
523
read after write (RAW),
415,
451
solving
write after read (WAR),
451
Heterogeneous multiprocessors,
456–458
Hexadecimal numbers,
11–13
Hexadecimal to binary and decimal conversion,
11,
12
Hierarchy,
High-level programming languages,
296,
624
compiling, assembling, and loading,
336–341
translating into assembly,
300
High-performance microprocessors,
444
Homogeneous multiprocessors,
456
I
IA-32 architecture,
See x86
If statements
Immediate addressing,
333
logical operations with,
311
Implicit leading one,
256
Information, amount of,
Initializing
InitTimer1Interrupt function,
530
Input/output elements (IOEs),
274
Input/Output (I/O) systems,
506–569
Institute of Electrical and Electronics Engineers (IEEE),
257
Instruction formats, MIPS
Instruction level parallelism (ILP),
452,
455
Instruction memory (IM),
373,
411
Instruction register (IR),
391,
398
multiplication and division,
314,
345
Instructions per cycle (IPC),
375
Integer Execution Unit (IEU),
461
Integrated circuits (ICs),
599
An Investigation of the Laws of Thought (Boole),
J
K
logic minimization using,
77–83
seven-segment display decoder,
79–81
with “don’t cares,”,
81–82
L
translating assembly to machine,
306
Last-in-first-out (LIFO) queue,
327.
See also Stack
comparison with flip-flops,
109,
118
lbu, load byte unsigned,
See Loads
Least recently used (LRU) replacement,
490–491
Least significant bit (lsb),
13,
14
Least significant byte (LSB),
13,
14,
302
lhu, load half unsigned,
See Loads
Line options, compiler and command,
665–667
Liquid crystal displays (LCDs),
538–541
Little-endian bus order in HDL,
178
load half (
lh or
lhu),
345
Logic
Logic array block (LAB),
275
transistor-level implementation,
279–280
multiple-input gates,
21–22
OR-AND-INVERT (OAI) gate,
46
Lookup tables (LUTs),
270,
275
in C
in MIPS assembly
Low Voltage CMOS Logic (LVCMOS),
25
Low Voltage TTL Logic (LVTTL),
25
lui, load upper immediate,
313
M
Machine code, assembly and,
437
translating assembly language to,
306
Magnitude comparator,
247
Master-slave flip-flop,
114
state transition and output table,
134
state transition diagrams,
133
Mean time between failure (MTBF),
153–154
Medium-scale integration (MSI) chips,
584
Memory map
Memory-mapped I/O
communicating with I/O devices,
507–508
Metal-oxide-semiconductor field effect transistors (MOSFETs),
26
Microchip In Circuit Debugger 3 (ICD3),
513
64-pin TQFP package in,
511
operational schematic of,
512
virtual memory map of,
510
Microcontroller peripherals,
537–558
Bluetooth wireless communication,
547–548
Microcontroller units (MCUs),
508
Microprocessors, ,
13,
295
architectural state of,
310
Millions of instructions per second,
409
microarchitectures
vs. x86 architecture,
348
formats
multiplication and division,
314,
345
MIPS registers,
Misses
Modularity,
Modules, in HDL
state transition and output table,
134
state transition diagrams,
133
Most significant bit (msb),
13,
14
Most significant byte (MSB),
13,
14,
302
Motors
mul, multiply, 32-bit result,
314
mult, multiply, 64-bit result,
314
Multichip module (MCM),
566
Multilevel combinational logic,
69–73.
See also Logic
Multiple-output circuit,
68–69
HDL for
symbol and truth table,
83
signed and unsigned instructions,
345
Multiprocessors
Multi-Protocol Synchronous Serial Engine (MPSSE),
563,
563
Multithreaded processor,
455
N
Nested if/else statement,
640
Nonarchitectural state,
372
Nonpreserved registers,
329,
330
Number conversion
binary to hexadecimal,
12
decimal to binary,
11,
13
decimal to hexadecimal,
13
hexadecimal to binary and decimal,
11,
12
taking the two’s complement,
16
decimal,
estimating powers of two,
14
negative and positive,
15
O
One-bit dynamic branch predictor,
446–447
One-time programmable (OTP),
584
Operands
immediates (constants),
304,
313
Operators
OR-AND-INVERT (OAI) gate,
46
Out-of-order execution,
453
Overflow
P
Perfect induction, proving theorems using,
64–65
multi-cycle MIPS processor,
405–407
processor comparison,
428
single-cycle MIPS processor,
388–389
Peripheral bus clock (PBCLK),
512
Peripheral Component Interconnect (PCI),
560
Personal computer (PC),
See x86
Personal computer (PC) I/O systems,
558–564
Phase locked loop (PLL),
544
Physical address extension,
567
Physical page number (PPN),
499
Plastic leaded chip carriers (PLCCs),
599
Positive edge-triggered flip-flop,
114
Power processor element (PPE),
457
Printed circuit boards (PCBs),
601–602
Priority
Processor-memory gap,
477
Processor performance comparison
pipelined MIPS processor,
428
Product-of-sums (POS) form,
60
transistor-level implementation,
280
Programmable logic devices (PLDs),
588
Programming
multiplication and division,
314
Pulse-Width Modulation (PWM),
536–537
Q
Quiescent supply current,
34
R
transistor-level implementation,
279–280
Reduced instruction set computer (RISC),
298
Register file (RF)
in pipelined MIPS processor (write on falling edge),
412
MIPS register descriptions,
299–300
use in MIPS processor,
373
Register-only addressing,
333
Regularity,
Replacement policies,
504
Resettable flip-flops,
116
Rotations per minute (RPM),
549
S
Schematics, rules of drawing,
31,
67
Selected signal assignment statements,
182
industry, sales,
flip-flops,
114–118.
Also see Registers
Serial communication, with PC,
525–527
Serial Data In (SDI),
516
Serial Data Out (SDO),
516
Serial Peripheral Interface (SPI),
515–521
connection between PIC32 and FPGA,
519
ports
Serial Data In (SDI),
516
Serial Data Out (SDO),
516
slave circuitry and timing,
520
set if less than immediate (
slti),
345
set if less than immediate unsigned (
sltiu),
345
set if less than (slt)
set if less than unsigned (
sltu),
345
Seven-segment display decoder,
79–82
Signed and unsigned instructions,
344–345
Signed binary numbers,
15–19
Silicon dioxide (SiO2),
28
Simple programmable logic devices (SPLDs),
274
Simulation waveforms,
176
Single-cycle MIPS processor,
376–389
Single instruction multiple data (SIMD),
447,
454,
463
Small-scale integration (SSI) chips,
584
Special function registers (SFRs),
509
Spinstepper function,
557
during recursive function call,
331
storing additional arguments on,
332–333
storing local variables on,
332–333
format conversion (
atoi,
atol,
atof),
663–664
Static branch prediction,
446
Static random access memory (SRAM),
266,
267
Stores
store half (
sh or
shu),
345
signed and unsigned instructions,
344–345
Sum-of-products (SOP) form,
58–60
Supply voltage,
22.
See also VDD
Switch/case statements
in HDL. see Case statement
Synchronous dynamic random access memory (SDRAM),
267
Synchronous resettable flip-flops,
116
Synergistic processor elements (SPEs),
457
Synergistic Processor Unit (SPU) ISA,
458
accessing parts of busses,
188,
192
bad synchronizer with blocking assignments,
209
delays (in simulation),
189
finite state machines (FSMs),
209–213
using always/process,
200
using nonblocking assignments,
208
seven-segment display decoder,
201
truth tables with undefined and floating inputs,
187,
188
T
Taking the two’s complement,
16–17
Thin Quad Flat Pack (TQFP),
510
Thin small outline package (TSOP),
599
Thread level parallelism (TLP),
455
Timing
of combinational logic,
88–95
with clock skew. See clock skew
Translation lookaside buffer (TLB),
502–503
Transmission Control Protocol and Internet Protocol (TCP/IP),
561
characteristic impedance (Z
0),
612–613
reflection coefficient (
kr),
613–614
series and parallel terminations,
610–612
seven-segment display decoder,
79
with undefined and floating inputs,
187–188
Two-bit dynamic branch predictor,
447
Two-cycle latency of
lw,
418
Two’s complement numbers,
16–18
U
Unit under test (UUT),
220
Universal Asynchronous Receiver Transmitter (UART),
521–527
hardware handshaking,
523
V
Vanity Fair (Carroll),
76
Variable-shift instruction,
313
Very High Speed Integrated Circuits (VHSIC),
175.
See also VHDL
VGA (Video Graphics Array) monitor,
541–547
VHSIC Hardware Description Language (VHDL),
173–175
accessing parts of busses,
188,
192
bad synchronizer with blocking assignments,
209
delays (in simulation),
189
finite state machines (FSMs),
209–213
using always/process,
200
using nonblocking assignments,
208
seven-segment display decoder,
201
truth tables with undefined and floating inputs,
187,
188
cache terms comparison,
497
replacement policies,
504
translation lookaside buffer (TLB),
502–503
Virtual page number (VPN),
499
W
Whitmore, Georgiana,
Wireless communication, Bluetooth,
547–548
Word-addressable memory,
301,
302
Write after write (WAW) hazard,
451
X
x86
memory addressing modes,
349
memory system, evolution of,
565
Z